Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Election/Restrictions
Applicant’s election without traverse of group I, claims 1-12, 20 in the reply filed on 11/11/25 is acknowledged. Claims 13-19 are withdrawn from further consideration by the examiner, 37 C.F.R. 1.142(b) as being drawn to a non-elected invention. Applicant is reminded that upon the cancellation of claims to a non-elected invention, the inventorship must be amended in compliance with 37 CFR 1.48(b) if one or more of the currently named inventors is no longer an inventor of at least one claim remaining in the application. Any amendment of inventorship must be accompanied by a diligently-filed petition under 37 CFR 1.48(b) and by the fee required under 37 CFR 1.17(h).
Information Disclosure Statement
The information disclosure statements filed 6/29/23 have been considered.
Oath/Declaration
Oath/Declaration filed on 6/29/23 has been considered.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-12 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by SIO et al. (U.S. Patent Publication No. 2020/0135640).
Referring to figures 2-9, SIO et al. teaches a structure comprising:
metal lines (TM1/TM2/TM3; 145a/b/c/d/e; 645a/b/c) and viabars (140a/b/c/d/e) that surround a periphery of an active area of a semiconductor device;
at least one viabar (150a/150b) that extends through multiple layers of the semiconductor device, wherein the at least one viabar connects a metal line of one layer of the structure with a metal line of another layer of the structure (M1-M3; M2-M4); and
a connection viabar (140b) that terminates at a metal line of a layer between the one layer of the structure and the another layer of the structure, wherein a thickness of the connection viabar (140a) is less than a thickness of the at least one viabar (150a, see figure 2).
Regarding to claim 2, a thickness of the metal line of the one layer is greater
than a thickness of the metal line of the another layer; and a thickness of the one layer is greater than a thickness of the another layer (see paragraph# 48, figures 2, 6).
Regarding to claim 3, the at least one viabar (150a) is between a first metal line of a first layer of the structure (M1) and a second metal line of the first layer of the structure (M2, see figure 2).
Regarding to claim 4, the metal line of the one layer (M3) is above the first metal line (M1) of the first layer, and the metal line of the another layer (M4) is below the first metal line of the first layer (M1, see figures 2-9).
Regarding to claim 5, the at least one viabar (150) is between a first metal line (M1) of a second layer of the structure and a second metal line of the second layer of the structure (M3).
Regarding to claim 6, a thickness of the first metal line of the first layer and the second metal line of the first layer is greater than a thickness of the first metal line of the second layer and the second metal line of the second layer; and a thickness of the first layer is greater than a thickness of the second layer (see paragraph# 48).
Regarding to claim 7, a thickness of the metal line of the one layer is substantially the same as a thickness of the first metal line of the first layer and the second metal line of the first layer; and the thickness of the first metal line of the second layer and the second metal line of the second layer is substantially the same as a thickness of the metal line of the another layer (see paragraph# 48).
Regarding to claim 8, at least one other viabar that extends through multiple layers of the semiconductor device, wherein the at least one other viabar connects the second metal line of the first layer of the structure to the metal line of the another layer of the structure; wherein the at least one other viabar is between the second metal line of the second layer of the structure and a third metal line of the second layer of the structure (see figures 2-9).
Regarding to claim 9, the at least one viabar (150) and the at least one other viabar (140) are staggered within the structure such that the at least one viabar (150) extends through more layers of the structure than the at least one other viabar (140, see figures 2-9).
Regarding to claim 10, at least one other viabar (150) that extends through multiple layers of the semiconductor device, wherein the at least one other viabar (140) connects another metal line (M4) of the one layer of the structure with the metal line of the another layer of the structure; wherein the at least one viabar (150) is between a first metal line (M3) of a first layer of the structure and a second metal line (M1) of the first layer of the structure; wherein the at least one other viabar (150) is between the second metal line (M2) of the first layer of the structure and a third metal line of the first layer of the structure (M4); wherein the metal line of the one layer (M4) and the another metal line of the one layer (M3) are above: the first metal line (M3) of the first layer, the second metal line (M1) of the first layer, and the third metal line (M4) of the first layer; wherein the metal line of the another layer of the structure is below: the first metal line (M3) of the first layer, the second metal line (M1) of the first layer, and the third metal line of the first layer (M4, see figures 2-9).
Regarding to claim 11, an extension viabar (150) that extends through multiple layers of the semiconductor device; wherein the viabar (150) connects the second metal line of the first layer of the structure to a metal line that is in a layer above the metal line of the one layer of the structure and the another metal line of the one layer of the structure; wherein the viabar is between the metal line of the one layer of the structure and the another metal line of the one layer of the structure (see figures 2-9).
Regarding to claim 12, a thickness of the metal line that is in the layer above the metal line of the one layer of the structure and the another metal line of the one layer of the structure is greater than a thickness of the second metal line of the first layer of the structure (see paragraph# 48, figure 2).
Claim(s) 20 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Lanzillo et al. (U.S. Patent Publication No. 2024/0153867).
Referring to figures 4-5, Lanzillo et al. teaches a mechanical crackstop barrier comprising viabar mesh patterns (see paragraph# 37) that extend across multiple back end of line layers and terminate on different metal levels so that a seam of a metal line (M) to a viabar (SV) is staggered through a back end of line dielectric stack height (20, see figures 4-5).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Thanh Nguyen whose telephone number is (571) 272-1695, or by Email via address Thanh.Nguyen@uspto.gov. The examiner can normally be reached on Monday-Thursday from 6:00AM to 3:30PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Yara Green, can be reached on (571) 270-3035. The fax phone number for this Group is (571) 273-8300.
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/THANH T NGUYEN/ Primary Examiner, Art Unit 2893