DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is responsive to the following communications: the Application filed June 29, 2023.
Claims 1-20 are pending. Claims 1, 10 and 17 are independent.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-9 and 17-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Rajaei et. al. (“Dynamic Memory and Sequential Logic Design using Negative Capacitance FinFETs”; hereinafter “Rajaei”).
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Regarding independent claim 1, Rajaei discloses an apparatus (Fig. 5(b)) comprising:
an input stage of a latch (see First Examiner’s Markup Rajaei’s Figure 5(b)) to receive input data information and clock information (Fig. 5(b): “D” and CLK/CLKb);
a memory node coupled to the input stage to store data information based on the input data information (Fig. 5(b): SN);
an output stage of the latch (see First Examiner’s Markup Rajaei’s Figure 5(b)) coupled to the memory node (Fig. 5(b): SN) and including an output node to provide output data information (Fig. 5(b): Q) based on the data information stored at the memory node (Fig. 5(b): SN);
a first circuit to provide a first circuit path (Fig. 5(b): Psch) between the memory node (Fig. 5(b): SN) and a first node in the input stage (see First Examiner’s Markup Rajaei’s Figure 5(b)); and
a second circuit to provide a second circuit path (Fig. 5(b): Nsch) between the memory node (Fig. 5(b): SN) and a second node in the input stage (see First Examiner’s Markup Rajaei’s Figure 5(b)).
Regarding claim 2, Rajaei discloses wherein the input stage includes transistors coupled in series with each other between a first supply node and a second supply node (see Second Examiner’s Markup Rajaei’s Figure 5(b)), the transistors include respective gates, and at least one of the gates of the transistors is to receive the input data information (Fig. 5(b): two transistors with gates receiving input “D”).
Regarding claim 3, Rajaei discloses wherein at least one of the gates of the transistors is to receive the clock information (Fig. 5(b): transistors receiving at the gates input CLK and CLKb).
Regarding claim 4, Rajaei discloses wherein the first circuit includes a first additional transistor (Fig. 5(b): Psch), the first additional transistor including a first terminal coupled to the memory node (Fig. 5(b): Psch including a first terminal electrically coupled to SN through transistor receiving CLKb), a second terminal coupled to the first node in the input stage (Fig. 5(b): Psch including a second terminal electrically coupled to the first node, as shown in First Examiner’s Markup Rajaei’s Figures 5(b)), and a gate coupled to the output node (Fig. 5(b): gate of Psch electrically coupled to “Q” through the buffer).
Regarding claim 5, Rajaei discloses wherein the second circuit includes a second additional transistor (Fig. 5(b): Nsch), the second additional transistor including a first terminal coupled to the memory node (Fig. 5(b): Nsch including a first terminal electrically coupled to SN through transistor receiving CLK), a second terminal coupled to the second node in the input stage (Fig. 5(b): Nsch including a second terminal electrically coupled to the second node, as shown in First Examiner’s Markup Rajaei’s Figures 5(b)), and a gate coupled to the output node (Fig. 5(b): gate of Nsch electrically coupled to “Q” through the buffer).
Regarding claim 6, Rajaei discloses wherein the input stage includes:
a first clock node to receive a first clock signal of the clock information (Fig. 5(b): CLKb);
a second clock node to receive a second clock signal of the clock information (Fig. 5(b): CLK);
a first transistor having a gate coupled to the first clock node (Fig. 5(b): transistor receiving at gate CLKb); and
a second transistor having a gate coupled to the second clock node (Fig. 5(b): transistor receiving at gate CLK).
Regarding claim 7, Rajaei discloses wherein the input stage includes
a data node to receive the input data information (Fig. 5(b): “D”);
a first transistor coupled between a first supply node and the first node, the first transistor including a gate coupled to the data node (Fig. 5(b): first transistor coupled between CLK and Psch and including a gate coupled to “D”);
a second transistor coupled between the first node and the memory node, the second transistor including a gate to receive a first clock signal of the clock information (Fig. 5(b): transistor including a gate receiving CLKb and coupled between Psch and SN);
a third transistor coupled between the memory node and the second node; the third transistor including a gate to receive a second clock signal of the clock information (Fig. 5(b): transistor including a gate receiving CLK and coupled between SN and Nsch); and
a fourth transistor coupled between the second node and the second supply node, the fourth transistor including a gate coupled to the data node (Fig. 5(b): transistor coupled between Nsch and CLKb including a gate coupled to “D”).
Regarding claim 8, Rajaei discloses wherein the apparatus comprises circuitry, the circuitry including at least one of a clock distribution network and a data path (Fig. 5(b): circuitry that inputs signals CLKs and “D” not shown in figure), and wherein the latch is a dynamic latch, and the at least one of a clock distribution network and a data path includes the dynamic latch (see V. Conclusion).
Regarding claim 9, Rajaei discloses wherein the apparatus comprises a processor, the processor including the input stage, the memory node, the output stage, the first circuit, and the second circuit (see V. Conclusion and Fig. 5(b)).
Regarding independent claim 17, Rajaei discloses a method comprising:
receiving input data information at a data input node of a dynamic latch during a first state of the dynamic latch (Fig. 5(b): “D”);
storing data information at a node of the dynamic latch during the first state, the data information at the node having a value based on a value of the input data information (Fig. 5(b): “SN”); and
activating a circuit path coupled between the node and a supply node during a second state of the dynamic latch (Fig. 5(b): Psch, Nsch and output “Q”).
Regarding claim 18, Rajaei discloses wherein activating the circuit path includes turning on a transistor of the circuit path (Fig. 5(b): turning on Psch or Nsch); and
wherein a gate of the transistor is controller based on a value of the data information at the node in the second state (Fig. 5(b): turning on transistor Psch or Nsch based on SN).
Regarding claim 19, Rajaei discloses wherein activating the circuit path includes turning on a p-type transistor of the circuit path (Fig. 5(b): Psch).
Regarding claim 20, Rajaei discloses wherein activating the circuit path includes turning on an n-type transistor of the circuit path (Fig. 5(b): Nsch).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 10-11 and 14-16 are rejected under 35 U.S.C. 103 as being unpatentable over Rajaei et. al. (“Dynamic Memory and Sequential Logic Design using Negative Capacitance FinFETs”; hereinafter “Rajaei”) in view of Holm (U.S. 2020/0143851).
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Regarding independent claim 10, Rajaei teaches an apparatus (Fig. 5(b)) comprising:
an input stage of a latch (see First Examiner’s Markup Rajaei’s Figure 5(b)) to receive input data information and clock information (Fig. 5(b): “D” and CLK/CLKb), the input stage coupled to a first supply node and a second supply node (see Second Examiner’s Markup Rajaei’s Figure 5(b));
a memory node coupled to the input stage to store data information based on the input data information (Fig. 5(b): SN);
an output stage of the latch (see First Examiner’s Markup Rajaei’s Figure 5(b)) coupled to the memory node (Fig. 5(b): SN) and including an output node to provide output data information (Fig. 5(b): Q) based on the data information stored at the memory node (Fig. 5(b): SN);
a first circuit to provide a first circuit path (Fig. 5(b): Psch) between the memory node (Fig. 5(b): SN) and the first supply node (see Second Examiner’s Markup Rajaei’s Figure 5(b));
a second circuit to provide a second circuit path (Fig. 5(b): Nsch) between the memory node (Fig. 5(b): SN) and the second supply node (see Second Examiner’s Markup Rajaei’s Figure 5(b)); and
a third circuit (Fig. 5(b): buffer that outputs “Q”).
However, Rajaei is silent with respect to a third circuit to provide control information to the first circuit and the second circuit based on the information stored at the memory node.
Similar to Rajaei, Holm teaches an apparatus comprising a latch to receive input data information and clock information (Fig. 3A: receiving “D”, CLKB and CLK) comprising a first circuit (Fig. 3A: P4) and a second circuit (Fig. 3A: N3).
Furthermore, Holm teaches a third circuit to provide control information to the first circuit and the second circuit based on the information stored at the memory node (Fig. 3A: P5 and N5 provide signal to the gates of P4 and N3).
Since Holm and Rajaei are from the same field of endeavor, the teachings described by Holm would have been recognized in the pertinent art of Rajaei.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Holm with the teachings of Rajaei for the purpose of causes the latch circuit to hold data stably, see Holm’s page 3, par. 0043.
Regarding claim 11, Rajaei in combination with Holm teaches the limitations with respect to claim 10.
Furthermore, Rajaei teaches wherein the first circuit includes at least one transistor coupled between the memory node and the first supply node (Fig. 5(b): Psch coupled between SN and CLK);
the second circuit includes at least one transistor coupled between the memory node and the second supply node (Fig. 5(b): Nsch coupled between SN and CLKb).
Furthermore, Holm teaches the third circuit includes an inverter (Fig. 3A: P5/N5), the inverter including an input node coupled to the memory node (Fig. 3A: inverter P5/N5 including an input node couples to Internal node) and an output node coupled to a gate of a transistor of the first circuit and a gate of a transistor of the second circuit (Fig. 3A: inverter P5/N5 including an output node coupled to gate of P4 and N3).
Regarding claim 14, Rajaei in combination with Holm teaches the limitations with respect to claim 10.
Furthermore, Rajaei teaches the memory node is configured to receive data information during a first phase of a clock signal of the clock information; and the memory node is configured to retain the data information during a second phase of the clock signal (Fig. 5(b): SN).
Regarding claim 15, Rajaei in combination with Holm teaches the limitations with respect to claim 10.
Furthermore, Rajaei teaches wherein the input stage includes:
a first p-type transistor coupled between a first supply node and the first node, the first p-type transistor including a gate to receive the input data information (Fig. 5(b): first transistor coupled between CLK and Psch and including a gate coupled to “D”);
a second p-type transistor coupled between the first node and the memory node, the second p-type transistor including a gate to receive a first clock signal of the clock information (Fig. 5(b): transistor including a gate receiving CLKb and coupled between Psch and SN);
a first n-type transistor coupled between the memory node and the second node; the first n-type transistor including a gate to receive a second clock signal of the clock information (Fig. 5(b): transistor including a gate receiving CLK and coupled between SN and Nsch); and
a second n-type transistor coupled between the second node and the second supply node, the second n-type transistor including a gate to receive the input data information (Fig. 5(b): transistor coupled between Nsch and CLKb including a gate coupled to “D”).
Regarding claim 16, Rajaei in combination with Holm teaches the limitations with respect to claim 10.
Furthermore, Holm teaches a connector and an integrated circuit (IC) chip coupled to the connector, the IC chip including the input stage, the memory node, the output stage, the first circuit, the second circuit, and the third circuit, wherein the connector conforms with at least one of Universal Serial Bus (USB), High-Definition Multimedia Interface (HDMI), Thunderbolt, Peripheral Component Interconnect Express (PCIe), and Ethernet specifications (see page 1, par. 0012-0017).
Allowable Subject Matter
Claims 12-13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
With respect to claim 12, there is no teaching or suggestion in the prior art of record to provide the recited first circuit includes a first current generator coupled between the memory node and the first supply node; and the second circuit includes a second current generator coupled between the memory node and the second supply node.
With respect to claim 13, there is no teaching or suggestion in the prior art of record to provide the recited first circuit is part of a first current mirror; and the second circuit is part of a second current mirror.
Conclusion
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/Alfredo Bermudez Lozada/ Primary Examiner, Art Unit 2825
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