DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 1/14/2025 was filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2 and 8-11 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ong (US 2023/0209797).
Regarding claim 1, Ong discloses, in at least figures 2A-4B and related text, an apparatus, comprising:
a first transistor (upper 130, [29], figure 2A), comprising a first channel region (260 under 285 of upper 130, [29], [31], figures) with a first width (W2, [29]), and a second transistor (upper 125, [29], figure 2A), comprising a second channel region (260 under 285 of upper 125, [29], [31], figures) with a second width (W1, [29]) greater than the first width (W2, [29]);
a third transistor (lower 130, [29], figure 2A), comprising a third channel region (260 under 285 of lower 130, [29], [31], figures) with a third width (W2, [29]), and a fourth transistor (lower 125, [29], figure 2A), comprising a fourth channel region (260 under 285 of lower 125, [29], [31], figures) with a fourth width (W1, [29]) greater than the third width (W2, [29]);
first (upper 260, [29], figure 2A) and second (lower 260, [29], figure 2A) semiconductor structures, extending in a first direction (x direction, figures), wherein the first semiconductor structure (upper 260, [29], figure 2A) comprises the first (260 under 285 of upper 130, [29], [31], figures) and second (260 under 285 of upper 125, [29], [31], figures) channel regions and a first sidewall (sidewall in upper 290, [29], figures) therebetween and the second semiconductor structure (lower 260, [29], figure 2A) comprises the third (260 under 285 of lower 130, [29], [31], figures) and fourth (260 under 285 of lower 125, [29], [31], figures) channel regions and a second sidewall (sidewall in lower 290, [29], figures) therebetween; and
a stripe of material (280, [31]) between and adjacent the first (sidewall in upper 290, [29], figures) and second (sidewall in lower 290, [29], figures) sidewalls, spanning the first (upper 260, [29], figure 2A) and second (lower 260, [29], figure 2A) semiconductor structures in a second direction (y direction, figures) perpendicular to the first direction (x direction, figures).
Regarding claim 2, Ong discloses the apparatus of claim 1 as described above.
Ong further discloses, in at least figures 2A-4B and related text, a transition portion (upper 290, [29], figures) of the first semiconductor structure (upper 260, [29], figure 2A) is under the stripe of material (280, [31]) and between the first (260 under 285 of upper 130, [29], [31], figures) and second (260 under 285 of upper 125, [29], [31], figures) channel regions;
the transition portion (upper 290, [29], figures) has the first width (W2, [29]) on a first side adjacent the first channel region (260 under 285 of upper 130, [29], [31], figures); and
the transition portion (upper 290, [29], figures) has the second width (W1, [29]) on a second side adjacent the second channel region (260 under 285 of upper 125, [29], [31], figures).
Regarding claim 8, Ong discloses the apparatus of claim 1 as described above.
Ong further discloses, in at least figures 2A-4B and related text, the first semiconductor structure (upper 260, [29], figure 2A) comprises a nanoribbon ([29]);
the nanoribbon has the first width (W2, [29]) at the first channel region (260 under 285 of upper 130, [29], [31], figures); and
the nanoribbon has the second width (W1, [29]) at the second channel region (260 under 285 of upper 125, [29], [31], figures).
Regarding claim 9, Ong discloses the apparatus of claim 8 as described above.
Ong further discloses, in at least figures 2A-4B and related text, an axis of the nanoribbon (260, [29]) bisects the first (W2, [29]) and second (W1, [29]) widths.
Regarding claim 10, Ong discloses the apparatus of claim 8 as described above.
Ong further discloses, in at least figures 2A-4B and related text, the first semiconductor structure (upper 260, [29], figure 2A) comprises a stack of nanoribbons, and the stack of nanoribbons comprises the first (260 under 285 of upper 130, [29], [31], figures) and second (260 under 285 of upper 125, [29], [31], figures) channel regions (figures).
Regarding claim 11, Ong discloses, in at least figures 2A-4B and related text, an apparatus, comprising:
a plurality of channel structures (upper 260/lower 260, [29], figure 2A), extending in a first direction (x direction, figures), wherein individual ones of the channel structures (upper 260/lower 260, [29], figure 2A) comprise adjacent first (260 under 285 of 130, [29], [31], figures) and second (260 under 285 of 125, [29], [31], figures) channel regions, the first channel regions (260 under 285 of 130, [29], [31], figures) having a first width (W2, [29]) less than a second width (W1, [29]) of the second channel regions (260 under 285 of 125, [29], [31], figures);
an array of transistors (125/130, [29]) comprising pluralities of first (130, [29]) and second (125, [29]) transistors, wherein the first transistors (130, [29]) comprise the first channel regions (260 under 285 of 130, [29], [31], figures), and the second transistors (125, [29]) comprise the second channel regions (260 under 285 of 125, [29], [31], figures); and
a conductive floating structure (280, [31]), extending in a second direction (y direction, figures) and coupling the plurality of channel structures (upper 260/lower 260, [29], figure 2A) and between the first (130, [29]) and second (125, [29]) transistors, wherein the floating structure (280, [31]) covers a transition section (290, [29]) of an individual one of the channel structures (upper 260/lower 260, [29], figure 2A), the transition section (290, [29]) having the first width (W2, [29]) on a first side coupled to a corresponding one of the first transistors (130, [29]) and having the second width on a second side (W1, [29]) coupled to a corresponding one of the second transistors (125, [29]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 3-4, 6-7 and 12-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ong (US 2023/0209797) in view of Cho (US 2023/0131215).
Regarding claim 3, Ong discloses the apparatus of claim 1 as described above.
Ong does not explicitly disclose the stripe of material is a floating conductor coupled to the first and second semiconductor structures by a dielectric material layer.
Cho teaches, in at least figures 4A, 5, and related text, the device comprising the stripe of material (163 of 165D, [34], [53]) is a floating conductor coupled to the first (105A, [54]) and second (105B, [54]) semiconductor structures by a dielectric material layer (162, [33]), for the purpose of providing semiconductor devices having improved electrical characteristics and reliability characteristics ([4]).
Ong and Cho are analogous art because they both are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Ong with the specified features of Cho because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Ong to have the stripe of material being a floating conductor coupled to the first and second semiconductor structures by a dielectric material layer, as taught by Cho, for the purpose of providing semiconductor devices having improved electrical characteristics and reliability characteristics ([4], Cho).
Regarding claim 4, Ong discloses the apparatus of claim 1 as described above.
Ong does not explicitly disclose the stripe of material spans over an isolation structure between the first and second semiconductor structures.
Cho teaches, in at least figures 4A, 5, and related text, the device comprising the stripe of material (163 of 165D, [34], [53]) spans over an isolation structure (110, [29]) between the first (105A, [54]) and second (105B, [54]) semiconductor structures, for the purpose of providing semiconductor devices having improved electrical characteristics and reliability characteristics ([4]).
Ong and Cho are analogous art because they both are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Ong with the specified features of Cho because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Ong to have the stripe of material spanning over an isolation structure between the first and second semiconductor structures, as taught by Cho, for the purpose of providing semiconductor devices having improved electrical characteristics and reliability characteristics ([4], Cho).
Regarding claim 6, Ong discloses the apparatus of claim 1 as described above.
Ong does not explicitly disclose the first and second transistors have p-type conductivity, and the third and fourth transistors have n-type conductivity.
Cho teaches, in at least figures 4A, 5, and related text, the device comprising the first (TR6, [53]) and second (TR4, [53]) transistors have p-type conductivity, and the third (TR2, [53]) and fourth (TR2, [53]) transistors have n-type conductivity, for the purpose of providing semiconductor devices having improved electrical characteristics and reliability characteristics ([4]).
Ong and Cho are analogous art because they both are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Ong with the specified features of Cho because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Ong to have the first and second transistors having p-type conductivity, and the third and fourth transistors have n-type conductivity, as taught by Cho, for the purpose of providing semiconductor devices having improved electrical characteristics and reliability characteristics ([4], Cho).
Regarding claim 7, Ong discloses the apparatus of claim 1 as described above.
Ong does not explicitly disclose the first semiconductor structure comprises a plurality of fins within the second width, a first of the plurality of fins is within the first width, and a second of the plurality of fins is outside the first width.
Cho teaches, in at least figures 4A, 5, and related text, the device comprising the first semiconductor structure (105A, [54]) comprises a plurality of fins within the second width (W1a/W1c, figures), a first of the plurality of fins is within the first width (W1b, figures), and a second of the plurality of fins is outside the first width (W1b, figures), for the purpose of providing semiconductor devices having improved electrical characteristics and reliability characteristics ([4]).
Ong and Cho are analogous art because they both are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Ong with the specified features of Cho because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Ong to have the first semiconductor structure comprising a plurality of fins within the second width, a first of the plurality of fins is within the first width, and a second of the plurality of fins is outside the first width, as taught by Cho, for the purpose of providing semiconductor devices having improved electrical characteristics and reliability characteristics ([4], Cho).
Regarding claim 12, Ong discloses the apparatus of claim 11 as described above.
Ong does not explicitly disclose a dielectric material couples the floating structure and individual ones of the channel structures.
Cho teaches, in at least figures 4A, 5, and related text, the device comprising a dielectric material (162, [33]) couples the floating structure (163 of 165D, [34], [53]) and individual ones of the channel structures (105A/105B, [54]), for the purpose of providing semiconductor devices having improved electrical characteristics and reliability characteristics ([4]).
Ong and Cho are analogous art because they both are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Ong with the specified features of Cho because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Ong to have the dielectric material coupling the floating structure and individual ones of the channel structures, as taught by Cho, for the purpose of providing semiconductor devices having improved electrical characteristics and reliability characteristics ([4], Cho).
Regarding claim 13, Ong in view of Cho discloses the apparatus of claim 12 as described above.
Cho further teaches, in at least figures 4A, 5, and related text, individual ones of the first (channel of TR2, [53]) and second (channel of TR1, [53]) channel regions corresponding to a first channel structure (105A, [54]) are of a first conductivity type ([53]), and individual ones of the first (channel of TR6, [53]) and second (channel of TR4, [53]) channel regions corresponding to an adjacent second channel structure (105B, [54]) are of a second conductivity type ([53]), for the purpose of providing semiconductor devices having improved electrical characteristics and reliability characteristics ([4]).
Regarding claim 14, Ong in view of Cho discloses the apparatus of claim 13 as described above.
Ong further discloses, in at least figures 2A-4B and related text, the first channel structure (upper 260, [29], figure 2A) comprises a stack of nanoribbons having the second width (W1, [29]) within an individual one of the second transistors (125, [29]) and having the first width (W2, [29]) within an individual one of the first transistors (130, [29]).
Regarding claim 15, Ong in view of Cho discloses the apparatus of claim 14 as described above.
Ong further discloses, in at least figures 2A-4B and related text, a first plane of symmetry of an individual one of the first channel regions (260 under 285 of 130, [29], [31], figures) is substantially aligned with a second plane of symmetry of an individual one of the second channel regions (260 under 285 of 125, [29], [31], figures).
Regarding claim 16, Ong in view of Cho discloses the apparatus of claim 13 as described above.
Cho further teaches, in at least figures 4A, 5, and related text, the first channel structure (105A, [54]) comprises first and second fins within the second width (W1a/W1c, figures), the first fin is within the first width (W1b, figures), and the second fin is not in the first width (W1b, figures), for the purpose of providing semiconductor devices having improved electrical characteristics and reliability characteristics ([4]).
Allowable Subject Matter
Claim 5 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims because the prior art of record neither anticipates nor render obvious the limitations of the base claims 1 and 5 that recite "the first and second threshold voltages are substantially equal" in combination with other elements of the base claims 1 and 5.
Claims 17-20 are allowed because the prior art of record neither anticipates nor render obvious the limitations of the base claims 17 that recite "first, second, and third pluralities of fins or nanoribbons extending in a first direction, the first plurality between the second and third pluralities and comprising a channel region; first and second floating conductors spanning between the second and third pluralities in a second direction, wherein the first plurality has a first width between the first and second floating conductors and a second width greater than the first width outside the first and second floating conductors" in combination with other elements of the base claims 17.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TONG-HO KIM whose telephone number is (571)270-0276. The examiner can normally be reached Monday thru Friday; 8:30 AM to 5PM.
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/TONG-HO KIM/Primary Examiner, Art Unit 2811
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