DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species A (Fig. 1, Claims 1-5 and 15-19 in the reply filed on 02/09/2026 is acknowledged.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the
“a N-type electrode that is in Ohmic contact with the N-type semiconductor layer; and a P-type electrode that is in Ohmic contact with the P-type semiconductor layer.” of Claim 19
must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claim 1 objected to because of the following informalities:
The Examiner notes that “a gate elimination layer” is objected since the language is not commensurate with common use. The use of the term "gate" creates, assuming the standard definition applied in the semiconductor art, the expectation of a three terminal device which does not appear to be present in the current application. See attached definition of gate in the semiconductor art attached.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 17 recites the limitation " the plurality of sub-shallow well layers" in line 2. There is insufficient antecedent basis for this limitation in the claim.
For the purposes of examination the Examiner will treat “the plurality of sub-shallow well layers” as --a plurality of sub-shallow well layers--.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 2, 4, 15-17 and 19 is/are rejected under 35 U.S.C. 102 (a1) as being anticipated by Sokol et al. (US 2020/0075798 A1).
Regarding Claim 1, Sokol (Fig. 1) discloses a semiconductor epitaxial structure, comprising:
a substrate (10), an N-type semiconductor layer (11), a gate elimination layer (15, 16), an active layer (17), and a P-type semiconductor layer (30, 32), wherein
the N-type semiconductor layer (14), the gate elimination layer (15), the active layer (17), and the P-type semiconductor layer (30, 32) are sequentially stacked on the substrate (10), and wherein
the gate elimination layer (15) comprises an N-type doped semiconductor layer (n-type doped GaN) [0061]
Regarding Claim 2, Sokol (Fig. 1) discloses the semiconductor epitaxial structure according to claim 1, wherein
the gate elimination layer (15) comprises a non-uniform N-type doped semiconductor layer. (the LED further comprises a spacer layer arranged between the n-type GaN layer and the first barrier-well unit, wherein the spacer layer comprises a first sublayer and a second sublayer and the first sublayer has a higher n-type doping concentration than the second sublayer.”) [0009, 0018, 0069].
Regarding Claim 4, Sokol (Fig. 1) discloses the semiconductor epitaxial structure according to claim 1, further comprising:
a shallow well layer (16) that is sandwiched between the gate elimination layer (15) and the active layer (17), wherein
the shallow well layer (16) comprises a plurality of sub-shallow well layers that are sequentially stacked along a first direction (Fig. 1). [0072, 0073]
Regarding Claim 15, Sokol (Fig. 1) discloses the semiconductor epitaxial structure according to claim 1, wherein
an N-type doping concentration in the gate elimination layer (15) is between 1×10.sup.17 to 1×10.sup.20 cm.sup.−3. [0009, 0018, 0069, 0074]
Regarding Claim 16, Sokol (Fig. 1) discloses the semiconductor epitaxial structure according to claim 1, wherein
the gate elimination layer (15) comprises an N-type doped GaN layer, an N-type doped AlGaN layer, an N-type doped AlGaInN layer, an N-type doped GaInN layer, or an N-type doped AlInN layer. [0009, 0018, 0069, 0074]
Regarding Claim 17, Sokol (Fig. 1) discloses the semiconductor epitaxial structure according to claim 1, wherein
a number the plurality of sub-shallow well layers is between 1 to 20, including endpoint values. (Fig. 1) [0072, 0073]
Regarding Claim 19, Sokol (Fig. 1) discloses a Light-emitting diode (LED) chip, comprising: a semiconductor epitaxial structure, comprising:
a substrate (10), an N-type semiconductor layer (14), a gate elimination layer (15), an active layer (17), and a P-type semiconductor layer (32), wherein the N-type semiconductor layer (14), the gate elimination layer (15), the active layer (17), and the P-type semiconductor layer (32) are sequentially stacked on the substrate (10), and wherein
the gate elimination layer (15) comprises an N-type doped semiconductor layer; (n-type doped GaN) [0061]
a N-type electrode (27) that is in Ohmic contact with the N-type semiconductor layer (; and a P-type electrode (28) that is in Ohmic contact with the P-type semiconductor layer. (32)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 3 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sokol et al. (US 2020/0075798 A1).
Regarding Claim 3, Sokol (Fig. 1) discloses the semiconductor epitaxial structure according to claim 1, wherein
an N-type doping concentration in the gate elimination layer (15, 16) varies in one of following manners:
gradually increasing along a first direction;
gradually decreasing along the first direction; or
varying in a gradient, wherein
a highest N-type doping concentration of the gate elimination layer (15) along the first direction [0009, 0018, 0069, 0074] and an N-type doping concentration of the N-type semiconductor layer (14, second nitride layer 14 may be doped with Si at a concentration of less than about 5×10.sup.19 cm.sup.−3.) [0068], and wherein
the first direction is perpendicular to the substrate (10) and from the substrate to the N-type semiconductor layer (14).
Sokol does not explicitly disclose a highest N-type doping concentration of the gate elimination layer along the first direction is greater than an N-type doping concentration of the N-type semiconductor layer.
However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor epitaxial structure in Sokol such that a highest N-type doping concentration of the gate elimination layer along the first direction is greater than an N-type doping concentration of the N-type semiconductor layer since it has been held that the general conditions of a claim are disclosed in a prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 and in order to have LED structures may have improved tolerance to electrostatic discharge (ESD). [0069].
Regarding Claim 18, Sokol (Fig. 1) discloses the semiconductor epitaxial structure according to claim 1, wherein
a thickness of the gate elimination layer. (“The spacer layer 15 may have a thickness in a range of about 100 Å to about 1200 Å”) [0069]
Sokol does not explicitly disclose a thickness of the gate elimination layer is no greater than 100 nm.
However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor epitaxial structure in Sokol such that a thickness of the gate elimination layer is no greater than 100 nm since it has been held that the general conditions of a claim are disclosed in a prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 and in order to have LED structures may have improved tolerance to electrostatic discharge (ESD). [0069]
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sokol et al. (US 2020/0075798 A1) in view of LU et al. (CN 110635004 A; Publiched 12/31/2019)
Regarding Claim 5, Sokol (Fig. 1) discloses the semiconductor epitaxial structure according to claim 4, wherein
energy band of each sub-shallow well layer decreases along the first direction, and energy band of the adjacent sub-shallow layer that is adjacent to the active layer (17) is greater than energy band of the active layer (17) [0078].
Sokol does not explicitly disclose that a lattice constant of each sub-shallow well layer increases along the first direction, and a lattice constant of an adjacent sub-shallow layer that is adjacent to the active layer is smaller than a lattice constant of the active layer
Lu (Fig. 1) discloses a lattice constant of each sub-shallow well layer (130) increases along a first direction, and a lattice constant of an adjacent sub-shallow layer that is adjacent to an active layer (140) is smaller than a lattice constant of the active layer (140), (“to further reduce the N-type epitaxial layer 120 and the luminescent layer has a lattice 140 mismatch between the need to adjust the lattice parameter of the stress adjusting layer 130. direction lattice parameter to make the first periodic structure layer close to the lattice parameter of the N-type epitaxial layer 120, the lattice parameter of the M-th periodic structure layer close to the lattice parameter of the luminous layer 140, and from the N-type epitaxial layer 120 to the light emitting layer 140, and the lattice parameter of the stress adjusting layer gradually approaches the lattice parameter of the luminous layer 140, polarization effect so as to reduce the light emitting layer 140 due to lattice mismatch,”
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor epitaxial structure in Sokol such that a lattice constant of each sub-shallow well layer increases along the first direction, and a lattice constant of an adjacent sub-shallow layer that is adjacent to the active layer is smaller than a lattice constant of the active layer in order reduce the light emitting layer 140 due to lattice mismatch [Lu
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DMITRIY YEMELYANOV whose telephone number is (571)270-7920. The examiner can normally be reached M-F 9a.m.-6p.m.
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/DMITRIY YEMELYANOV/Examiner, Art Unit 2891