DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claims 1 – 9, and 11 – 20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 11 – 20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The claims recite “wherein D1 is greater than D2”. However, the specification teaches that D2 may be greater than or equal to D1 ([0033], [0058]). The conflicting teachings of the specification render the recitations in the claims indefinite (MPEP 2173.03).
For the purposes of examination, the claims will be interpreted in view of the specification, which states that longer wires may have a larger diameter.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 – 6, 8, and 9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yu et al. (US 9,773,757).
Regarding claim 1, Yu teaches (FIG. 8A):
A semiconductor package, comprising:
a redistribution wiring layer having redistribution wirings stacked in at least two levels (102b);
a first semiconductor chip (154a) arranged on the redistribution wiring layer, wherein first chip pads are formed on a front surface of the first semiconductor chip and the front surface of the first semiconductor chip faces the redistribution wiring layer (FIG. 8A);
a plurality of second semiconductor chips (104a/b) arranged on the first semiconductor chip, wherein second chip pads are formed on a front surface of the plurality of second semiconductor chips and the front surface of the plurality of second semiconductor chips faces the redistribution wiring layer, and wherein the second chip pads are exposed from the first semiconductor chip (FIG. 8A);
first conductive wires (110c) electrically connecting the first chip pads of the first semiconductor chip and the redistribution wirings of the redistribution wiring layer;
second conductive wires (110b) electrically connecting the second chip pads of the plurality of second semiconductor chips and the redistribution wirings of the redistribution wiring layer; and
a sealing unit (120) disposed on the redistribution wiring layer and covering the first semiconductor chip, the plurality of second semiconductor chips, the first conductive wires, and the second conductive wires, and
external connection units (130) disposed on an outer surface of the redistribution wiring layer and electrically connected to the redistribution wirings, wherein in a plan view, the redistribution wiring layer includes a fan-out region around the plurality of second semiconductor chips, and some of the external connection units are disposed in the fan-out region (FIG. 8A).
Regarding claim 2, Yu teaches:
The semiconductor package of claim 1, wherein each of the plurality of second semiconductor chips includes an overhang portion that protrudes from a side of the first semiconductor chip, and wherein the second chip pads are disposed on a lower surface of the overhang portion (FIG. 8A).
Regarding claim 3, Yu teaches:
The semiconductor package of claim 1, wherein the plurality of second semiconductor chips are arranged at a same level on the first semiconductor chip and are spaced apart from each other (FIG. 8A).
Regarding claim 4, Yu teaches:
The semiconductor package according to claim 1, wherein a backside surface of the first semiconductor chip is attached to the front surfaces of the plurality of second semiconductor chips with a first adhesive film (106).
Regarding claim 5, Yu teaches:
The semiconductor package of claim 1, wherein the first conductive wires extend upward from a first uppermost redistribution wiring among the redistribution wirings to the first chip pad, and the second conductive wires extend upward from a second uppermost redistribution wiring among the redistribution wirings to the second chip pad (FIG. 8A).
Regarding claim 6, Yu teaches:
The semiconductor package of claim 1, wherein the first conductive wires have a first height from the redistribution wiring layer, and the second conductive wires have a second height greater than the first height from the redistribution wiring layer (FIG. 8A).
Regarding claim 8, Yu teaches:
The semiconductor package of claim 1, wherein second adhesive films are attached to backside surfaces of the plurality of second semiconductor chips (106, FIG. 1).
Regarding claim 9, Yu teaches:
The semiconductor package of claim 8, wherein the second adhesive films are exposed from an upper surface of the sealing unit (FIG. 8A, adhesive films are attached to 2nd RDL, and therefore not covered by the molding material 120).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Yu et al. (US 9,773,757) as applied to claim 1 above, and further in view of Uzoh et al. (US 9,728,527).
Regarding claim 7, Yu teaches varying lengths and thickness of connections, including very short connections as in 146, and longer and thicker connections as in 110a/b/c sized as appropriate to connect across the thickness of the stacked devices, but fails to expressly disclose:
The semiconductor package of claim 6, wherein the first height is 10 µm to 50 µm, and the second height is 400 µm to 550 µm.
However, Uzoh teaches stacked devices having wires of varying lengths and diameters for integrating multiple semiconductor die in a single package, wherein shorter wires have a length of less than 0.01 mm and a diameter of 0.01 mm, and medium wires have a length of 0.05 mm and a diameter of 0.01 mm, with longer wires having a larger diameter for varying performance characteristics.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to design the varying lengths of diameters of the conductive wires of Yu to whatever relationship was necessary or expedient for the particular semiconductor devices being integrated into a stacked package, with longer wires being formed of larger diameter to optimize performance in a conventional and predictable manner as taught by Uzoh.
Claims 11 – 20 are rejected under 35 U.S.C. 103 as being unpatentable over Yu et al. (US 9,773,757) in view of Uzoh et al. (US 9,728,527), as best understood by the examiner in light of the rejections under 35 USC 112(b) above.
Regarding claim 11, Yu teaches (FIG. 8A, 8B):
A semiconductor package, comprising:
a redistribution wiring layer (102b) including, in a plan view, a first region, a second region surrounding the first region, and a third region surrounding the second region, wherein first uppermost redistribution wirings are disposed in the first region and second uppermost redistribution wirings are disposed in the second region (FIG. 8A);
first conductive wires (110c) extending upward on the first uppermost redistribution wirings by a first height, the first conductive wires having a first diameter D1;
second conductive wires (110b) extending upward on the second uppermost redistribution wirings by a second height greater than the first height (FIG. 8A), the second conductive wires having a second diameter D2;
a first semiconductor chip (154a) disposed on the redistribution wiring layer via the first conductive wires (FIG. 8A);
a plurality of second semiconductor chips (104a/b) disposed on the redistribution wiring layer via the second conductive wires, wherein the plurality of second semiconductor chips are arranged on the first semiconductor chip (FIG. 8A); and
a sealing unit (120) on the redistribution wiring layer and covering the first semiconductor chip, the plurality of second semiconductor chips, the first conductive wires, and the second conductive wires,.
Yu teaches varying conductive connections including very short connections as in 146, and longer and thicker connections as in 110a/b/c sized as appropriate to connect across the thickness of the stacked devices, but fails to expressly disclose wherein D1 is greater than D2, and D1 and D2 are each in a range from 15 µm to 25 µm.
However, Uzoh teaches stacked devices having wires of varying lengths and diameters for integrating multiple semiconductor die in a single package, wherein shorter wires have a length of less than 0.01 mm and a diameter of 0.01 mm, and medium wires have a length of 0.05 mm and a diameter of 0.01 mm, with longer wires having a larger diameter for varying performance characteristics.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to design the varying lengths of diameters of the conductive wires of Yu to whatever relationship was necessary or expedient for the particular semiconductor devices being integrated into a stacked package, with longer wires being formed of larger diameter to optimize performance in a conventional and predictable manner as taught by Uzoh.
Regarding claim 12, Yu teaches:
The semiconductor package of claim 11, wherein the first conductive wires electrically connect first chip pads disposed on the first semiconductor chip to the first redistribution wirings respectively, and the second conductive wires connect second chip pads disposed on the second semiconductor chip to the second redistribution wirings respectively (FIG. 8A).
Regarding claim 13, Yu teaches:
The semiconductor package of claim 11, wherein each of the plurality of second semiconductor chips includes an overhang portion that protrudes from one side of the first semiconductor chip, and wherein second chip pads disposed on the plurality of second semiconductor chip are disposed on the overhang portion (FIG. 8A).
Regarding claim 14, Yu teaches:
The semiconductor package of claim 11, wherein the plurality of second semiconductor chips are disposed at a same level on the first semiconductor chip and are spaced apart from each other (FIG. 8A).
Regarding claim 15, Yu teaches:
The semiconductor package of claim 11, wherein first chip pads are formed on a front surface of the first semiconductor chip, and the front surface of the first semiconductor chip faces the redistribution wiring layer, and second chip pads are formed on a front surface of the plurality of second semiconductor chips, and the front surface of the plurality of second semiconductor chips faces the redistribution wiring layer (FIG. 8A).
Regarding claim 16, Yu teaches:
The semiconductor package of claim 15, wherein a backside surface of the first semiconductor chip is attached to front surfaces of the plurality of second semiconductor chips with a first adhesive film (106).
Regarding claim 17, Yu teaches:
The semiconductor package of claim 15, wherein second adhesive films are attached to backside surfaces of the plurality of second semiconductor chips (106, FIG. 1).
Regarding claim 18, Uzoh teaches (col 15, line 30 – col 16, line 6):
The semiconductor package of claim 11, wherein the first height is 10 µm to 50 µm, and the second height is 400 µm to 550 µm.
Regarding claim 19, Yu teaches:
The semiconductor package of claim 11, further comprising: external connection units disposed on an outer surface of the redistribution wiring layer (130), wherein in a plan view, one or more of the external connection units are disposed in the third region (FIG. 8A, 8B).
Regarding claim 20, Yu teaches (FIG. 8A, 8B):
A semiconductor package, comprising:
a plurality of second semiconductor chips (104a/b), each of the plurality of second semiconductor chips having a front surface, wherein second chip pads are formed on the front surface and the plurality of second semiconductor chips are positioned at a same level and spaced apart from each other (FIG. 8A);
a first semiconductor chip (154a) arranged on the plurality of second semiconductor chips, wherein the second chip pads are exposed from the first semiconductor chip and first chip pads are formed on a front surface of the first semiconductor chip (FIG. 8A);
first conductive wires (110c) extending upwardly on the first chip pads by a first height (FIG. 8A), the first conductive wires having a first diameter D1;
second conductive wires (110b) extending upwardly on the second chip pads by a second height greater than the first height (FIG. 8A), the second conductive wires having a second diameter D2;
a sealing unit (120) covering the plurality of second semiconductor chips, the first semiconductor chip, the first conductive wires, and the second conductive wires and exposing end portions of the first conductive wires and the second conductive wires; and
a redistribution wiring layer (102b) disposed on the sealing unit, the redistribution wiring layer having redistribution wirings electrically connected to the exposed end portions of the first conductive wires and the second conductive wires respectively (FIG. 8A), external connection units (130) disposed on an outer surface of the redistribution wiring layer and electrically connected to the redistribution wirings, wherein in a plan view, the redistribution wiring layer includes a fan-out region not overlapping the plurality of second semiconductor chips, and some of the external connection units are disposed in the fan-out region (FIG. 8A, 8B),.
Yu teaches varying conductive connections including very short connections as in 146, and longer and thicker connections as in 110a/b/c sized as appropriate to connect across the thickness of the stacked devices, but fails to expressly disclose wherein D1 is greater than D2, and D1 and D2 are each in a range from 15 µm to 25 µm.
However, Uzoh teaches stacked devices having wires of varying lengths and diameters for integrating multiple semiconductor die in a single package, wherein shorter wires have a length of less than 0.01 mm and a diameter of 0.01 mm, and medium wires have a length of 0.05 mm and a diameter of 0.01 mm, with longer wires having a larger diameter for varying performance characteristics.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to design the varying lengths of diameters of the conductive wires of Yu to whatever relationship was necessary or expedient for the particular semiconductor devices being integrated into a stacked package, with longer wires being formed of larger diameter to optimize performance in a conventional and predictable manner as taught by Uzoh.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CORY W ESKRIDGE whose telephone number is (571)272-0543. The examiner can normally be reached M - F 9 - 5.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jerry O'Connor can be reached at (571) 272-6787. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CORY W ESKRIDGE/Primary Examiner, Art Unit 3624
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