Prosecution Insights
Last updated: April 19, 2026
Application No. 18/216,733

PACKAGING STRUCTURE AND ELECTRONIC DEVICE HAVING THE PACKAGING STRUCTURE

Non-Final OA §102§103
Filed
Jun 30, 2023
Examiner
CUTLER, ETHAN EDWARD
Art Unit
2892
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Rayprus Technology (Foshan) Co. Ltd.
OA Round
1 (Non-Final)
92%
Grant Probability
Favorable
1-2
OA Rounds
3y 6m
To Grant
99%
With Interview

Examiner Intelligence

Grants 92% — above average
92%
Career Allow Rate
34 granted / 37 resolved
+23.9% vs TC avg
Moderate +12% lift
Without
With
+12.0%
Interview Lift
resolved cases with interview
Typical timeline
3y 6m
Avg Prosecution
30 currently pending
Career history
67
Total Applications
across all art units

Statute-Specific Performance

§103
60.7%
+20.7% vs TC avg
§102
24.0%
-16.0% vs TC avg
§112
15.0%
-25.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 37 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of species A in the reply filed on 1/8/2026 is acknowledged. Claims 6-7 & 16-17 are withdrawn. All elected claims are examined on the merits. Specification The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. It is suggested that the title include the phrase “including a transparent substrate and cover.” Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1, 3-5, 8-10, 13-15, & 18-19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by U.S. Pat. Pub. No. US 20110080516 A1, which is of record, to Yi et al. (hereinafter “Yi”). Regarding claim 1, Yi teaches a packaging structure (image sensor module 500; fig. 1) [0057] comprising: a first transparent substrate (lower transparent board 150; fig. 1) [0058] comprising a first surface (vertically lower surface of 150; fig. 1) and a second surface (vertically higher surface of 150; fig. 1) facing away (being opposite) from the first surface (lower); a second transparent substrate (upper transparent board 221; fig. 1) [0068], the second transparent substrate (221) and the first transparent substrate (150) stacked in a first direction (vertical direction in fig. 1), and the second transparent substrate (221) comprising a third surface (vertically lower surface of 221) facing the second surface (upper of 150) of the first transparent substrate (150); a support (adhesion 231; fig. 1) [0070] connecting the second surface (upper of 150) and the third surface (lower of 221), and a first cavity (transmitting space S2; fig. 1) [0072] defined by the support (231) connecting the second transparent substrate (221) and the first transparent substrate (150); an optical lens assembly (lens 211; fig. 1) [0067] received in the first cavity (S2) and fixed on the third surface (lower of 221); a packaging assembly (assembly below 150; fig. 1) comprising a base (substrate 110 fig. 1) [0058] fixed (attached to) on the first surface (lower of 150) and electrodes (140; fig. 1) [0058], a second cavity (space of 111) defined by the base (110) and the first transparent substrate (150); and an optical component (image sensor chip 111; fig. 1) [0060] received in the second cavity (space of 111), wherein the optical component (111) and the optical lens assembly (211) overlaps in the first direction (vertical direction), the optical component (111) is electrically connected to the electrodes (140) and located between the first surface (lower of 150) and the electrodes (140). Regarding claim 3, Yi teaches the packaging structure of claim 1, wherein the optical component (111) is fixed on (fastened to) the first surface (lower 150) (this is done through the attachments on each lateral side of 111). The Examiner notes that a phrase such as “in direct contact with” would overcome the above interpretation of the term “fixed on.” Regarding claim 4, Yi teaches the packaging structure of claim 3, wherein the optical component (111) is a light emitter (comprises a photodiode) [0059]. Regarding claim 5, Yi teaches the packaging structure of claim 1, wherein the optical component (111) is spaced from (space exists which separates) the first surface (lower 150). Regarding claim 8, Yi teaches the packaging structure of claim 1, wherein the electrodes are located in a surface of the base (110) facing away from the first surface (lower 150), the base (110) is provided with conducting circuits (conductive pathways), the electrodes (140) are electrically connected to the optical component (111) through the conducting circuits (not explicitly shown in fig. 1 but described by Yi) [0060]. Regarding claim 9, Yi teaches the packaging structure of claim 1, wherein the electrodes (140) extend through the base (110) to be connected to the optical component (111). Regarding claim 11, Yi teaches an electronic device (device of fig. 1) [0057] comprising: a packaging structure (image sensor module 500; fig. 1) [0057] comprising: a first transparent substrate (lower transparent board 150; fig. 1) [0058] comprising a first surface (vertically lower surface of 150; fig. 1) and a second surface (vertically higher surface of 150; fig. 1) facing away (being opposite) from the first surface (lower of 150); a second transparent substrate (upper transparent board 221; fig. 1) [0068], the second transparent substrate (221) and the first transparent substrate (150) stacked in a first direction (vertical direction in fig. 1), and the second transparent substrate (221) comprising a third surface (vertically lower surface of 221) facing the second surface (upper of 150) of the first transparent substrate (150); a support (adhesion 231; fig. 1) [0070] connecting the second surface (upper 150) and the third surface (lower of 221), and a first cavity (transmitting space S2; fig. 1) [0072] defined by the support (231) connecting the second transparent substrate (221) and the first transparent substrate (150); an optical lens assembly (lens 211; fig. 1) [0067] received in the first cavity (S2) and fixed on (fastened to) the third surface (lower 221); a packaging assembly (assembly below 150; fig. 1) comprising a base (substrate 110 fig. 1) [0058] fixed on (fastened to) the first surface (lower 150) and electrodes (140; fig. 1) [0058], a second cavity (space of 111) defined by the base (110) and the first transparent substrate (150); and an optical component (image sensor chip 111; fig. 1) [0060] received in the second cavity (space of 111), wherein the optical component (111) and the optical lens assembly (211) overlaps in the first direction (vertical), the optical component (111) is electrically connected to the electrodes (140) and located between the first surface and the electrodes. Regarding claim 13, Yi teaches the electronic device of claim 11, wherein the optical component (111) is fixed on (fastened to) the first surface (lower 150) (this is done through the attachments on each lateral side of 111). The Examiner notes that a phrase such as “in direct contact with” would overcome the above interpretation. Regarding claim 14, Yi teaches the electronic device of claim 13, wherein the optical component (111) is a light emitter (comprises a photodiode) [0059]. Regarding claim 15, Yi teaches the electronic device of claim 11, wherein the optical component (111) is spaced from (space exists which separates) the first surface (lower 150). Regarding claim 18, Yi teaches the electronic device of claim 11, wherein the electrodes are located in a surface of the base (110) facing away from the first surface (lower 150), the base (110) is provided with conducting circuits (conductive pathways), the electrodes (140) are electrically connected to the optical component (111) through the conducting circuits (not explicitly shown in fig. 1 but described by Yi) [0060]. Regarding claim 19, Yi teaches the electronic device of claim 11, wherein the electrodes (140) extend through the base (110) to be connected to the optical component (111). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claims 10 & 20 are rejected under 35 U.S.C. 103 as being unpatentable over Yi in view of U.S. Pat. Pub. No. US 20220085571 A1 to Chen et al. (hereinafter “Chen”). Regarding claim 10, Yi teaches the packaging structure of claim 1, wherein a distance between the optical component (111) and the optical lens assembly (211) along the first direction (vertical) is greater than or equal to 3pm. Chen, however, teaches a packaging structure (fig. 3A) wherein a distance between the optical component (laser chip 302; fig. 3A) [0055] and the optical lens assembly (optical component 352; fig. 3A) [0056] is greater than or equal to 3µm. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the structure of Yi to comprise a distance between the optical component and the optical lens assembly being greater than or equal to 3µm to optimize focal length as taught by Chen [0065]. Regarding claim 20, Yi does not teach the electronic device of claim 11, wherein a distance between the optical component and the optical lens assembly along the first direction is greater than or equal to 3pm. Chen, however, teaches a packaging structure (fig. 3A) wherein a distance between the optical component (laser chip 302; fig. 3A) [0055] and the optical lens assembly (optical component 352; fig. 3A) [0056] is greater than or equal to 3µm. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the structure of Yi to comprise a distance between the optical component and the optical lens assembly being greater than or equal to 3µm to optimize focal length as taught by Chen [0065]. Allowable Subject Matter Claims 2 & 12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Regarding claim 2, it is not found any reference which teaches a receiving groove recessed from one surface to an opposite surface of a packaging substrate which is transparent in addition to comprising an adhesive in the groove. There are references which teach a receiving groove in a semiconductor substrate, but these references do not teach that the semiconductor substrate is transparent. Claim 12 contains allowable subject matter for the same reason. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to ETHAN EDWARD CUTLER whose telephone number is (703)756-5415. The examiner can normally be reached Monday-Friday 7:30 am - 5:00 pm Eastern Time. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Drew Richards can be reached on (571) 272-1736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ETHAN EDWARD CUTLER/Examiner, Art Unit 2892 /NORMAN D RICHARDS/ Supervisory Patent Examiner, Art Unit 2892
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Prosecution Timeline

Jun 30, 2023
Application Filed
Mar 08, 2026
Non-Final Rejection — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
92%
Grant Probability
99%
With Interview (+12.0%)
3y 6m
Median Time to Grant
Low
PTA Risk
Based on 37 resolved cases by this examiner. Grant probability derived from career allow rate.

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