Office Action Predictor
Last updated: April 15, 2026
Application No. 18/216,745

SEMICONDUCTOR APPARATUS HAVING MULTI-LAYERED BIT LINE CONTACT AND MANUFACTURING METHOD OF THE SAME

Final Rejection §112
Filed
Jun 30, 2023
Examiner
PAGE, STEVEN MITCHELL CHR
Art Unit
2812
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Samsung Electronics Co., LTD.
OA Round
2 (Final)
83%
Grant Probability
Favorable
3-4
OA Rounds
2y 2m
To Grant
92%
With Interview

Examiner Intelligence

Grants 83% — above average
83%
Career Allow Rate
359 granted / 433 resolved
+14.9% vs TC avg
Moderate +9% lift
Without
With
+8.6%
Interview Lift
resolved cases with interview
Typical timeline
2y 2m
Avg Prosecution
33 currently pending
Career history
466
Total Applications
across all art units

Statute-Specific Performance

§101
3.4%
-36.6% vs TC avg
§103
38.5%
-1.5% vs TC avg
§102
35.9%
-4.1% vs TC avg
§112
21.6%
-18.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 433 resolved cases

Office Action

§112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 112 The following is a quotation of the first paragraph of 35 U.S.C. 112(a): (a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention. Claim 1 and 3-10 are rejected under 35 U.S.C. 112(a) or pre-AIA 35 U.S.C. 112, first paragraph, as based on a disclosure which is not enabling. The disclosure does not enable one of ordinary skill in the art to practice the invention without “the first contact spacer being continuous along an entire perimeter of the bit line contact within the trench and surrounding the entire perimeter of the bit line contact,” as recited in claim 1, which is/are critical or essential to the practice of the invention but not included in the claim(s). See In re Mayhew, 527 F.2d 1229, 188 USPQ 356 (CCPA 1976). Examiner notes that the bit line contact 146 is not surrounded along its entire perimeter by the first contact spacer 301. Instead, as shown in FIGS. 3 and 4, the top and bottom perimeter of contact 146 are shown to be open to all of the spacers, including first contact spacer 301. In other words, Applicant does not have support for the amendment “the first contact spacer being continuous along an entire perimeter of the bit line contact within the trench and surrounding the entire perimeter of the bit line contact,” as recited in claim 1. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Ahn et al (US 20220157822 A1) – multi-level spacer structure on the bit line. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEVEN M Page whose telephone number is (571)272-3249. The examiner can normally be reached M-F: 10:00AM-6:00PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine S. Kim can be reached at 571-272-8548. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /STEVEN M PAGE/Primary Patent Examiner, Art Unit 2812
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Prosecution Timeline

Jun 30, 2023
Application Filed
Oct 14, 2025
Non-Final Rejection — §112
Nov 19, 2025
Applicant Interview (Telephonic)
Nov 19, 2025
Examiner Interview Summary
Dec 29, 2025
Response Filed
Jan 27, 2026
Final Rejection — §112
Mar 30, 2026
Response after Non-Final Action

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12581643
SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME
2y 5m to grant Granted Mar 17, 2026
Patent 12575089
MEMORY DEVICE WITH TAPERED BIT LINE CONTACT
2y 5m to grant Granted Mar 10, 2026
Patent 12568611
MEMORY DEVICE WITH CELL PADS HAVING DIAGONAL SIDEWALLS
2y 5m to grant Granted Mar 03, 2026
Patent 12568845
CHIP SCALE SEMICONDUCTOR PACKAGE HAVING BACK SIDE METAL LAYER AND RAISED FRONT SIDE PAD AND METHOD OF MAKING THE SAME
2y 5m to grant Granted Mar 03, 2026
Patent 12563719
INTEGRATED CIRCUIT DEVICE
2y 5m to grant Granted Feb 24, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
83%
Grant Probability
92%
With Interview (+8.6%)
2y 2m
Median Time to Grant
Moderate
PTA Risk
Based on 433 resolved cases by this examiner. Grant probability derived from career allow rate.

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