DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 4-10, and 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over Cheah et al. (“Cheah”), US 2016/0005718 (listed in the IDS filed 9-25-2024), in view of Bartley et al. “Bartley”), US 2012/0007229.
Regarding Claim 1, Cheah discloses a package structure (Figs. 1A-1B, 2A-2B; ¶ 0021, 0025), comprising:
a substrate (246; Fig. 2A; ¶ 0027 “package substrate…246”) having an upper surface (Fig. 2A the upper surface of substrate 246);
a first chip package (220; Fig. 2A; ¶ 0025 “main stacked dies (MSD) structures 220”) positioned on the upper surface of the substrate (Fig. 2A; ¶ 0022 “MSD structure…may be disposed above a package substrate”), the first chip package comprising a first chip (122, 124, 126, 128, 130, 132, 134; Fig. 1A not labeled in Fig. 2A; ¶ 0021 “MSD structure…includes stacked dies 122, 124, 126, 128, 130, 132 and 134”) having a first integrated circuit (¶ 0023 “the dies of the MSD structure …are silicon dies such as, but not limited to, logic or memory based devices, e.g., processor, chipset, memory flash, sensor, optical and MEMS etc.”) connected to a first redistribution layer (123, 125, 127, 129, 131, 133, 135; Fig. 1A not labeled in Fig. 2A; ¶ 0021 “Corresponding active layers 123, 125, 127, 129, 131, 133 and 135 are also shown.”);
a second chip package (221; Fig. 2A; ¶ 0025 “main stacked dies (MSD) structures…221”) positioned on the upper surface of the substrate (Fig. 2A; ¶ 0022 “MSD structure…may be disposed above a package substrate”), the second chip package comprising a second chip (122, 124, 126, 128, 130, 132, 134; Fig. 1A not labeled in Fig. 2A; ¶ 0021 “MSD structure…includes stacked dies 122, 124, 126, 128, 130, 132 and 134”) having a second integrated circuit (¶ 0023 “the dies of the MSD structure …are silicon dies such as, but not limited to, logic or memory based devices, e.g., processor, chipset, memory flash, sensor, optical and MEMS etc.”) connected to a second redistribution layer (123, 125, 127, 129, 131, 133, 135; Fig. 1A not labeled in Fig. 2A; ¶ 0021 “Corresponding active layers 123, 125, 127, 129, 131, 133 and 135 are also shown.”);
an orthogonal bridge (201; Figs. 2A-2B; ¶ 0025 “an intermediate vertical side chip (i-VSC) 201 coupled to two main stacked dies (MSD) structures 220 and 221”) positioned between the first chip package and the second chip package (Figs. 2A-2B; ¶ 0025 “an intermediate vertical side chip (i-VSC) 201 coupled to two main stacked dies (MSD) structures 220 and 221”) and having an interconnection (204, 262; Figs. 2A-2B; ¶ 0025 “One or more VSC interconnections 204”and “One or more VSC interconnections 262”) to the first redistribution layer (Figs. 2A-2B; ¶ 0025 “One or more VSC interconnections 204…couples the active layer 202 of the i-VSC 201 to the MSD structure 220.”, ¶ 0026 “die side pad structure 236, of one or more of the stacked dies of the MSD structure 220 may be included for coupling with the i-VSC interconnections 204” and “die backside metal routing 238 of one or more of the stacked dies of the MSD structure 220 may be included for coupling with the i-VSC interconnections 204”) and the second redistribution layer (Figs. 2A-2B; ¶ 0025 “One or more VSC interconnections 262…couples the die backside metal routing 260 of the i-VSC 201 to the MSD structure 221”, ¶ 0026 “die side pad structure 236′, of one or more of the stacked dies of the MSD structure 221 may be included for coupling with the i-VSC interconnections 262” and “die backside metal routing 238′ of one or more of the stacked dies of the MSD structure 221 may be included for coupling with the VSC interconnections 262”); and
wherein the orthogonal bridge is arranged substantially orthogonal to the upper surface of the substrate (Fig. 2A; ¶ 0024, ¶ 0025 “packaging system includes an intermediate vertical side chip (i-VSC) 201”); and
wherein the first chip package and the second chip package lack through-silicon vias (¶ 0027 in this instance Cheah discloses that TSVs 244, 244’ “may” be included in the first chip package 220 and the second chip package 221; therefore Cheah also discloses that the first chip package 220 and the second chip package 221 “lack through-silicon vias”).
Cheah does not disclose a heat spreader positioned in direct contact with at least one of the first chip package, the second chip package, or the orthogonal bridge.
Bartley discloses a heat spreader (240; Fig. 4; ¶ 0021 “Thermal Interface Material (TIM) 240”) positioned in direct contact (Fig. 4; ¶ 0030 “TIM 240 is disposed on…the top surface 2390 of the top-most computing component 231”) with at least one of the first chip package (Fig. 4; ¶ 0025 “die stack 230 is formed as a stack of alternating layers of adhesive 232 and the computing components 231”), the second chip package, or the orthogonal bridge.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for Cheah to have a heat spreader positioned in direct contact with at least one of the first chip package, the second chip package, or the orthogonal bridge, as taught by Bartley, because it “improves the die stack…interconnect reliability” (Bartley ¶ 0024) and provides overall mechanical support for the chip package (Bartley ¶ 0024, 0030).
Regarding Claim 4, Cheah discloses wherein the interconnection of the orthogonal bridge to the first redistribution layer and the second redistribution layer are solder interconnections (¶ 0025 “One or more VSC interconnections 204, e.g., one or more solder bumps, couples the active layer 202 of the i-VSC 201 to the MSD structure 220.” and “One or more VSC interconnections 262, e.g., one or more solder bumps, couples the die backside metal routing 260 of the i-VSC 201 to the MSD structure 221.”).
Regarding Claim 5, Cheah discloses wherein a plurality of first chips in the first chip package are connected to each other via at least one of hybrid bonding, fusion bonding (¶ 0023 “surface activated bonding (SAB)” and “the dies within the MSD structure…are electrically coupled to one another through SAB at the corresponding active layers”, therefore Cheah discloses hybrid bonding or fusion bonding), or thermal compression bonding, and wherein a plurality of second chips in the second chip package are connected to each other via at least one of hybrid bonding, fusion bonding (¶ 0023 “surface activated bonding (SAB)” and “the dies within the MSD structure…are electrically coupled to one another through SAB at the corresponding active layers”, therefore Cheah discloses hybrid bonding or fusion bonding), or thermal compression bonding.
Regarding Claim 6, Cheah discloses wherein the plurality of first chips in the first chip package are separated by first bumps (236; Fig. 2B (shown but not labeled in Fig. 2A); ¶ 0026 “pad structure 236”), and wherein the plurality of second chips in the second chip package are separated by second bumps (236’; Fig. 2B (shown but not labeled in Fig. 2A); ¶ 0026 “pad structure 236′ ”).
Regarding Claim 7, Cheah discloses wherein the orthogonal bridge comprises one or more of silicon, silicon carbide, silicon dioxide, diamond, a silicon nitride, a glass, a dielectric material, a solder material (¶ 0026 “i-VSC interconnections 204” and “i-VSC interconnections 262”, ¶ 0025 “One or more VSC interconnections 204, e.g., one or more solder bumps, couples the active layer 202 of the i-VSC 201 to the MSD structure 220.” and “One or more VSC interconnections 262, e.g., one or more solder bumps, couples the die backside metal routing 260 of the i-VSC 201 to the MSD structure 221.”), polymer, copper, tantalum, tantalum nitride, nickel, gold, aluminum nitride, indium, or combinations thereof.
Regarding Claim 8, Cheah discloses a package structure (Figs. 1A-1C; ¶ 0020-0023), comprising:
a first chip stack (120; Fig. 1A; ¶ 0021 “a main stacked dies (MSD) structure 120”) comprising one or more first chips (122, 126, 128, 130, 132, 134; Fig. 1A; ¶ 0021 “MSD structure 120 includes stacked dies 122…126, 128, 130, 132 and 134”);
a first bridge (100; Fig. 1A; ¶ 0020 “a vertical side chip (VSC) connected to a main stacked dies (MSD) structure”) interconnected to (¶ 0020 “a vertical side chip (VSC) connected to a main stacked dies (MSD) structure”) a first lateral edge (Figs. 1A-1C; ¶ 0021 “One or more VSC interconnections 104…couples each VSC 100 to the MSD structure 120.” and “die side pad structure 136, of one or more of the stacked dies of the MSD structure 120 may be included for coupling with the VSC interconnections 104”) of the first chip stack (Figs. 1A-1C); and
wherein the first chip stack and a lower edge of the bridge are positioned on a planar surface of a substrate (Fig. 1A; ¶ 0022 “VSC 100 and MSD structure 120 may be disposed above a package substrate…146”) such that the first bridge extends orthogonal to the planar surface of the substrate (Fig. 1A; ¶ 0020 “a vertical side chip (VSC)”, ¶ 0022 “VSC 100 and MSD structure 120 may be disposed above a package substrate…146”); and
wherein the first chip stack lacks through-silicon vias (¶ 0022 in this instance Cheah discloses that TSVs 144 “may” be included in the first chip stack, therefore Cheah discloses that the first chip stack “lacks through-silicon vias”; ¶ 0027 in this instance Cheah discloses that TSVs 244, 244’ “may” be included in the first chip package 220 and the second chip package 221; therefore Cheah also discloses that the first chip stack 220, 221 “lacks through-silicon vias”).
Cheah does not disclose a heat spreader positioned in direct contact with at least one of the first chip stack or the bridge.
Bartley discloses a heat spreader (240; Fig. 4; ¶ 0021 “Thermal Interface Material (TIM) 240”) positioned in direct contact (Fig. 4; ¶ 0030 “TIM 240 is disposed on…the top surface 2390 of the top-most computing component 231”) with at least one of the first chip stack (Fig. 4; ¶ 0025 “die stack 230 is formed as a stack of alternating layers of adhesive 232 and the computing components 231”) or the bridge.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for Cheah to have a heat spreader positioned in direct contact with at least one of the first chip stack or the bridge, as taught by Bartley, because it “improves the die stack…interconnect reliability” (Bartley ¶ 0024) and provides overall mechanical support for the chip package (Bartley ¶ 0024, 0030).
Regarding Claim 9, Cheah discloses further comprising a second bridge (100; Fig. 1C; ¶ 0021 “more than one VSC 100 may be coupled to the MSD structure 120”) having a lower edge positioned on the planar surface of the substrate (Fig. 1A; ¶ 0022 “VSC 100…may be disposed above a package substrate…146”), and the second bridge interconnected to a second lateral edge of the first chip stack (Fig. 1C; ¶ 0021 “One or more VSC interconnections 104…couples each VSC 100 to the MSD structure 120”).
Regarding Claim 10, Cheah discloses further comprising a second chip (124; Fig. 1A; ¶ 0021 “MSD structure 120 includes stacked dies…124”) interconnected to an upper edge of the first bridge (Figs. 1A-1B; ¶ 0021 “One or more VSC interconnections 104…couples each VSC 100 to the MSD structure 120.” and “die side pad structure 136, of one or more of the stacked dies of the MSD structure 120 may be included for coupling with the VSC interconnections 104”) and to an upper edge of the second bridge (Figs. 1A-1C; ¶ 0021 “more than one VSC 100 may be coupled to the MSD structure 120”).
Regarding Claim 13, Cheah discloses wherein an interconnection of the first chip stack to the first bridge is a solder interconnection (¶ 0021 “One or more VSC interconnections 104, e.g., one or more solder bumps, couples each VSC 100 to the MSD structure 120.”).
Regarding Claim 14, Cheah discloses wherein the first bridge transports at least one of current or voltage to the first chip stack (¶ 0019 “vertical side chips is used in a multi-die structure to significantly increase I/O pin density and additional electrical paths to the silicon devices within a main stacked die (MSD)”, in this instance current or voltage is transported by bridge VSC 100 to chip stack MSD 120).
Claims 2 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Cheah et al. (“Cheah”), US 2016/0005718 (listed in the IDS filed 9-25-2024) and Bartley et al. “Bartley”), US 2012/0007229, as applied to independent Claims 1 and 8 respectively, in view of Refai-Ahmed et al. (“Refai-Ahmed”), US 2018/0308783.
Regarding Claim 2, Cheah as modified by Bartley does not disclose wherein the heat spreader comprises at least one of aluminum, copper, tungsten, molybdenum, nickel, silicon, silicon carbide, silicon nitride, aluminum nitride, graphite, diamond, or combinations thereof.
Refai-Ahmed discloses wherein the heat spreader (102; Fig. 1; ¶ 0027) comprises at least one of aluminum, copper, tungsten, molybdenum, nickel, silicon, silicon carbide, silicon nitride, aluminum nitride, graphite, diamond, or combinations thereof (¶ 0027 “suitable materials for fabricating the heat sink 102 include copper…or aluminum”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for Cheah as modified to have wherein the heat spreader comprises at least one of aluminum, copper, tungsten, molybdenum, nickel, silicon, silicon carbide, silicon nitride, aluminum nitride, graphite, diamond, or combinations thereof, as taught by Refai-Ahmed, in order to thermally manage the heat generated from the chip package (Refai-Ahmed ¶ 0027) thereby enhancing temperature control of the package structure (Refai-Ahmed ¶ 0005).
Regarding Claim 12, Cheah as modified by Bartley does not disclose wherein the heat spreader comprises at least one of aluminum, copper, tungsten, molybdenum, nickel, silicon, silicon carbide, silicon nitride, aluminum nitride, graphite, diamond, or combinations thereof.
Refai-Ahmed discloses wherein the heat spreader (102; Fig. 1; ¶ 0027) comprises at least one of aluminum, copper, tungsten, molybdenum, nickel, silicon, silicon carbide, silicon nitride, aluminum nitride, graphite, diamond, or combinations thereof (¶ 0027 “suitable materials for fabricating the heat sink 102 include copper…or aluminum”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for Cheah as modified to have wherein the heat spreader comprises at least one of aluminum, copper, tungsten, molybdenum, nickel, silicon, silicon carbide, silicon nitride, aluminum nitride, graphite, diamond, or combinations thereof, as taught by Refai-Ahmed, in order to thermally manage the heat generated from the chip stack (Refai-Ahmed ¶ 0027) thereby enhancing temperature control of the package structure (Refai-Ahmed ¶ 0005).
Allowable Subject Matter
Regarding Claim 11, the prior art does not teach or render obvious wherein the first bridge and the second bridge are cube memory chips. Therefore the combination of the features of Claims 8-11 is considered allowable.
Response to Arguments
In their amendment and response dated 6-23-2026, the Applicant states (pages 7 and 10 of 12) that “”every disclosed embodiment in the reference includes TSVs”, “It appears that every single embodiment of Cheah teaches TSVs in the chip stacks.”, and “the reference consistently including TSVs in all examples”
As explained supra, Cheah ¶ 0022 and ¶ 0027 disclose that vias 144, 224, and 244’ “may” be included in the chip stacks. Furthermore, ¶ 0022 describes Fig. 1B that “is a magnified view of a portion of the structure of FIG. 1A” (¶ 0006) and ¶ 0027 describes Fig. 2B that “is a magnified view of a portion of the structure of FIG. 2A”. Therefore, the embodiments of Figs. 1A-2E disclose chip stacks that “lack through-silicon vias”.
The Applicant states (page 10 of 12) Cheah has “no guidance indicating that the invention would function without TSVs”, “a person of ordinary skill would understand TSVs to be integral to that specific disclosure”, and “Cheah does not disclose, teach or enable the claimed limitation”.
As explained supra, Cheah says “may” when describing every TSV 144, 244, 244’ (¶ 0022, 0027). If all of the TSVs 144, 244, 244’ were not optional, then Cheah would indicate that TSVs 144, 244, and 244’ are required by Cheah not using the word “may” to describe every TSV 144, 244, and 244’.
The Applicant states (page 10 of 12) that “omission of TSVs would require undue experimentation.”
Cheah states in ¶ 0022 and 0027 that TSVs 144, 244, 244’ “may” be included. Therefore, it would not “require undue experimentation” (Applicants’ wording) to have chip stacks that “lack through-silicon vias” (the amendment to independent Claims 1 and 8) 144, 244, 244’.
Because Cheah uses the language “may”, the presence of the TSV is not a requirement. Therefore, no undue experimentation is required.
Independent Claims 1 and 8 are rejected for at least the reasons stated supra. Dependent Claims 2, 4-7, 9-10, and 12-24 are rejected for at least the reasons stated supra.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/R.K./Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818
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