DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on September 1, 2026 has been entered.
Response to Amendment
Election/Restrictions
Restriction to one of the following inventions is required under 35 U.S.C. 121:
I. Claims 1-2, 4-7, 19-21, and 25-28 drawn to a package structure, classified in H10W 90/00.
II. Claims 8, 12-14, and 22-24, drawn to a package structure, classified in H10W 70/611.
Inventions I and II are directed to related products. The related inventions are distinct if: (1) the inventions as claimed are either not capable of use together or can have a materially different design, mode of operation, function, or effect; (2) the inventions do not overlap in scope, i.e., are mutually exclusive; and (3) the inventions as claimed are not obvious variants. See MPEP § 806.05(j).
In the instant case, the inventions as claimed have a materially different design, do not overlap in scope, and are not obvious variants. Specifically, invention I and specifically, Claim 8, has a first chip on a substrate, a first cube memory and a second cube memory on the first chip, and a second chip on the first cube memory and the second cube memory all lacking in invention II. While invention II describes a substrate, having chip stacks with horizontal/orthogonal bridges all lacking in invention I. Furthermore, the inventions as claimed do not encompass overlapping subject matter and there is nothing of record to show them to be obvious variants.
Restriction for examination purposes as indicated is proper because all the inventions listed in this action are independent or distinct for the reasons given above and there would be a serious search and/or examination burden if restriction were not required because one or more of the following reasons apply:
--the inventions have acquired a separate status in the art in view of their different classification;
--the inventions have acquired a separate status in the art due to their recognized divergent subject matter; and/or
--the inventions require a different field of search (e.g., searching different classes/subclasses or electronic resources, or employing different search strategies or search queries).
Additionally, newly submitted claims 8, 12-14, and 22-24 are directed to an invention that is independent or distinct from the invention originally claimed for the following reasons:
The inventions as claimed have a materially different design, do not overlap in scope, and are not obvious variants. Specifically, totally rewritten Claim 8 has a first chip on a substrate, a first cube memory and a second cube memory on the first chip, and a second chip on the first cube memory and the second cube memory, while many of the original limitations in claim 8 have been deleted (as seen in the amendment filed on September 1, 2026 and those limitations were related to invention I as described above). Furthermore, the inventions as claimed do not encompass overlapping subject matter and there is nothing of record to show them to be obvious variants.
Since Applicant has received an action on the merits for the originally presented invention, this invention has been constructively elected by original presentation for prosecution on the merits. Therefore, invention I, directed to claims 1-2, 4-7, 19-21, and 25-28 is examined below. Accordingly, claims 8, 12-14, and 22-24 are withdrawn from consideration as being directed to a non-elected invention. See 37 CFR 1.142(b) and MPEP § 821.03.
To preserve a right to petition, the reply to this action must distinctly and specifically point out supposed errors in the restriction requirement. Otherwise, the election shall be treated as a final election without traverse. Traversal must be timely. Failure to timely traverse the requirement will result in the loss of right to petition under 37 CFR 1.144. If claims are subsequently added, applicant must indicate which of the subsequently added claims are readable upon the elected invention.
Should applicant traverse on the ground that the inventions are not patentably distinct, applicant should submit evidence or identify such evidence now of record showing the inventions to be obvious variants or clearly admit on the record that this is the case. In either instance, if the examiner finds one of the inventions unpatentable over the prior art, the evidence or admission may be used in a rejection under 35 U.S.C. 103 or pre-AIA 35 U.S.C. 103(a) of the other invention.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 4-7, and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Cheah et al. (“Cheah”), US 2016/0005718 (listed in the IDS filed 9-25-2024), in view of Bartley et al. “Bartley”), US 2012/0007229.
Regarding Claim 1, Cheah discloses a package structure (Figs. 1A-1B, 2A-2B; ¶ 0021, 0025), comprising:
a substrate (246; Fig. 2A; ¶ 0027 “package substrate…246”) having an upper surface (Fig. 2A the upper surface of substrate 246);
a first chip package (220; Fig. 2A; ¶ 0025 “main stacked dies (MSD) structures 220”) positioned on the upper surface of the substrate (Fig. 2A; ¶ 0022 “MSD structure…may be disposed above a package substrate”), the first chip package comprising a first chip stack including a plurality of vertically stacked first chips (122, 124, 126, 128, 130, 132, 134; Figs. 1A, Fig. 2A not labeled in Fig. 2A; ¶ 0021 “MSD structure…includes stacked dies 122, 124, 126, 128, 130, 132 and 134”), a first chip (122; Figs. 1A, 2A not labeled in Fig. 2A; ¶ 0021 “MSD structure…includes stacked dies 122”) of the plurality of vertically stacked first chips (Fig. 2A) having a first integrated circuit (¶ 0023 “the dies of the MSD structure…are silicon dies such as, but not limited to, logic or memory based devices, e.g., processor, chipset, memory flash, sensor, optical and MEMS etc.”) connected to a first redistribution layer (123; Figs. 1A, 2A not labeled in Fig. 2A; ¶ 0021 “Corresponding active layers 123…are also shown”);
a second chip package (221; Fig. 2A; ¶ 0025 “main stacked dies (MSD) structures…221”) positioned on the upper surface of the substrate (Fig. 2A; ¶ 0022 “MSD structure…may be disposed above a package substrate”), the second chip package comprising a second chip stack including a plurality of vertically stacked second chips (122, 124, 126, 128, 130, 132, 134; Figs. 1A, 2A not labeled in Fig. 2A; ¶ 0021 “MSD structure…includes stacked dies 122, 124, 126, 128, 130, 132 and 134”), a second chip (122; Figs. 1A, 2A not labeled in Fig. 2A; ¶ 0021 “MSD structure…includes stacked dies 122”) of the plurality of vertically stacked second chips (Fig. 2A) having a second integrated circuit (¶ 0023 “the dies of the MSD structure…are silicon dies such as, but not limited to, logic or memory based devices, e.g., processor, chipset, memory flash, sensor, optical and MEMS etc.”) connected to a second redistribution layer (123; Figs. 1A, 2A not labeled in Fig. 2A; ¶ 0021 “Corresponding active layers 123…are also shown.”);
an orthogonal bridge (201; Figs. 2A-2B; ¶ 0025 “an intermediate vertical side chip (i-VSC) 201 coupled to two main stacked dies (MSD) structures 220 and 221”) positioned between the first chip package and the second chip package (Figs. 2A-2B; ¶ 0025 “an intermediate vertical side chip (i-VSC) 201 coupled to two main stacked dies (MSD) structures 220 and 221”) and having an interconnection (204, 262; Figs. 2A-2B; ¶ 0025 “One or more VSC interconnections 204”and “One or more VSC interconnections 262”) to the first redistribution layer (Figs. 2A-2B; ¶ 0025 “One or more VSC interconnections 204…couples the active layer 202 of the i-VSC 201 to the MSD structure 220.”, ¶ 0026 “die side pad structure 236, of one or more of the stacked dies of the MSD structure 220 may be included for coupling with the i-VSC interconnections 204” and “die backside metal routing 238 of one or more of the stacked dies of the MSD structure 220 may be included for coupling with the i-VSC interconnections 204”) and the second redistribution layer (Figs. 2A-2B; ¶ 0025 “One or more VSC interconnections 262…couples the die backside metal routing 260 of the i-VSC 201 to the MSD structure 221”, ¶ 0026 “die side pad structure 236′, of one or more of the stacked dies of the MSD structure 221 may be included for coupling with the i-VSC interconnections 262” and “die backside metal routing 238′ of one or more of the stacked dies of the MSD structure 221 may be included for coupling with the VSC interconnections 262”); and
wherein the orthogonal bridge is arranged substantially orthogonal to the upper surface of the substrate (Fig. 2A; ¶ 0024, ¶ 0025 “packaging system includes an intermediate vertical side chip (i-VSC) 201”).
Cheah does not disclose a heat spreader positioned in direct contact with edges of intermediate first chips of the plurality of vertically stacked first chips within the first chip stack and edges of intermediate second chips of the plurality of vertically stacked second chips within the second chip stack.
Bartley discloses a heat spreader (240; Fig. 4; ¶ 0021 “Thermal Interface Material (TIM) 240”) positioned in direct contact (Fig. 4; ¶ 0030 “TIM 240 is disposed on the…surface of…the top-most computing component 231”) with edges of intermediate first chips (leftmost edges of 124, 126, 128, 130, 132 of first chip package 220; Fig. 2A; ¶ 0021 “MSD structure…includes stacked dies…124, 126, 128, 130, 132”) of the plurality of vertically stacked first chips within the first chip stack (Fig. 2A in this instance it is obvious to put TIM 240 in direct contact with edges of intermediate first chips because the heat spreader 240 would beneficially remove heat from the edges of those intermediate first chips) and edges of intermediate second chips (rightmost edges of 124, 126, 128, 130, 132 of second chip package 221; Fig. 2A; ¶ 0021 “MSD structure…includes stacked dies…124, 126, 128, 130, 132”) of the plurality of vertically stacked second chips within the second chip stack (Fig. 2A in this instance it is obvious to put TIM 240 in direct contact with edges of intermediate second chips because the heat spreader 240 would beneficially remove heat from the edges of those intermediate second chips).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for Cheah to have a heat spreader positioned in direct contact with edges of intermediate first chips of the plurality of vertically stacked first chips within the first chip stack and edges of intermediate second chips of the plurality of vertically stacked second chips within the second chip stack, as taught by Bartley because it “improves the die stack…interconnect reliability” (Bartley ¶ 0024), provides overall mechanical support for the chip package (Bartley ¶ 0024, 0030), and beneficially removes heat to improve the reliability of the package structure.
Regarding Claim 4, Cheah discloses wherein the interconnection of the orthogonal bridge to the first redistribution layer and the second redistribution layer includes solder interconnections (¶ 0025 “One or more VSC interconnections 204, e.g., one or more solder bumps, couples the active layer 202 of the i-VSC 201 to the MSD structure 220.” and “One or more VSC interconnections 262, e.g., one or more solder bumps, couples the die backside metal routing 260 of the i-VSC 201 to the MSD structure 221.”).
Regarding Claim 5, Cheah discloses wherein the plurality of vertically stacked first chips in the first chip package are connected to each other via bonding (¶ 0023 “surface activated bonding (SAB)” and “the dies within the MSD structure…are electrically coupled to one another through SAB at the corresponding active layers” noting that this is a method of connecting in a structure claim), and wherein the plurality of vertically stacked second chips in the second chip package are connected to each other via bonding (¶ 0023 “surface activated bonding (SAB)” and “the dies within the MSD structure…are electrically coupled to one another through SAB at the corresponding active layers” noting that this is a method of connecting in a structure claim).
Cheah as modified lacks specifically disclosing wherein the bonding is specifically thermal compression bonding.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for Cheah as modified to have wherein the plurality of vertically stacked first chips in the first chip package are connected to each other via thermal compression bonding, and wherein the plurality of vertically stacked second chips in the second chip package are connected to each other via thermal compression bonding, because surface activated bonding and thermal compression bonding are both well known; however, in some instances thermal activated bonding would be chosen over surface activated bonding to have the advantages of bonding strength from both mechanical interlock and atomic diffusion, direct electrical interconnect structures without additional steps beside the surface mounting process, and a bonding process that uses localized heating and rapid cooling.
Regarding Claim 6, Cheah discloses wherein the plurality of vertically stacked first chips in the first chip package are separated by first bumps (236; Fig. 2B (shown but not labeled in Fig. 2A); ¶ 0026 “pad structure 236”), and wherein the plurality of vertically stacked second chips in the second chip package are separated by second bumps (236’; Fig. 2B (shown but not labeled in Fig. 2A); ¶ 0026 “pad structure 236′ ”).
Regarding Claim 7, Cheah discloses wherein the orthogonal bridge comprises one or more of silicon, silicon carbide, silicon dioxide, diamond, a silicon nitride, a glass, a dielectric material, a solder material (¶ 0026 “i-VSC interconnections 204” and “i-VSC interconnections 262”, ¶ 0025 “One or more VSC interconnections 204, e.g., one or more solder bumps, couples the active layer 202 of the i-VSC 201 to the MSD structure 220.” and “One or more VSC interconnections 262, e.g., one or more solder bumps, couples the die backside metal routing 260 of the i-VSC 201 to the MSD structure 221.”), polymer, copper, tantalum, tantalum nitride, nickel, gold, aluminum nitride, indium, or combinations thereof.
Regarding Claim 21, Cheah discloses wherein the first chip stack (220) has a first planarized lateral surface (248; Fig. 2A; ¶ 0027 “MSD structures 220…may be disposed above…material layer 248”) on which a first lateral redistribution layer (135; Figs. 1A, 2A not labeled in Fig. 2A; ¶ 0021 “Corresponding active layers…135”) is disposed (Fig. 2A), the first lateral redistribution layer being connected to the first redistribution layer and to the orthogonal bridge (Figs. 2A-2C; ¶ 0025 “One or more VSC interconnections 204, e.g., one or more solder bumps, couples the active layer 202 of the i-VSC 201 to the MSD structure 220.” therefore, the first lateral redistribution layer is connected to the first redistribution layer and to the orthogonal bridge), and wherein the second chip stack (221) has a second planarized lateral surface (248; Fig. 2A; ¶ 0027 “MSD structures…221 may be disposed above…material layer 248”) on which a second lateral redistribution layer (135; Figs. 1A, 2A not labeled in Fig. 2A; ¶ 0021 “Corresponding active layers…135”) is disposed (Fig. 2A), the second lateral redistribution layer being connected to the second redistribution layer and to the orthogonal bridge (Figs. 2A-2C; ¶ 0025 “One or more VSC interconnections 262, e.g., one or more solder bumps, couples the die backside metal routing 260 of the i-VSC 201 to the MSD structure 221.” therefore the second lateral redistribution layer is connected to the second redistribution layer and to the orthogonal bridge).
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Cheah et al. (“Cheah”), US 2016/0005718 (listed in the IDS filed 9-25-2024) and Bartley et al. “Bartley”), US 2012/0007229, as applied to independent Claim 1, in view of Refai-Ahmed et al. (“Refai-Ahmed”), US 2018/0308783.
Regarding Claim 2, Cheah as modified by Bartley does not disclose wherein the heat spreader comprises at least one of aluminum, copper, tungsten, molybdenum, nickel, silicon, silicon carbide, silicon nitride, aluminum nitride, graphite, diamond, or combinations thereof.
Refai-Ahmed discloses wherein the heat spreader (102; Fig. 1; ¶ 0027) comprises at least one of aluminum, copper, tungsten, molybdenum, nickel, silicon, silicon carbide, silicon nitride, aluminum nitride, graphite, diamond, or combinations thereof (¶ 0027 “suitable materials for fabricating the heat sink 102 include copper…or aluminum”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for Cheah as modified to have wherein the heat spreader comprises at least one of aluminum, copper, tungsten, molybdenum, nickel, silicon, silicon carbide, silicon nitride, aluminum nitride, graphite, diamond, or combinations thereof, as taught by Refai-Ahmed, in order to thermally manage the heat generated from the chip package (Refai-Ahmed ¶ 0027) thereby enhancing temperature control of the package structure (Refai-Ahmed ¶ 0005).
Claims 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Cheah et al. (“Cheah”), US 2016/0005718 (listed in the IDS filed 9-25-2024), in view of Bartley et al. “Bartley”), US 2012/0007229, as applied to Claim 1, and further in view of Kim et al. “Kim”), US 2020/0243422.
Regarding Claim 19, Cheah as modified by Bartley does not disclose
wherein, for each pair of vertically adjacent first chips of the plurality of vertically stacked first chips, a plurality of the first bumps is disposed between the pair of vertically adjacent first chips, each first bump of the plurality of the first bumps being disposed on a lower surface of an upper first chip of the pair and directly contacting an upper surface of a lower first chip of the pair, and wherein, for each pair of vertically adjacent second chips of the plurality of vertically stacked second chips, a plurality of the second bumps is disposed between the pair of vertically adjacent second chips, each second bump of the plurality of the second bumps being disposed on a lower surface of an upper second chip of the pair and directly contacting an upper surface of a lower second chip of the pair.
Kim discloses
wherein, for each pair of vertically adjacent first chips of the plurality of vertically stacked first chips (301; Figs. 1, 3; ¶ 0044 “stack 300 may be formed by vertically stacking the second semiconductor dies 301”), a plurality of the first bumps (970: Fig. 1; ¶ 0044 “semiconductor dies 301 may be electrically connected to each other by…connectors 970”) is disposed between the pair of vertically adjacent first chips (Fig. 1; ¶ 0044 “semiconductor dies 301 may be electrically connected to each other by…connectors 970”), each first bump of the plurality of the first bumps being disposed on a lower surface of an upper first chip of the pair (Fig. 1 in this instance an upper first chip is the top chip 301) and directly contacting an upper surface of a lower first chip of the pair (Fig. 1 in this instance a lower first chip is the second-to-top chip 301).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for Cheah as modified to have wherein, for each pair of vertically adjacent first chips of the plurality of vertically stacked first chips, a plurality of the first bumps is disposed between the pair of vertically adjacent first chips, each first bump of the plurality of the first bumps being disposed on a lower surface of an upper first chip of the pair and directly contacting an upper surface of a lower first chip of the pair, as taught by Kim, because a data transmission speed between the first chip stack and the first horizontal bridge is improved (Kim ¶ 0049), thereby “enhancing the performance” of the package structure (Kim ¶ 0047. 0049).
Cheah as modified does not specifically disclose
wherein, for each pair of vertically adjacent second chips of the plurality of vertically stacked second chips, a plurality of the second bumps is disposed between the pair of vertically adjacent second chips, each second bump of the plurality of the second bumps being disposed on a lower surface of an upper second chip of the pair and directly contacting an upper surface of a lower second chip of the pair.
MPEP 2144.04 VI B states that mere duplication of parts has no patentable significance unless a new and unexpected result is produced. In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960).
As noted, supra, Kim discloses all the elements claimed for the first chip stack, and it would be known in the art that when multiple chip stacks are present, you would want to include the enhancement on all the chip stacks and not just one.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for Cheah as modified to have wherein, for each pair of vertically adjacent second chips of the plurality of vertically stacked second chips, a plurality of the second bumps is disposed between the pair of vertically adjacent second chips, each second bump of the plurality of the second bumps being disposed on a lower surface of an upper second chip of the pair and directly contacting an upper surface of a lower second chip of the pair (the argument being if you are enhancing one chip stack, you should enhance the others that are present too), as taught by Kim, because a data transmission speed between the second chip stack and the second horizontal bridge is improved (Kim ¶ 0049), thereby “enhancing the performance” of the package structure (Kim ¶ 0047. 0049) and further increasing the functionality of the package structure.
Regarding Claim 20, Cheah as modified does not disclose
wherein, at each interface between a pair of vertically adjacent first chips, the plurality of the first bumps is arranged in a row along the lower surface of the upper first chip, and wherein, at each interface between a pair of vertically adjacent second chips, the plurality of the second bumps is arranged in a row along the lower surface of the upper second chip.
Kim discloses
wherein, at each interface between (Fig. 1; ¶ 0044 “semiconductor dies 301 may be electrically connected to each other by…connectors 970”) a pair of vertically adjacent first chips (301), the plurality of the first bumps (970) is arranged in a row (Fig. 1 noting that the bumps 970 are in a row; ¶ 0044 “semiconductor dies 301 may be electrically connected to each other by…connectors 970”) along the lower surface of the upper first chip (Fig. 1).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for Cheah as modified to have wherein, at each interface between a pair of vertically adjacent first chips, the plurality of the first bumps is arranged in a row along the lower surface of the upper first chip, as taught by Kim, because a data transmission speed between the first chip stack and the first horizontal bridge is improved (Kim ¶ 0049), thereby “enhancing the performance” of the package structure (Kim ¶ 0047. 0049).
Cheah as modified by Kim does not specifically disclose
wherein, at each interface between a pair of vertically adjacent second chips, the plurality of the second bumps is arranged in a row along the lower surface of the upper second chip.
MPEP 2144.04 VI B states that mere duplication of parts has no patentable significance unless a new and unexpected result is produced. In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960).
As noted, supra, Kim discloses all the elements claimed for interfaces in the first chip stack, and it would be known in the art that when multiple chip stacks are present, you would want to include the enhancement on all the chip stacks and not just one.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for Cheah as modified to have wherein, at each interface between a pair of vertically adjacent second chips, the plurality of the second bumps is arranged in a row along the lower surface of the upper second chip, because a data transmission speed between the second chip stack and the second horizontal bridge is improved (Kim ¶ 0049), thereby “enhancing the performance” of the package structure (Kim ¶ 0047. 0049) and further increasing the functionality of the package structure.
Claims 25-28 are rejected under 35 U.S.C. 103 as being unpatentable over Cheah et al. (“Cheah”), US 2016/0005718 (listed in the IDS filed 9-25-2024), in view of Kim et al. “Kim”), US 2020/0243422.
Regarding Claim 25, Cheah discloses a package structure (Figs. 1A-1B, ¶ 0021, 0025), comprising:
a substrate (246; Fig. 2A; ¶ 0027 “package substrate…246”) having an upper surface (Fig. 2A the upper surface of substrate 246);
a first chip stack (220; Fig. 2A; ¶ 0025 “main stacked dies (MSD) structures 220”) and a second chip stack (221; Fig. 2A; ¶ 0025 “main stacked dies (MSD) structures…221”) positioned on the upper surface of the substrate (Fig. 2A; ¶ 0022 “MSD structure…may be disposed above a package substrate”); an orthogonal bridge (201; Fig. 2A; ¶ 0025 “vertical side chip (i-VSC) 201”) positioned between (Fig. 2A) and coupled to the first chip stack and the second chip stack (Figs. 2A-2C; ¶ 0025 “intermediate vertical side chip (i-VSC) 201 coupled to two main stacked dies (MSD) structures 220 and 221”), the orthogonal bridge extending orthogonal to the upper surface of the substrate (Fig. 2A; ¶ 0024; ¶ 0025 “packaging system includes an intermediate vertical side chip (i-VSC) 201”).
Cheah does not disclose
a first chip positioned on the upper surface of the substrate;
a first horizontal bridge positioned on the substrate and coupling the first chip to the first chip stack;
a second chip positioned on the upper surface of the substrate; and
a second horizontal bridge positioned on the substrate and coupling the second chip to the second chip stack.
Kim discloses
a first chip (200; Figs. 1-2; ¶ 0025 “semiconductor die 200”) positioned on (Figs. 1-2; ¶ 0026 “first semiconductor die 200 may be disposed on a first surface 101 of the package substrate 100”) the upper surface (Figs. 1-2) of the substrate (100; Figs. 1-3; ¶ 0025 “package substrate 100”);
a first horizontal bridge (400, 500, 600, 700; Figs. 1-3; ¶ 0025 “die assembly 400 may be configured to include a first bridge die 500, a second bridge die 600, a third semiconductor die 700”) positioned on the substrate (Figs. 1-3; ¶ 0026 “die assembly 400 may be disposed on the…package substrate 100”; ¶ 0029 “bridge die 500…may be located between the package substrate 100”; ¶ 0036 “bridge die 600…may be located between the package substrate 100”; ¶ 0042 “semiconductor die 700 may be disposed…faces the package substrate 100”) and coupling (Figs. 1-3; ¶ 0046 “semiconductor die 200 may be electrically connected to the third semiconductor die 700”; ¶ 0047 “stack 300 may be electrically connected to the third semiconductor die 700” therefore the first chip 200 is coupled to the first chip stack 300) the first chip to the first chip stack (300; Figs. 1, 3; ¶ 0025 “stack 300 of second semiconductor dies 301”; ¶ 0026 “stack 300 may be laterally spaced apart from the first semiconductor die 200”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for Cheah to have a first chip positioned on the upper surface of the substrate; a first horizontal bridge positioned on the substrate and coupling the first chip to the first chip stack, as taught by Kim, because a data transmission speed between the first chip and the first horizontal bridge is improved (Kim ¶ 0047), plus a data transmission speed between the first chip stack and the first horizontal bridge is improved (Kim ¶ 0049), thereby “enhancing the performance” of the package structure (Kim ¶ 0047. 0049).
Cheah as modified by Kim does not specifically disclose
a second chip positioned on the upper surface of the substrate; and
a second horizontal bridge positioned on the substrate and coupling the second chip to the second chip stack.
MPEP 2144.04 VI B states that mere duplication of parts has no patentable significance unless a new and unexpected result is produced. In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960).
As noted, supra, Kim discloses all the elements claimed for the first chip and a first horizontal bridge as related to the first chip stack, and it would be known in the art that when multiple chip stacks are present, you would want to include the enhancement on all the chip stacks and not just one.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for Cheah as modified to have a second chip positioned on the upper surface of the substrate; and a second horizontal bridge positioned on the substrate and coupling the second chip to the second chip stack, as taught by Kim, because a data transmission speed between the second chip and the second horizontal bridge is improved (Kim ¶ 0047), plus a data transmission speed between the second chip stack and the second horizontal bridge is improved (Kim ¶ 0049), thereby “enhancing the performance” of the package structure (Kim ¶ 0047. 0049) and further increasing the functionality of the package structure.
Regarding Claim 26, Cheah does not disclose
wherein the first chip stack comprises a plurality of vertically stacked first chips separated from one another by first bumps, and
wherein the second chip stack comprises a plurality of vertically stacked second chips separated from one another by second bumps.
Kim discloses
wherein the first chip stack (300) comprises a plurality of vertically stacked first chips (301; Figs. 1, 3; ¶ 0044 “stack 300 may be formed by vertically stacking the second semiconductor dies 301”) separated from one another by first bumps (970; Fig. 1; ¶ 0044 “semiconductor dies 301 may be electrically connected to each other through…connectors 970”; ¶ 0040 “connectors…may be bumps.”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for Cheah to have wherein the first chip stack comprises a plurality of vertically stacked first chips separated from one another by first bumps, as taught by Kim, because a data transmission speed between the first chip stack and the first horizontal bridge is improved (Kim ¶ 0049), thereby “enhancing the performance” of the package structure (Kim ¶ 0047. 0049).
Cheah as modified by Kim does not specifically disclose
wherein the second chip stack comprises a plurality of vertically stacked second chips separated from one another by second bumps.
MPEP 2144.04 VI B states that mere duplication of parts has no patentable significance unless a new and unexpected result is produced. In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960).
Kim discloses
wherein the second chip stack (300) comprises a plurality of vertically stacked second chips (301; Figs. 1, 3; ¶ 0044 “stack 300 may be formed by vertically stacking the second semiconductor dies 301”) separated from one another by second bumps (970; Fig. 1; ¶ 0044 “semiconductor dies 301 may be electrically connected to each other through…connectors 970”; ¶ 0040 “connectors…may be bumps.”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for Cheah as modified to have wherein the second chip stack comprises a plurality of vertically stacked second chips separated from one another by second bumps, as taught by Kim, because a data transmission speed between the second chip stack and the second horizontal bridge is improved (Kim ¶ 0049), thereby “enhancing the performance” of the package structure (Kim ¶ 0047. 0049) and further increasing the functionality of the package structure.
Regarding Claim 27, Cheah does not specifically disclose
wherein, for each pair of vertically adjacent first chips, a plurality of the first bumps is disposed between the pair of vertically adjacent first chips, each first bump of the plurality of the first bumps being disposed on a lower surface of an upper first chip of the pair and directly contacting an upper surface of a lower first chip of the pair, and
wherein, for each pair of vertically adjacent second chips, a plurality of the second bumps is disposed between the pair of vertically adjacent second chips, each second bump of the plurality of the second bumps being disposed on a lower surface of an upper second chip of the pair and directly contacting an upper surface of a lower second chip of the pair.
Kim discloses
wherein, for each pair of vertically adjacent first chips (301), a plurality of the first bumps (970) is disposed between the pair of vertically adjacent first chips (Fig. 1; ¶ 0044 “semiconductor dies 301 may be electrically connected to each other through the…connectors 970”), each first bump of the plurality of the first bumps being disposed on a lower surface of an upper first chip of the pair (Fig. 1 in this instance an upper first chip is the top chip 301) and directly contacting (Fig. 1) an upper surface of a lower first chip of the pair (Fig. 1 in this instance a lower first chip is the second-to-top chip 301).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for Cheah to have wherein, for each pair of vertically adjacent first chips, a plurality of the first bumps is disposed between the pair of vertically adjacent first chips, each first bump of the plurality of the first bumps being disposed on a lower surface of an upper first chip of the pair and directly contacting an upper surface of a lower first chip of the pair, as taught by Kim, because a data transmission speed between the first chip stack and the first horizontal bridge is improved (Kim ¶ 0049), thereby “enhancing the performance” of the package structure (Kim ¶ 0047. 0049).
MPEP 2144.04 VI B states that mere duplication of parts has no patentable significance unless a new and unexpected result is produced. In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960).
Cheah as modified by Kim does not specifically disclose
wherein, for each pair of vertically adjacent second chips, a plurality of the second bumps is disposed between the pair of vertically adjacent second chips, each second bump of the plurality of the second bumps being disposed on a lower surface of an upper second chip of the pair and directly contacting an upper surface of a lower second chip of the pair.
Kim discloses
wherein, for each pair of vertically adjacent second chips (301), a plurality of the second bumps (970) is disposed between the pair of vertically adjacent second chips (Fig. 1; ¶ 0044 “semiconductor dies 301 may be electrically connected to each other through the…connectors 970”), each second bump of the plurality of the second bumps being disposed on a lower surface of an upper second chip of the pair (Fig. 1 in this instance an upper second chip is the top chip 301) and directly contacting (Fig. 1) an upper surface of a lower second chip of the pair (Fig. 1 in this instance a lower second chip is the second-to-top chip 301).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for Cheah as modified to have wherein, for each pair of vertically adjacent second chips, a plurality of the second bumps is disposed between the pair of vertically adjacent second chips, each second bump of the plurality of the second bumps being disposed on a lower surface of an upper second chip of the pair and directly contacting an upper surface of a lower second chip of the pair, as taught by Kim, because a data transmission speed between the second chip stack and the second horizontal bridge is improved (Kim ¶ 0049), thereby “enhancing the performance” of the package structure (Kim ¶ 0047. 0049) and further increasing the functionality of the package structure.
Regarding Claim 28, Cheah does not disclose
wherein, at each interface between a pair of vertically adjacent first chips, the plurality of the first bumps is arranged in a row along the lower surface of the upper first chip, and
wherein, at each interface between a pair of vertically adjacent second chips, the plurality of the second bumps is arranged in a row along the lower surface of the upper second chip.
Kim discloses
wherein, at each interface between (Fig. 1; ¶ 0044 “semiconductor dies 301 may be electrically connected to each other through the…connectors 970”) a pair of vertically adjacent first chips (301), the plurality of the first bumps (970) is arranged in a row (Fig. 1 noting that bumps 970 are in a row; ¶ 0044 “semiconductor dies 301 may be electrically connected to each other through the…connectors 970”) along the lower surface of the upper first chip (Fig. 1).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for Cheah to have wherein, at each interface between a pair of vertically adjacent first chips, the plurality of the first bumps is arranged in a row along the lower surface of the upper first chip, as taught by Kim, because a data transmission speed between the first chip stack and the first horizontal bridge is improved (Kim ¶ 0049), thereby “enhancing the performance” of the package structure (Kim ¶ 0047. 0049).
Cheah as modified by Kim does not specifically disclose
wherein, at each interface between a pair of vertically adjacent second chips, the plurality of the second bumps is arranged in a row along the lower surface of the upper second chip.
MPEP 2144.04 VI B states that mere duplication of parts has no patentable significance unless a new and unexpected result is produced. In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960).
Kim discloses
wherein, at each interface between (Fig. 1; ¶ 0044 “semiconductor dies 301 may be electrically connected to each other through the…connectors 970”) a pair of vertically adjacent second chips (301), the plurality of the second bumps (970) is arranged in a row (Fig. 1 noting that bumps 970 are in a row; ¶ 0044 “semiconductor dies 301 may be electrically connected to each other through the…connectors 970”) along the lower surface of the upper second chip (Fig. 1).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for Cheah as modified to have wherein, at each interface between a pair of vertically adjacent second chips, the plurality of the second bumps is arranged in a row along the lower surface of the upper second chip, as taught by Kim, because a data transmission speed between the second chip stack and the second horizontal bridge is improved (Kim ¶ 0049), thereby “enhancing the performance” of the package structure (Kim ¶ 0047. 0049) and further increasing the functionality of the package structure.
Response to Arguments
In their amendment and response dated 9-1-2026, the applicant states (page 11) that “original claims 8-11 contained allowable subject matter” and “Claims 9-11 are canceled”. The applicant also states (page 13) that “Neither CHEAH nor BARTLEY discloses the quoted features of amended claim 8.”
Because there was prosecution on the elected original Claim 1, the totally rewritten amended independent Claim 8 has been withdrawn as distinct from the invention originally claimed, as explained supra.
The applicant states (page 12) that “Neither CHEAH nor BARTLEY discloses the heat spreader contact recited in amended claim 1, including direct contact with "edges of intermediate first chips of the plurality of vertically stacked first chips within the first chip stack" and "edges of intermediate second chips of the plurality of vertically stacked second chips within the second chip stack."
As explained supra, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for Cheah to have a heat spreader positioned in direct contact with edges of intermediate first chips of the plurality of vertically stacked first chips within the first chip stack and edges of intermediate second chips of the plurality of vertically stacked second chips within the second chip stack, as taught by Bartley because it “improves the die stack…interconnect reliability” (Bartley ¶ 0024), provides overall mechanical support for the chip package (Bartley ¶ 0024, 0030), and beneficially removes heat to improve the reliability of the package structure.
The applicant states (page 13) that “Applicant respectfully submits that the cited portions of CHEAH and BARTLEY do not disclose the features recited in amended claim 5.”
As explained supra, Claim 5 is rendered obvious by Cheah. It is noted that Claim 5 includes a method of connecting in a structure claim, though the structure implied by the method. See MPEP 2113 as to how product by process claims are examined. Any differences in the prior art and the claim invention would be better addressed if the claims defined a clear structural difference that is present because of thermal compression bonding
The applicant states (page 14) that “Claim 2 depends from amended claim 1…REFAI-AHMED does not cure the deficiencies of CHEAH and BARTLEY discussed above with respect to amended claims 1’.
As explained supra, Refai-Ahmed discloses wherein the heat spreader (102; Fig. 1; ¶ 0027) comprises at least one of aluminum, copper, tungsten, molybdenum, nickel, silicon, silicon carbide, silicon nitride, aluminum nitride, graphite, diamond, or combinations thereof (¶ 0027 “suitable materials for fabricating the heat sink 102 include copper…or aluminum”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for Cheah as modified to have wherein the heat spreader comprises at least one of aluminum, copper, tungsten, molybdenum, nickel, silicon, silicon carbide, silicon nitride, aluminum nitride, graphite, diamond, or combinations thereof, as taught by Refai-Ahmed, in order to thermally manage the heat generated from the chip package (Refai-Ahmed ¶ 0027) thereby enhancing temperature control of the package structure (Refai-Ahmed ¶ 0005).
The applicant states (page 14) that “Therefore, new claims 19-21 are patentable for at least the reasons given above with respect to claim 1 and for the additional distinguishing features recited therein.”
As explained supra, new claims 19-20 are disclosed by Cheah in view of Bartley, and further in view of Kim.
Also as explained supra, new claim 21 is disclosed by Cheah.
The applicant states (page 15) that “new independent claim 25 is patentable over the applied references.” and “new claims 26-28 are patentable for at least the reasons given above with respect to new independent claim 25 and for the additional distinguishing features recited therein.”
As explained supra, new claims 25-28 are rejected over Cheah in view of Kim.
Independent Claims 1 and 25 are rejected for at least the reasons stated supra. Dependent Claims 2, 4-7, 19-21 and 26-28 are rejected for at least the reasons stated supra.
Conclusion
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/R.K./Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818
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