DETAILED ACTION
Response to Arguments
The Examiner acknowledges the change of the title of the invention to “DISPLAY DEVICE INCLUDING AUXILIARY ELECTRODE INCLUDING BONDING PORTION HAVING PLURAL WIDTHS”. The specification objection has been withdrawn.
Applicant’s arguments, with respect to the drawing objection have been fully considered and are persuasive. The drawing objection has been withdrawn.
Applicant’s arguments in regard to claim 17 filed 12/24/2025 have been fully considered and are persuasive. Therefore, the 35 U.S.C 112(a) rejection has been withdrawn.
Applicant’s arguments in regard to claims 3 and 9-11 filed 12/24/2025 have been fully considered and are persuasive. Therefore, the 35 U.S.C 112(b) rejection has been withdrawn.
Applicant’s arguments filed 12/24/2025have been fully considered but are not persuasive.
Applicant argues on page 4 of the instant Remarks:
“Cho does not teach or suggest:
... alight-emitting element layer disposed on the substrate, the light-emitting element
layer comprising: ... a second common layer disposed on the light-emitting layer and
comprising an electron transport layer including an organic material having an
electron transport property: and a common electrode disposed on the second common
layer, ... the first bonding portion in contact with the second common layer, and
the second bonding portion in contact with the common electrode ... the first bonding
portion has a first width at a first point of the first side and has a second width
smaller than the first width at a second point of the third side " (emphasis added).
The examiner respectfully disagrees with this assessment. Applicant asserts that the first bonding portions of the device are the portions where the common layer CL contacts the power supply wires VL as shown in annotated Fig. 7 (see for example Applicant Arguments/Remarks pg. 7). This incorrectly illustrates the first bonding portion stated in the rejection which is stated to be the portion where a second electrode 183 contacts the second conductive layer VL2 where the second bonding partition is stated to be the portion where a common layer CL contacts the second conductive layer VL2. While the claim requires the first bonding portion to be in contact with the second common layer. There is no limiting language that specifies the placement of the first bonding portion nor is there limiting language that specifies the components that comprise the first bonding portion. Without any further limiting language, the portion where the common layer CL which contains the ETL/EIL that contacts the second conductive layer VL2, would be in electrical contact with the portion of the second electrode 183 that contacts the second conductive layer VL2 which functions as the first bonding portion. This also serves to refute Applicant’s assertion that Cho discloses that the first bonding portion has the same/symmetrical width on opposite sides. Further, while the amendment serves to further limit the second common layer, the amendment does not serve to refute the previous rejection of claim 1.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 3-9 are rejected under 35 U.S.C. 103 as being unpatentable over Cho et al. (US 2021/0202655 A1; hereinafter “Cho”) and further in view of Choi et al. (US 2017/0278910 A1; hereinafter “Choi”).
In regard to claim 1, Cho teaches a display device (a display apparatus) (Fig. 1 and paragraph 51), comprising:
a substrate (a base substrate 100) comprising a display area (a display area DA ) in which emission areas (areas containing a light-emitting structure 180) are arranged (the cross section of the display area containing the base substrate 100 and areas containing the light-emitting structure 180 are shown in Fig. 2) (Fig. 1, Fig. 2 and paragraphs 31, 51and 60);
an auxiliary electrode (a power supply wire VL) disposed on the substrate (the power supply wire VL may be the auxiliary wire) (Fig. 2 and paragraph 58), corresponding to at least a part of a non-emission area (areas outside the light-emitting structure 180) around each of the emission areas (the power supply wire VL is shown in the areas outside the light-emitting structure 180 in Fig. 2), the auxiliary electrode comprising:
metal layers (conductive layers VL1-VL3) stacked in an undercut structure (the first through third conductive layers VL1-VL3 are shown stacked in an undercut structure in Fig. 7) (Fig. 7 and paragraph 98);
a side surface (a side surface power supply wires VL) including a first bonding portion (the portion where a second electrode 183 contacts the second conductive layer VL2) and a second bonding portion (the portion where a common layer CL contacts the second conductive layer VL2) (Fig. 7 and paragraph 97); and
a first side (a side surface of the power supply wires VL annotated as 1ss) and a second side (a side surface of the power supply wires VL annotated as 2ss) facing each other in a first direction (with evidence given from associated figure 9 which gives the orientation of the power supply wires VL, the side surfaces 1ss and 2ss face each other in the second direction D2 as shown in annotated Fig. 8 below) (annotated Fig. 8, Fig. 9), and a third side (a side surface of the power supply wires VL annotated as 3ss) and a fourth side (a side surface of the power supply wires VL annotated as 4ss) facing each other in a second direction crossing the first direction (the side surfaces 3ss and 4ss face each other in the second direction DR2 as shown in annotated Fig. 8 below) (annotated Fig. 8 and paragraph 106);
a light-emitting element layer (the layer containing the light-emitting structure 180) disposed on the substrate (Fig. 2 and paragraph 60), the light-emitting element layer comprising:
a pixel electrode (a first electrode 181) corresponding to each of the emission areas (the first electrode 181 is shown in the areas containing the light-emitting structure 180 in Fig. 2) (Fig. 2 and paragraph 60);
a pixel defining layer (a pixel defining layer PDL) corresponding to the non-emission area and covering an edge of the pixel electrode (a pixel defining layer PDL is shown on the first electrode 181 in Fig. 2) (Fig. 2 and paragraph 60);
a first common layer disposed on the pixel electrode (a hole injection layer HIL and a hole transport layer HTL function as the first common layer and are shown disposed on the first electrode 181 in Fig. 2) (Fig. 2 and paragraph 60);
a light-emitting layer disposed on the first common layer (a light-emitting layer EL is shown disposed on the HIL/HTL in Fig. 2) (Fig. 2 and paragraph 77);
a second common layer disposed on the light-emitting layer and comprising an electron transport layer (an electron transport layer ETL and an electron injection layer EIL function as the second common layer and are shown disposed on top of the light-emitting layer EL in Fig. 4) (Fig. 2, Fig. 4 and paragraph 77); and
a common electrode (a second electrode 183 ) disposed on the second common layer (the second electrode 183 is shown disposed on the ETL/EIL in Fig. 4) (Fig. 2, Fig. 4, and paragraph 79), wherein the second common layer and the common electrode extend to the non-emission area (the ETL/EIL and second electrode 183 are formed over the whole base substrate and are shown extending to the areas outside the light-emitting structure 180 in Fig. 2) (Fig. 2 and paragraphs 77, 79, 121 and 123),
the first bonding portion in contact with the second common layer, and the second bonding portion in contact with the common electrode (the portion where a common layer CL which contains the ETL/EIL that contacts the second conductive layer VL2 would be in electrical contact with the portion of the second electrode 183 that contacts the second conductive layer VL2 which functions as the first bonding portion) (Fig. 2),
the common electrode is electrically connected to the auxiliary electrode by the second bonding portion (due to the HIL/ETL being layered and directly contacting the second electrode 183, the aforementioned second bonding portion is responsible for electrically connecting to the power supply wire VL to the second electrode 183) (Fig. 2 and paragraph 80).
However, Cho discloses the claimed device except for, the second common layer disposed on the light-emitting layer and comprises an electron transport layer including an organic material having an electron transport property;
the first bonding portion has a first width at a first point of the first side and has a second width smaller than the first width at a second point of the third side. However, Cho does disclose that it the second electrode 183 is formed over the whole base substrate 100 and contacts the second conductive layer VL2 of the power supply VL (paragraphs 99-100 and 123-124). Due to the second electrode being deposited using an open mask and fully contacting the power supply wires VL, with two widths on opposite sides with a contact length W2 of the second surface 2ss being smaller than a contact length W1. The Examiner takes official notice it would be obvious to one skilled in the art that there exist a gradient of the second electrode along the third side 3ss of VL with a third contact length W3 that is between the contact lengths W2 and W1) (Fig. 7, annotated Fig. 8, paragraphs 99-100 and 123-124).
Choi teaches a display device (an organic light emitting display (OLED) device 100) (Fig. 1 and paragraph 38), comprising
a second common layer (a second common layer 325) disposed on a light-emitting layer (a first light emitting layer 331) and comprising an electron transport layer (an electron transport layer (ETL) 326) including an organic material having an electron transport property (the second common layer includes the ETL 326 which contains organic transport material as taught in paragraph 62) (Fig. 1, Fig. 2 and paragraphs 38 and 62).
It would have been obvious to one skilled in the art to combine the teachings of Cho with the teachings of Choi to have the second common layer disposed on the light-emitting layer and comprise an electron transport layer including an organic material having an electron transport property since Cho teaches the use of an electron transport layer selecting organic material for the layer is held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416.
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In regard to claim 3, Cho in view of Choi discloses the claimed invention except for wherein a difference between the first width and the second width is about 0.1 or more.
However, it would have been obvious to one having ordinary skill in the art at the time of the invention was made to have a difference between the first width and the second width is about 0.1 or more, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980). Further, where patentability is said to be based upon particular chosen dimension or upon another variable recited in a claim, the Applicant must show that the chosen dimensions are critical. In re Woodruf, 919 F.2d 1
In regard to claim 4, Cho teaches wherein the light-emitting layer and the common electrode are separated by the undercut structure of the auxiliary electrode (portions of the light-emitting layer EL are shown separated from portions of the second electrode 183 in Fig. 2).
In regard to claim 5, Cho teaches wherein the metal layers of the auxiliary electrode comprise:
a first metal layer (the second conductive layer VL2 includes aluminum) (paragraph 117); and
a second metal layer disposed on the first metal layer and having an edge protruding beyond the first metal layer (third conductive layer VL3 includes titanium and is shown protruding beyond the second conductive layer VL2 in Fig. 7) (Fig. 7 and paragraph 117),
wherein the first metal layer has a lower resistance than the second metal layer (it is known among those skilled in the art aluminum has a lower resistance than titanium), and
a side surface of the first metal layer comprises the first bonding portion and the second bonding portion (the side surface of the second conductive layer VL2 contains the first and second bonding portions as shown in Fig. 2).
In regard to claim 6, Cho teaches wherein the first metal layer comprises aluminum (Al) or copper (Cu ) (the second conductive layer VL2 may include aluminum) (paragraph 117), and
the second metal layer comprises one of titanium (Ti) (third conductive layer VL3 may include titanium) (paragraph 117), molybdenum (Mo) and indium tin oxide.
In regard to claim 7, Cho teaches wherein the metal layers of the auxiliary electrode further comprise a third metal layer (a first conductive layer VL1) disposed under the first metal layer (the first conductive layer VL1 is under the second conductive layer VL2 as shown in Fig. 2), and the third metal layer comprises one of titanium (Ti) (the first conductive layer VL1 includes titanium) (paragraph 117), molybdenum (Mo) and indium tin oxide.
In regard to claim 8, Cho teaches further comprising a sealing layer (a thin film encapsulation layer TFE) covering the light-emitting element layer (Fig. 2 and paragraph 81), wherein the side surface of the first metal layer further comprises a third bonding portion in contact with the sealing layer (the portion where the thin film encapsulation layer TFE contacts the second conductive layer VL2 functions as the third bonding portion as shown in Fig. 2).
In regard to claim 9, Cho teaches wherein a width of the third bonding portion corresponds to the undercut structure of the auxiliary electrode (the width of the portion of the thin film encapsulation layer contacting the second conductive layer VL2 would function as a third bonding portion corresponding to the undercut structure as shown in Fig, 2), and a width of the second bonding portion is a value obtained by subtracting a width of the first bonding portion and the width of the third bonding portion from a width of the side surface of the first metal layer (due to all bonding portions being located on the same side of the second conductive layer any bonding portions width could be determined by subtracting the remaining two bonding portions width from the total side length of the second conductive layer VL2 as shown in Fig. 2). 575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Cho in view of Choi as applied to claim 5 above, and further in view of Lee et al. (US 20180130827 A1; hereinafter “Lee”).
In regard to claim 12, Cho teaches further comprising a circuit layer (a layer containing a thin film transistor TFT) disposed between the substrate and the light-emitting element layer (the thin film transistor TFT is shown between the base substrate 100 and the layer containing the light-emitting structure 180 in Fig. 2) (Fig. 2 and paragraph 62),
wherein the circuit layer has a structure comprising:
a first conductive layer (a lower blocking electrode BML) disposed on the substrate (the lower blocking electrode BML is shown disposed on the base substrate 100 in Fig. 2) (Fig. 2 and paragraph 62);
a semiconductor layer (an active pattern ACT) disposed on a buffer layer (a buffer layer 110 ) covering the first conductive layer (the active pattern ACT of the thin film transistor TFT may be disposed on the buffer layer 110 as shown on Fig. 2) (Fig. 2 and paragraph 64);
a second conductive layer (a layer containing a gate electrode GE) disposed on a gate insulating layer (a gate insulating layer 120 ) covering the semiconductor layer (the gate electrode GE is shown on the gate insulating layer 120 in Fig. 2) (Fig. 2 and paragraph 60);
wherein the circuit layer comprises a pixel driver (a driving circuit for driving the display apparatus) corresponding to each of the emission areas and electrically connected to the pixel electrode (the thin film transistor includes the gate electrode which is in the same layer as the power supply wire that receives the second power supply voltage ELVSS to drive the pixel) (Fig. 1, Fig. 2 and paragraphs 13, and 55) and a first power line (a power supply line for a first power supply voltage ELVDD) and a second power line (a power supply line for the second power supply voltage ELVSS) respectively transmitting a first power (the first power supply voltage ELVDD) and a second power (the second power supply voltage ELVSS) having different voltage levels (the diving circuit layer and respective power lines extend from the non-display area adjacent to the display area DA to drive the pixels) (paragraphs 54-56).
However, Cho in view of Choi doesn’t explicitly teach a third conductive layer disposed on an inter-insulating layer covering the second conductive layer; a fourth conductive layer disposed on a first planarization layer covering the third conductive layer; and a second planarization layer covering the fourth conductive layer.
Lee teaches a display device (a display device as shown in Fig. 11) (Fig. 11 and paragraph 134), comprising a circuit layer (layers containing a storage capacitor Cst and a power line PL form the circuit layer) (Fig. 11 and paragraphs 132-133),
wherein the circuit layer has a structure comprising:
a third conductive layer (an upper electrode UE) disposed on an inter-insulating layer (a first insulating layer IL1) covering a second conductive layer (the upper electrode UE is shown on the first insulating layer IL1 which covers the gate electrode GE1) (Fig. 11 and paragraphs 183-185) ;
a fourth conductive layer (a power line PL) disposed on a first planarization layer (a second insulating layer IL2) covering the third conductive layer (the power line PL is shown on the second insulating layer IL2 which covers the upper electrode) (Fig. 11 and paragraphs 186-187); and
a second planarization layer (a protective layer PSV) covering the fourth conductive layer (the protective layer PSV is shown over the power line PL in Fig. 11) (Fig. 11 and paragraph 193).
It would have been obvious to one skilled in the art to combine the teachings of Cho in view of Choi with the teachings of Lee to have a third conductive layer disposed on an inter-insulating layer covering the second conductive layer; a fourth conductive layer disposed on a first planarization layer covering the third conductive layer; and a second planarization layer covering the fourth conductive layer since this allows for a display device with a capacitor with short protection which is known to provide pixel light stability and prevent internal device damage.
Claims 13 and 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over Cho in view of Choi and Lee as applied to claim 12 above, and further in view of Kim et al. (US 20190131375 A1; hereinafter “Kim”).
In regard to claim 13, Cho in view of Choi and Lee teach wherein the fourth conductive layer comprises a second power line (a power line PL) (Lee Fig. 6 and paragraph 133).
Cho in view of Choi and Lee don’t explicitly teach and the auxiliary electrode is disposed on a part of the second power line exposed through an auxiliary hole, contacts a part of the second power line, and includes or consists of the same layer as the pixel electrode.
Kim teaches a display device (a display device) (Fig. 1 and paragraph 53), wherein a fourth conductive layer (a layer containing a second power supply line PL2) comprises a second power line (the layer above passivation layer PSV contains the second power supply line PL2) (Fig. 6 and paragraphs 158-159), and an auxiliary electrode (the portion of the second electrode CD within the contact hole CH12 functions as an auxiliary electrode) is disposed on a part of a second power line exposed through an auxiliary hole (the portion of the second electrode CD within the contact hole CH12 which functions as an auxiliary electrode is formed on the second power supply line PL2) (Fig. 6 and paragraphs 158-159), contacts a part of the second power line, and includes or consists of the same layer as a pixel electrode (the portion second electrode CD electrically connected to the second power supply line PL2 through the twelfth contact hole CH12 is shown in the same layer of the first electrode AD as shown in Fig. 6) (Fig. 6 and paragraph 137).
It would have been obvious to one skilled in the art to combine the teachings of Cho in view of Choi and Lee with the teachings of Kim to have the fourth conductive layer comprises the second power line, and the auxiliary electrode is disposed on a part of the second power line exposed through an auxiliary hole, contacts a part of the second power line, and includes or consists of the same layer as the pixel electrode since it has been held that rearranging parts of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70.
In regard to claim 15, Cho in view of Choi and Lee teach wherein the fourth conductive layer comprises a second power line (a power line PL) (Lee Fig. 6 and paragraph 133).
Cho in view of Choi and Lee don’t explicitly teach the auxiliary electrode is disposed on the second planarization layer, includes or consists of the same layer as the pixel electrode, and is electrically connected to the second power line through a power connection hole penetrating the second planarization layer.
Kim teaches a display device (a display device) (Fig. 1 and paragraph 53), the auxiliary electrode is disposed on the second planarization layer (the portion of the second electrode CD through the twelfth contact hole CH12 is shown disposed on the passivation layer PSV) (Fig. 6 and paragraphs 171 and 175), includes or consists of the same layer as the pixel electrode (the portion of the second electrode CD through the twelfth contact hole CH12 is shown in the same layer as the first electrode AD) (Fig. 6 and paragraph 206), and is electrically connected to the second power line through a power connection hole penetrating the second planarization layer (the second electrode CD may be electrically connected to the second power supply line PL2 through the twelfth contact hole CH12) (Fig. 6 and paragraph 171).
It would be obvious to one skilled in the art to combine the teachings of Cho in view of Choi and Lee with the teachings of Kim to have the auxiliary electrode is disposed on the second planarization layer, includes or consists of the same layer as the pixel electrode, and electrically connected to the second power line through a power connection hole penetrating the second planarization layer since Cho in view of Lee contains all of the aforementioned components and it has been held that rearranging parts of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70.
In regard to claim 16, Cho in view of Choi, Lee and Kim teach wherein the substrate further comprises a non-display area around the display area (a peripheral area PA may be a non-display area, and may be adjacent to the display area DA) (Cho Fig. 1 and paragraph 56),
the second power line is disposed in the non-display area and is electrically connected to the common electrode (the second power supply voltage ELVSS may be applied to the power supply wire VL which is disposed in the peripheral area PA and extends to connect to the second electrode 183) (Cho Fig. 2 and paragraphs 55-56), and
the fourth conductive layer comprises the auxiliary electrode (the portion of the second electrode CD within the contact hole CH12 functions as an auxiliary electrode and is in the fourth conductive layer) (Kim Fig. 6)
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Cho in view of Choi and Lee as applied to claim 12 above, and further in view of Ogawa et al. (US 20220157229 A1; hereinafter “Ogawa”).
In regard to claim 14, Cho teaches, wherein the pixel driver comprises at least one transistor (a thin film transistor TFT) (Fig. 2 and paragraph 62),
one of the at least one transistor comprises a channel portion (a channel region is disposed between the drain region and the source region) (Fig. 2 and paragraph 64), a source portion connected to one side of the channel portion, a drain portion connected to the other side of the channel portion (a channel region is disposed between the drain region and the source region) (Fig. 2 and paragraph 64),
the semiconductor layer comprises the channel portion, the source portion and the drain portion (the semiconductor layer is formed of the active pattern and contains the channel region is disposed between the drain region and the source region) (Fig. 2 and paragraph 64), and
the second conductive layer comprises the second gate electrode (the second conductive layer is the layer containing the gate electrode GE) (Fig. 2 and paragraph 60).
However Cho in view of Choi and Lee doesn’t explicitly teach, a first gate electrode and a second gate electrode overlapping the channel portion,
the first conductive layer comprises the first gate electrode.
Ogawa teaches a display device (display device 1) (Fig. 7 and paragraph 77), comprising a first gate electrode and a second gate electrode overlapping a channel portion (the drive transistor DRT may have a bottom-gate structure in which the gate electrode 64 is provided under the semiconductor layer 61 or a dual-gate structure in which the gate electrodes 64 are provided both on and under the semiconductor layer 61) (Fig. 7 and paragraph 84),
the first conductive layer comprises the first gate electrode (the bottom gate oof the dual-gate structure would be the first conductive layer).
It would be obvious to one skilled in the art to combine the teachings of Cho in view of Choi and Lee with the teachings of Ogawa to have a first gate electrode and a second gate electrode overlapping the channel portion with the first conductive layer comprises the first gate electrode since using a dual gate structure is well known amongst those skilled in the art since they are known to provide better current control within channels and higher drive current.
Claim Objections
Claims 10-11 and 17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 10, the prior art of record, taken alone or in combination, fails to teach or suggest:
“second bonding portion has a third width at the first point of the first side, and has a fourth width smaller than the third width at the second point of the third side”
Cho is considered the closest prior art of record. However, Cho fails to teach a second bonding portion has a third width at the first point of the first side, and has a fourth width smaller than the third width at the second point of the third side. Cho teaches the aforementioned bonding portions only contain a total of three different widths.
Regarding claim 11, the prior art of record, taken alone or in combination, fails to teach or suggest:
“wherein the second bonding portion has a third width at the first point of the first side, and has a fourth width smaller than the third width at the second point of the third side”
Cho is considered the closest prior art of record. However, Cho fails to teach the second bonding portion has a third width at the first point of the first side, and has a fourth width smaller than the third width at the second point of the third side. Cho teaches the aforementioned bonding portions only contain a total of three different widths.
Regarding claim 17, the prior art of record, taken alone or in combination, fails to teach or suggest:
“the auxiliary electrode is disposed on the pixel defining layer”
Cho is considered the closest prior art of record. However, Cho fails to teach the auxiliary electrode is disposed on the pixel defining layer. Cho teaches the element that functions as the auxiliary electrode is separated from the pixel defining layer.
Allowable Subject Matter
Claims 2 and 18-21 are allowed.
As claim 2 has been rewritten in independent form including all of the limitations of the base claim and any intervening claims, The Examiners reasons for allowance is explained in the non-final office action mailed 09/24/2025.
The Examiners reasons for allowance of claims 18-21 are explained in the non-final office action mailed 09/24/2025.
Moreover, none of the prior arts of record, taken either alone or in combination, anticipate nor render obvious the claimed inventions. Hence, claims 2 and 18-21 are allowable over the prior arts of record
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SEYON ALI-SIMAH PUNCHBEDDELL whose telephone number is (571)270-0078. The examiner can normally be reached Mon-Thur: 7:30AM-3:30 PM.
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/SEYON ALI-SIMAH PUNCHBEDDELL/ Examiner, Art Unit 2893
/SUE A PURVIS/ Supervisory Patent Examiner, Art Unit 2893