DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election of Invention I in the reply filed on 12/29/2025 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Claims 12-17 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on December 29, 2025.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 – 11, and 18 – 26 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chou et al. (US 2007/0205520).
Regarding claim 1, Chou teaches (FIG. 7E):
A circuit board, comprising:
a first insulating layer (14);
a second insulating layer (39) positioned on the first insulating layer; and
a first pad portion (108) and a second pad portion (110) which are partially buried in the first insulating layer, protrude from the second insulating layer, and have different thicknesses (FIG. 7E),
wherein the first pad portion and the second pad portion each include a first layer (18) and a second layer (102/106) positioned on the first layer, and
heights of the first layer of the first pad portion and the first layer of the second pad portion are lower than a height of the first insulating layer (FIG. 7E).
Regarding claim 2, Chou teaches:
The circuit board of claim 1, wherein: a thickness of the second layer of the first pad portion is different from a thickness of the second layer of the second pad portion (FIG. 7E).
Regarding claim 3, Chou teaches:
The circuit board of claim 2, wherein: a thickness of the first layer of the first pad portion and a thickness of the first layer of the second pad portion are substantially the same (FIG. 7E).
Regarding claim 4, Chou teaches:
The circuit board of claim 3, wherein: the first pad portion and the second pad portion each further include a third layer (20) positioned on the second layer.
Regarding claim 5, Chou teaches:
The circuit board of claim 2, wherein: a thickness of the third layer of the first pad portion and a thickness of the third layer of the second pad portion are substantially the same (FIG. 7E).
Regarding claim 6, Chou teaches:
The circuit board of claim 5, wherein: the first layer, the second layer, and the third layer include different metals ([0048] – [0050], [0168] – [0171]).
Regarding claim 7, Chou teaches:
The circuit board of claim 6, wherein: the first layer includes copper ([0048]), the second layer includes nickel ([0170] – [0176]), and the third layer includes gold ([0049]).
Regarding claim 8, Chou teaches:
The circuit board of claim 1, wherein: the second insulating layer is located on a side surface of the second layer of the first pad portion and the second layer of the second pad portion, and a thickness of the second insulating layer positioned on the side surface of the second layer of the first pad portion and a thickness of the second insulating layer positioned on the side surface of the second layer of the second pad portion are substantially the same (FIG. 7E).
Regarding claim 9, Chou teaches:
The circuit board of claim 8, wherein: the second insulating layer includes a solder resist layer ([0074] – [0075]).
Regarding claim 10, Chou teaches:
The circuit board of claim 1, further comprising: a third insulating layer (12) positioned under the first insulating layer; and a third pad portion (8) buried in the third insulating layer.
Regarding claim 11, Chou teaches:
The circuit board of claim 10, further comprising: a via (10) layer located in the first insulating layer, wherein the first pad portion and the third pad portion are connected to each other through the via layer (FIG. 7E).
Regarding claim 18, Chou teaches:
A circuit board, comprising:
a first insulating layer (14);
a second insulating layer (39) positioned on the first insulating layer; and
a first pad portion (108) and a second pad portion (110) which are partially buried in the first insulating layer and protrude from an upper surface of the second insulating layer to have different heights with respect to the upper surface of the second insulating layer (FIG. 7E), wherein the first pad portion and the second pad portion each include a first layer (18) and a second layer (102/106) disposed on the first layer, and
the first layer of the first pad portion and the first layer of the second pad portion include a first metal ([0048] – [0050]), and the second layer of the first pad portion and the second layer of the second pad portion have different thicknesses and include a second metal different from the first metal (FIG. 7E, [0168] – [0171]).
Regarding claim 19, Chou teaches:
The circuit board of claim 18, wherein: a thickness of the first layer of the first pad portion and a thickness of the first layer of the second pad portion are substantially the same (FIG. 7E).
Regarding claim 20, Chou teaches:
The circuit board of claim 18, wherein: the first pad portion and the second pad portion each further include a third layer ([0171]) disposed on the second layer, the third layer of the first pad portion and the third layer of the second pad portion include a third metal different from the first metal and the second metal ([0049]), the first layer, the second layer, and the third layer of the first pad portion are sequentially disposed, and the first layer, the second layer, and the third layer of the second pad portion are sequentially disposed ([0171]).
Regarding claim 21, Chou teaches:
The circuit board of claim 20, wherein: the first metal is copper, the second metal is nickel, and the third metal is gold [0168] – [0171].
Regarding claim 22, Chou teaches:
The circuit board of claim 18, further comprising: a via layer (16) disposed in the first insulating layer to connect to one of the first pad portion or the second pad portion.
Regarding claim 23, Chou teaches:
The circuit board of claim 18, wherein: the first layer of the first pad portion and the first layer of the second pad portion are disposed on a same level with respect to the upper surface of the second insulating layer (FIG. 7E).
Regarding claim 24, Chou teaches:
The circuit board of claim 18, wherein: the second layer of the first pad portion and the second layer of the second pad each penetrate through the upper surface of the second insulating layer and a lower surface of the second insulating layer (FIG. 7E).
Regarding claim 25, Chou teaches:
The circuit board of claim 18, wherein: a width of the first pad portion and a width of the second pad portion are substantially the same (FIG. 7E).
Regarding claim 26, Chou teaches ([0029] – [0032]):
The circuit board of claim 18, further comprising: a semiconductor device disposed on the second insulating layer; and first and second wiring parts connecting the first and second pad portions to the semiconductor device.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CORY W ESKRIDGE whose telephone number is (571)272-0543. The examiner can normally be reached M - F 9 - 5.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jerry O'Connor can be reached at (571) 272-6787. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CORY W ESKRIDGE/Primary Examiner, Art Unit 3624