Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I: claims 1-5 in the reply filed on 9/16/2026 is acknowledged.
Prior Art of Record
The applicant's attention is directed to additional pertinent prior art cited in the accompanying PTO-892 Notice of References Cited, which, however, may not be currently applied as a basis for the following rejections. While these references were considered during the examination of this application and are deemed relevant to the claimed subject matter, they are not presently being applied as a basis for rejection in this Office action. The pertinence of these documents, however, may be revisited, and they may be applied in subsequent Office actions, particularly in light of any amendments or further clarification of the claimed invention.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-4 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Huang et al. (US 20220359375 A1).
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CLAIM 1. Huang teaches the integrated circuit structure, comprising:
a front side structure 120-136 comprising:
a device layer 107; and
a plurality of metallization layers 136 and/or 120/122/124 above the device layer (“above” “below” are relative. Huang teaches metallization layers above both sides for the device layer.);
a backside structure layers 136 and/or 120/122/124 below the device layer(“above” “below” are relative. Huang teaches metallization layers above both sides for the device layer.); and
a carrier wafer 150 or substrate bonded directly to and in contact with the front side structure (Huang fig. 29C).
CLAIM 2. Huang teaches the integrated circuit structure of claim 1, wherein the carrier wafer or substrate is a wafer or substrate selected from the group consisting of an amorphous silicon carrier wafer or substrate, a glass carrier wafer or substrate (such as silica glass), a Si(110) carrier wafer or substrate, and a Si(111) carrier wafer or substrate (Huang fig. 29C & ¶74).
CLAIM 3. Huang teaches the integrated circuit structure of claim 1, wherein the device layer comprises a plurality of nanowire-based transistors (Huang fig. 29C & ¶12).
CLAIM 4. Huang teaches the integrated circuit structure of claim 1, wherein the device layer comprises a plurality of fin-based transistors (Huang fig. 29C & ¶12). .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Huang et al. (US 20220359375 A1) in view of Yuh et al. (US 20230067715 A1).
CLAIM 5. Huang teaches the integrated circuit structure of claim 1, however may be silent upon wherein the backside structure includes a plurality of dynamic random access memory (DRAM) devices.
Yuh et al. teaches integrated circuit devices featuring memory structures integrated directly into a backside structure (Yuh Fig. 45, abstract). Specifically, Yuh discloses that a memory stack (MS') forming dynamic random access memory (DRAM) storage cells can be disposed within a backside structure to optimize proximity to logic components (Yuh, ¶161, disclosing that a "backside trench or MIM capacitance can be used for embedded DRAM with very close proximity to logic area").
It would have been obvious to a person having ordinary skill in the art (PHOSITA) at the time the invention was made to modify the integrated circuit structure of Huang et al. by incorporating the backside DRAM storage cells as taught by Yuh into the backside structure of Huang. A PHOSITA would have been motivated to make this modification to provide local, high-speed embedded memory capacity directly adjacent to the active device layer without consuming valuable front-side layout area, thereby maximizing functional density, reducing interconnect parasitics, and improving overall device performance.
Furthermore, it would have been obvious to a PHOSITA at the time of the invention to modify the integrated circuit structure of Huang with the backside DRAM storage cells of Yuh. Applying a known technique (backside memory integration) to a known device ready for improvement (Huang’s integrated circuit structure) to yield predictable results (increased functional density and reduced latency) is a standard practice that falls squarely within the scope of ordinary skill (KSR International Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JARRETT J STARK whose telephone number is (571)272-6005. The examiner can normally be reached 8-4 M-F.
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JARRETT J. STARK
Primary Examiner
Art Unit 2822
10/1/2026
/JARRETT J STARK/Primary Examiner, Art Unit 2898
