DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
The status of the claims is as follows: Claims 1-20 are pending. An action on the merits for claims 1-20 follows.
IDS
All references provided in the IDS have been considered.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-5, 11-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lin et al. (US20220139823A1), hereinafter Lin.
Regarding Claim 1, Lin teaches an integrated circuit structure ("IC interconnect structure," (301); Figs. 3A-3D (cross-sections of manufacturing steps); Paragraph [0010]), comprising:
a conductive via ("interconnect via," (310A); Paragraph [0081]) in a first dielectric layer (first part of "dielectric material," (320) comprising "a stack of dielectric material layers;" Paragraph [0089]); and
a conductive line ("interconnect feature," (316); Paragraph [0081]) in a second dielectric layer (second part of "dielectric material," (320) comprising "a stack of dielectric material layers;" Paragraph [0089]), the conductive line (316) comprising a conductive liner ("adhesion layer;" Paragraph [0082]) having a conductive barrier ("liner of barrier material;" Paragraph [0082]) therein, the conductive barrier ("liner of barrier material) having a conductive fill ("fill metal;" Paragraph [0082]) therein, wherein the conductive liner ("adhesion layer" for "adhesion to an underlying material;" Paragraph [0082]) is directly on the conductive via (310A).
Regarding Claim 2, Lin teaches the integrated circuit structure of claim 1, wherein the conductive via (310A) comprises a metal selected from the group consisting of W, Mo, and Ru ("include a fill metal of […] W;" Paragraph [0073]).
Regarding Claim 3, Lin teaches the integrated circuit structure of claim 1, wherein the conductive liner ("adhesion layer") comprises a metal selected from the group consisting of Ta and Ti ("adhesion materials may also vary, with Ti;" Paragraph [0082]).
Regarding Claim 4, Lin teaches the integrated circuit structure of claim 1, wherein the conductive barrier ("liner of barrier material") comprises tantalum and nitrogen ("comprising a metallic compound, such as, but not limited to, TaN;" Paragraph [0082]).
Regarding Claim 5, Lin teaches the integrated circuit structure of claim 1, wherein the conductive fill ("fill metal") comprises copper ("fill metal of predominately Cu;" Paragraph [0082]).
Regarding Claim 11, Lin teaches a computing device ("computing device," (3400) "inside [mobile computing] platform 3305;" Figs. 33 (mobile computing platform), 34 (computing device), Paragraph [0241] with 3305 "employing an IC […], for example as described elsewhere herein" as is seen below in reference to Figs. 3A-3D; Paragraph [0238] ), comprising:
a board ("motherboard," (3402); Fig. 34, Paragraph [0241]); and
a component coupled to the board (3402), the component including an integrated circuit structure ("IC interconnect structure," (301); Figs. 3A-3D (cross-sections of manufacturing steps); Paragraph [0010]), comprising:
a conductive via ("interconnect via," (310A); Paragraph [0081]) in a first dielectric layer (first part of "dielectric material," (320) comprising "a stack of dielectric material layers;" Paragraph [0089]); and
a conductive line ("interconnect feature," (316); Paragraph [0081]) in a second dielectric layer (second part of "dielectric material," (320) comprising "a stack of dielectric material layers;" Paragraph [0089]), the conductive line (316) comprising a conductive liner ("adhesion layer;" Paragraph [0082]) having a conductive barrier ("liner of barrier material;" Paragraph [0082]) therein, the conductive barrier ("liner of barrier material) having a conductive fill ("fill metal;" Paragraph [0082]) therein, wherein the conductive liner ("adhesion layer" for "adhesion to an underlying material;" Paragraph [0082]) is directly on the conductive via (310A).
Regarding Claim 12, Lin teaches the computing device of claim 11, further comprising: a memory ("DRAM," (3432); Fig. 34, Paragraph [0242]) coupled to the board (3402).
Regarding Claim 13, Lin teaches the computing device of claim 11, further comprising: a communication chip ("communication chips," (3406); Fig. 34, Paragraph [0243]) coupled to the board (3402).
Regarding Claim 14, Lin teaches the computing device of claim 11, further comprising: a camera ("camera," (3441); Fig. 34, Paragraph [0242]) coupled to the board (3402).
Regarding Claim 15, Lin teaches the computing device of claim 11, further comprising: a battery ("battery," (3406); Fig. 34, Paragraph [0242]) coupled to the board (3402).
Regarding Claim 16, Lin teaches the computing device of claim 11, further comprising: a speaker ("speaker," (3420); Fig. 34, Paragraph [0242]) coupled to the board (3402).
Regarding Claim 17, Lin teaches the computing device of claim 11, further comprising: a compass ("compass," (3445); Fig. 34, Paragraph [0242]) coupled to the board (3402).
Regarding Claim 18, Lin teaches the computing device of claim 11, further comprising: a GPS ("global positioning system (GPS) device," (3440); Fig. 34, Paragraph [0242]) coupled to the board (3402).
Regarding Claim 19, Lin teaches the computing device of claim 11, further comprising: a display ("touchscreen display," (3415); Fig. 34, Paragraph [0242]) coupled to the board (3402).
Regarding Claim 20, Lin teaches the computing device of claim 11, wherein the component is a packaged integrated circuit die ("package level integrated system," (3310); Fig. 33, Paragraph [0239]).
Claims 6-10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Amanapu et al. (US20190198444A1), hereinafter Amanapu.
Regarding Claim 6, Amanapu teaches an integrated circuit structure ("metallic interconnect structure;" Figs. 1-11A (cross-sectional side views of method for fabricating metallic interconnect structure), 11B (top-down view), Paragraph [0006]), comprising:
a plurality of conductive lines (140, 160) on a same level and along a same direction (y-direction of Fig. 11A), a first one of the plurality of conductive lines ("metallic material," (140); Paragraph [0038]) having a first width ("first width," (W1); Fig. 2, Paragraph [0034]) and a first composition ("may comprise Ru, Co;" Fig. 11A, Paragraph [0038]), and a second one of the plurality of conductive lines ("second layer metallic material," (160); Paragraph [0045]) having a second width ("second width," (W2); Paragraph [0034]) and a second composition ("comprises copper;" Paragraph [0046]), the second width (W2) greater than the first width (W1), and the second composition different than the first composition, the second one of the plurality of conductive lines (160) having a conductive liner ("conformal liner layer," (130); Paragraph [0037]) having a conductive barrier ("second conformal liner layer;" (150) Paragraph [0043]) therein, the conductive barrier () having a conductive fill ("metallic line," (160-1); Fig. 11A, Paragraph [0045]) therein; and
an inter-layer dielectric (ILD) structure ("insulating layer," (125); Paragraph [0031]) having portions between adjacent ones of the plurality of conductive lines (140, 160).
Regarding Claim 7, Amanapu teaches the integrated circuit structure of claim 6, wherein the second one of the plurality of conductive lines (160) is on a conductive via ("conductive via contacts;" Paragraph [0030]) comprising a metal selected from the group consisting of W, Mo, and Ru ("openings are filled with a conductive material, such as tungsten, to form conductive via contacts […] provide electrical connections;" Paragraph [0030]).
Regarding Claim 8, Amanapu teaches the integrated circuit structure of claim 6, wherein the conductive liner (130) comprises a metal selected from the group consisting of Ta and Ti ("formed of […] tantalum;" Paragraph [0037]).
Regarding Claim 9, Amanapu teaches the integrated circuit structure of claim 6, wherein the conductive barrier (150) comprises tantalum and nitrogen ("formed of […] TaN;" Paragraph [0043]).
Regarding Claim 10, Amanapu teaches the integrated circuit structure of claim 6, wherein the conductive fill (160-1) comprises copper ("comprises copper;" Paragraph [0046]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Nolan Stuessy whose telephone number is (571) 645-5843. The examiner can normally be reached on M-F; 9:00-5:00 (EST).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached at (571) 272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/NOLAN GABRIEL STUESSY/ Examiner, Art Unit 2812
/DAVIENNE N MONBLEAU/Supervisory Patent Examiner, Art Unit 2812
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