Prosecution Insights
Last updated: July 17, 2026
Application No. 18/217,008

THREE DIMENSIONAL MECHANICALLY BOLTING STAPLE FILL

Non-Final OA §103
Filed
Jun 30, 2023
Examiner
MELLINGER, CORBYN DAVID
Art Unit
2899
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
International Business Machines Corporation
OA Round
1 (Non-Final)
73%
Grant Probability
Favorable
1-2
OA Rounds
2m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 73% — above average
73%
Career Allowance Rate
22 granted / 30 resolved
+5.3% vs TC avg
Strong +44% interview lift
Without
With
+44.4%
Interview Lift
resolved cases with interview
Typical timeline
3y 2m
Avg Prosecution
13 currently pending
Career history
58
Total Applications
across all art units

Statute-Specific Performance

§103
80.9%
+40.9% vs TC avg
§102
9.6%
-30.4% vs TC avg
§112
8.8%
-31.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 30 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of claims 1-11 in the reply filed on 10 November 2025 is acknowledged. Applicant's election with traverse of claims 12-16 in the reply filed on 10 November 2025 is acknowledged. The traversal is on the ground(s) that it is moot in light of the primary election of claims 1-11. Because the traversal is based on the non-elected claims, the election is acknowledged but moot. However, in the case of applicant’s elected claims being found to be in condition of allowance, such an election is necessary in order to examine claims which may be eligible for rejoinder. The requirement is still deemed proper and is therefore made FINAL. Drawings Color photographs and color drawings are not accepted in utility applications unless a petition filed under 37 CFR 1.84(a)(2) is granted. Any such petition must be accompanied by the appropriate fee set forth in 37 CFR 1.17(h), one set of color drawings or color photographs, as appropriate, if submitted via the USPTO patent electronic filing system or three sets of color drawings or color photographs, as appropriate, if not submitted via the via USPTO patent electronic filing system, and, unless already present, an amendment to include the following language as the first paragraph of the brief description of the drawings section of the specification: The patent or application file contains at least one drawing executed in color. Copies of this patent or patent application publication with color drawing(s) will be provided by the Office upon request and payment of the necessary fee. Color photographs will be accepted if the conditions for accepting color drawings and black and white photographs have been satisfied. See 37 CFR 1.84(b)(2). Additionally, many of the black and white version of the submitted color drawings have illegible labels or are impossible to distinguish between different labeled features in the drawings. See, as non-complete examples, Figures 25A and Figure 11, respectively. Appropriate correction is required. Specification The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification. The specification contains a number of informalities, including but not limited to: Several paragraph number labels appear to be crossed out, for example para [0068] on specification page 13. The paragraph numbering appears to restart near the end of the document, see specification page 20. Appropriate correction is required. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1-5 and 8-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20120074579 (Su et al) and US 20200098849 (Naser et al). As to Claim 1: Su teaches a structure comprising: a semiconductor substrate (50); a plurality of first dielectric layers at a top side of the semiconductor substrate (60 may contain interlevel dielectric layers ¶0039); an active device layer at a top side of the plurality of first dielectric layers (70 ¶0039); a plurality of second dielectric layers at a top side of the active device layer (75+85, which may contain interlevel dielectric layers ¶0039); and at least hundreds of metal bodies, (labeled 100a, 100b, etc., which may explicitly number in the hundreds ¶0040) and comprises: a first metal plate, at a first level in the plurality of first dielectric layers that is adjacent to the active device layer (one of the metal layers in 60); a second metal plate, at a second level in the plurality of second dielectric layers that is adjacent to the active device layer (one of the metal layers in 75+85); and a first plurality of vias that connect the first metal plate to the second metal plate through the active device layer (e.g., 100a-e in Fig 2). Su fails to explicitly teach wherein each of which is on the order of about 10 nm to about 1000 nm in critical dimension. Naser teaches a structure similar to that of Su, and explicitly teaches similar features having length of 20-25 nm (Naser, TSVs ¶0020). This disclosed size is broadly interpreted as a “critical dimension” of the structure. It would have been obvious to one of ordinary skill in the art at the time of filing, in light of the discloser of Naser, that the metal bodies taught by Su be on the order of about 10 nm to about 1000 nm in critical dimension. As to Claim 2: Su and Naser teach the structure of claim 1. Su further teaches wherein each of the at least hundreds of metal bodies further comprises: a third metal plate at a third level in the plurality of first dielectric layers (another of the metal layers in 60); a fourth metal plate at a fourth level in the plurality of second dielectric layers (another of the metal layers in 75); a second plurality of vias that connect the second metal plate to the fourth metal plate (e.g., 100f-g); and a third plurality of vias that connect the third metal plate to the first metal plate (e.g., 100h-i). As to Claim 3: Su and Naser teach the structure of claim 2. Su further teaches wherein at least a portion of the metal bodies bridge through an active device region of the active device layer (100a-e through middle parts of 70 as seen in Fig 2). As to Claim 4: Su and Naser teach the structure of claim 2. Su further teaches wherein at least a portion of the metal bodies are located in white space of the structure, away from an active device region of the active device layer (100f-i not through middle parts of 70 as seen in Fig 2). As to Claim 5: Su and Naser teach the structure of claim 2. Su further teaches wherein at least a portion of the metal bodies are located in an interior portion of the structure, away from a perimeter thereof (100a-e away from edge of 15). As to Claim 8: Su and Naser teach the structure of claim 2. Su further teaches a crackstop at a perimeter of the structure (100f and 100i function as crackstops at perimeter of 15, Fig 3 ¶0043). As to Claim 9: Su and Naser teach the structure of claim 8. Su further teaches a guard ring laterally inward of the crackstop (100g and 100h may be connected externally, i.e., function as a guard ring laterally inward of 100f and 100i Fig 7 ¶0047). Claim(s) 6-7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Su and Naser as applied to claim 1 above, and further in view of US 20220310841 (Ju et al). As to Claim 6: Su and Naser teach the structure of claim 2. Su teaches wherein the active device layer includes a plurality of transistors (¶0039). However, it fails to explicitly teach those transistors being nanosheet field effect transistors. Ju explicitly teaches the substitutability of general transistors with other devices, specifically with nanosheet FETs (Ju ¶0012). The claim would have been obvious because the substitution of one known element for another would have yielded predictable results to one of ordinary skill in the art. As to Claim 7: Su, Naser, and Ju teach the structure of claim 6. Su further teaches: a plurality of first wires within the first dielectric layers (45 within layers of 60); a plurality of second wires within the second dielectric layers (90 within layers of 75+85); and a plurality of contacts and a plurality of buried power rails interconnected between at least some of the nanosheet field effect transistors and some of the first and second pluralities of wires (80 connected by contacts above 100a-e between devices in 70 and second wires 90). Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Su and Naser as applied to claim 1 above, and further in view of US 20230168300 (Giacomini et al). As to Claim 10: Su and Naser teach the structure of claim 1. Su teaches 100f may function as a crack sensor (¶0048). However, this is not considered to be laterally inward of the guard ring. Giacomini teaches a device similar to that of Su and Naser, wherein a crack sensor may be placed at an arbitrary location within a device package. All of the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination would have yielded predictable results to one of ordinary skill in the art at the time of applicant’s filing. Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Su, Naser, and Giacomini as applied to claim 10 above, and further in view of US 20170027058 (Perkins et al). As to Claim 11: Su, Naser, and Giacomini teach the structure of claim 10. However, it does not explicitly teach a moisture sensor laterally inward of the crack sensor. Perkins teaches a device similar to that of Su, Naser, and Giacomini, wherein a moisture sensor may be placed at an arbitrary location within a device package. All of the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination would have yielded predictable results to one of ordinary skill in the art at the time of applicant’s filing. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to Corbyn D Mellinger whose telephone number is (703)756-5683. The examiner can normally be reached M-F 9-6 Eastern. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Zandra Smith can be reached at 571-272-2429. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Corbyn D Mellinger/Examiner, Art Unit 2899 /ZANDRA V SMITH/Supervisory Patent Examiner, Art Unit 2899
Read full office action

Prosecution Timeline

Jun 30, 2023
Application Filed
Jun 10, 2026
Non-Final Rejection mailed — §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12672560
SEMICONDUCTOR DEVICE INCLUDING SEMICONDUCTOR ELEMENTS, INSULATING BASE MEMBERS, WIRINGS, AND AT LEAST ONE WIRING MEMBER
3y 7m to grant Granted Jun 30, 2026
Patent 12648153
SEMICONDUCTOR DEVICE PACKAGES AND METHODS OF FORMATION
3y 4m to grant Granted Jun 02, 2026
Patent 12616060
STACKED RANDOM-ACCESS MEMORY DEVICES WITH REFRIGERATION
4y 2m to grant Granted Apr 28, 2026
Patent 12604760
SEMICONDUCTOR MODULE AND METHOD FOR MANUFACTURING SEMICONDUCTOR MODULE
3y 5m to grant Granted Apr 14, 2026
Patent 12588490
SEMICONDUCTOR STRUCTURE COMPRISING POWER DELIVER NETWORK STRUCTURE
2y 10m to grant Granted Mar 24, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

1-2
Expected OA Rounds
73%
Grant Probability
99%
With Interview (+44.4%)
3y 2m (~2m remaining)
Median Time to Grant
Low
PTA Risk
Based on 30 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month