DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claims 1-20 are pending.
Priority
Acknowledgment is made of Applicant's claim for foreign priority based on an application filed in Korea on 18 October 2022. It is noted, however, that applicant has not filed a certified copy of the 10-2022-0135280 application as required by 37 CFR 1.55.
Claim Objections
Claims 5, 13, and 19 are objected to because of the following informalities: the term "date" should read "data”. Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-8, and 10-20 are rejected under 35 U.S.C. 103 as being unpatentable over He (US 2022/0320196) in view of Park (US 2015/0262526) and Nishiyama (US 2022/0367597). All reference is to He unless otherwise indicated.
Regarding Claim 1 (Original), He teaches a display device comprising:
a substrate [fig. 1 @1] including an active area [fig. 1 @S1] and a dummy area [fig. 1 @S2, ¶0082, “The dummy pixel circuits 3 are disposed on the substrate 1 and in the peripheral area S2”], and
including a plurality of sub-pixels [fig. 1 @2 and 3] arranged in m rows and n columns [¶0084, “ … A plurality of pixel circuits 2 are repeatedly arranged on the substrate 1 and in the display area S1 along the first direction (i.e., X direction) and the second direction (i.e., Y direction), and each pixel circuit is configured to drive a light-emitting device of a sub-pixel in the pixel unit”];
first initialization power lines [fig. 4E @init] which provide a first initialization voltage [fig. 2B @Vinit1] to sub-pixels of the plurality of sub-pixels and extending in a first direction [horizontal];
second initialization power lines [fig. 4E @init’ (not shown)] which provide a second initialization voltage [fig. 2B @Vinit2] to sub-pixels of the plurality of sub-pixels and extending in the first direction [¶0095, “the second electrode of the second reset transistor T1 and the second electrode of the first reset transistor T7 are connected to the second reset power terminal Vinit2 and the first reset power terminal Vinit1, respectively, the first reset power terminal Vinit1 and the second reset power terminal Vinit2 may be DC reference voltage terminals for outputting a constant DC reference voltage. The first reset power terminal Vinit1 and the second reset power terminal Vinit2 may be the same”]; and
sub-pixels [fig. 1 @3] of the dummy area [fig. 1 @S2] among the plurality of sub-pixels [fig. 1 @2 and 3] are arranged in an outermost column [fig. 1 illustrates claimed structure] of the n columns and
m and n are natural numbers [fig. 1 illustrates a discrete number of rows and columns]
He does not teach the initialization power lines extending in the column direction; repair lines extending in a row direction, wherein the repair lines connect the sub-pixels of the dummy area and sub-pixels of the active area among the plurality of sub-pixels, respectively
Park teaches repair lines [fig. 1 @RLm] extending in a row direction, wherein
the repair lines [fig. 2 @RLm] connect the sub-pixels of the dummy area [fig. 2 @DP] and sub-pixels [fig. 3 @P] of the active area [fig. 2 @AA] among the plurality of sub-pixels, respectively
Before the application was filed it would have been obvious to one of ordinary skill in the art to incorporate the concept of repair lines connecting dummy and real pixels, as taught by Park into the display taught by He in order to repair defective pixels
He in view of Park does not teach the initialization power lines extending in the column direction
Nishiyama teaches initialization power lines [fig. 9 @INI] extend in a column direction [¶0035, “… Although extending vertically, the initialization line INI may extend horizontally”]
Before the application was filed it would have been obvious to one of ordinary skill in the art to incorporate the concept of routing initialization power lines in a column direction, as taught by Nishiyama, into the display panel taught by He in view of Park in order to provide initialization signals to each pixel circuit.
Regarding Claim 10 (Original), He teaches a display device comprising:
a substrate [fig. 1 @1] including a plurality of sub-pixels [fig. 1 @2 and 3] arranged in m rows and n columns and including active pixels [fig. 1 @2] and dummy pixels [fig. 1 @3];
first initialization power lines [fig. 4E @init] which provide a first initialization voltage [fig. 2B @Vinit1] to sub-pixels of the plurality of sub-pixels and extending in a first direction [horizontal];
second initialization power lines [fig. 4E @init’ (not shown)] which provide a second initialization voltage [fig. 2B @Vinit2] to sub-pixels of the plurality of sub-pixels and extending in the first direction [¶0095, “the second electrode of the second reset transistor T1 and the second electrode of the first reset transistor T7 are connected to the second reset power terminal Vinit2 and the first reset power terminal Vinit1, respectively, the first reset power terminal Vinit1 and the second reset power terminal Vinit2 may be DC reference voltage terminals for outputting a constant DC reference voltage. The first reset power terminal Vinit1 and the second reset power terminal Vinit2 may be the same”], and
the dummy pixels [fig. 1 @3] are disposed in a n column [construed as the rightmost column in fig. 1] in odd rows [fig. 1 illustrates a dummy pixel in the odd rows of the rightmost column] among the plurality of sub-pixels, and
are disposed in a first column in even rows [fig. 1 illustrates a dummy pixel 3 in the even rows of the leftmost column] among the plurality of sub-pixels, and
m and n are natural numbers [fig. 1 illustrates a discrete number of rows and columns]
He does not teach the initialization power lines extending in the column direction; repair lines extending in a row direction, wherein the repair lines connect the dummy pixels and the active pixels among, respectively
Park teaches repair lines [fig. 1 @RLm] extending in a row direction, wherein
the repair lines [fig. 2 @RLm] connect the dummy pixels [fig. 2 @DP] and the active pixels [fig. 3 @P] among the plurality of sub-pixels, respectively
Before the application was filed it would have been obvious to one of ordinary skill in the art to incorporate the concept of repair lines connecting dummy and real pixels, as taught by Park into the display taught by He in order to repair defective pixels
He in view of Park does not teach the initialization power lines extending in the column direction
Nishiyama teaches initialization power lines [fig. 9 @INI] extend in a column direction [¶0035, “… Although extending vertically, the initialization line INI may extend horizontally”]
Before the application was filed it would have been obvious to one of ordinary skill in the art to incorporate the concept of routing initialization power lines in a column direction, as taught by Nishiyama, into the display panel taught by He in view of Park in order to provide initialization signals to each pixel circuit.
Regarding Claim 16 (Original), He teaches a display device comprising:
a substrate [fig. 1 @1] including a plurality of sub-pixels [fig. 1 @2 and 3] arranged in m rows and n columns and including active pixels [fig. 1 @2] and dummy pixels [fig. 1 @3];
first initialization power lines [fig. 4E @init] which provide a first initialization voltage [fig. 2B @Vinit1] to sub-pixels of the plurality of sub-pixels and extending in a first direction [horizontal];
second initialization power lines [fig. 4E @init’ (not shown)] which provide a second initialization voltage [fig. 2B @Vinit2] to sub-pixels of the plurality of sub-pixels and extending in the first direction [¶0095, “the second electrode of the second reset transistor T1 and the second electrode of the first reset transistor T7 are connected to the second reset power terminal Vinit2 and the first reset power terminal Vinit1, respectively, the first reset power terminal Vinit1 and the second reset power terminal Vinit2 may be DC reference voltage terminals for outputting a constant DC reference voltage. The first reset power terminal Vinit1 and the second reset power terminal Vinit2 may be the same”], and
the dummy pixels [fig. 1 @3] are disposed in a first column in odd rows [fig. 1 illustrates a dummy pixel in the odd rows of the leftmost column] among the plurality of sub-pixels, and
are disposed in a n column in even rows [fig. 1 illustrates a dummy pixel in the even rows of the rightmost column] among the plurality of sub-pixels, and
m and n are natural numbers [fig. 1 illustrates a discrete number of rows and columns]
He does not teach the initialization power lines extending in the column direction; repair lines extending in a row direction, wherein the repair lines connect the dummy pixels and the active pixels, respectively
Park teaches repair lines [fig. 1 @RLm] extending in a row direction, wherein
the repair lines [fig. 2 @RLm] connect the dummy pixels [fig. 2 @DP] and the active pixels [fig. 3 @P], respectively
Before the application was filed it would have been obvious to one of ordinary skill in the art to incorporate the concept of repair lines connecting dummy and real pixels, as taught by Park into the display taught by He in order to repair defective pixels
He in view of Park does not teach the initialization power lines extending in the column direction
Nishiyama teaches initialization power lines [fig. 9 @INI] extend in a column direction [¶0035, “… Although extending vertically, the initialization line INI may extend horizontally”]
Before the application was filed it would have been obvious to one of ordinary skill in the art to incorporate the concept of routing initialization power lines in a column direction, as taught by Nishiyama, into the display panel taught by He in view of Park in order to provide initialization signals to each pixel circuit.
Regarding Claim 2 (Original), He in view of Park and Nishiyama teach the display device of Claim 1, wherein
the sub-pixels of the dummy area [fig. 1 @S2] are arranged in n column [fig. 1 illustrates pixels in 2 are in columns].
Regarding Claims 3, 11, and 17 (Original), He in view of Park and Nishiyama teaches the display devices of Claims 1, 10, and 16, wherein
the first [Init1] initialization power lines [¶0105, “ … first reset power signal line Init1 of the first reset power terminal Vinit1 and the second reset power signal line Init2 of the second reset power terminal Vinit2 …”] and the second [Init2] initialization power lines are alternately disposed [fig. 2B illustrates T1 connected to Vinit2 and T7 connected to Vinit1, ¶0105 teaches Init1 connected to Vinit1 and Init2 connected to Vinit2, fig. 2C illustrates lines connected to T1 and T7 are disposed alternately].
Regarding Claims 4, 12, and 18 (Original), He in view of Park and Nishiyama teaches the display device of Claims 3, 11, and 17, wherein
the first initialization power lines [fig. 4E @init] are disposed in sub-pixels of even columns among the plurality of sub-pixels [Nishiyama: fig. 9 @INI illustrates initialization lines disposed in the even columns].
Regarding Claims 5, 13, and 19 (Original), He in view of Park and Nishiyama teaches the display device of Claims 1, 10, and 16, further comprising
data lines [fig. 4F @DATA] extending in the column direction and providing a data signal to the plurality of sub-pixels [fig. 2B illustrates Data connected to typical sub-pixel].
Regarding Claims 6 and 14 (Original), He in view of Park and Nishiyama teaches the display device of Claims 1 and 10, wherein
the plurality of sub-pixels of the active area [fig. 1 @2] includes a transistor [fig. 2B @T3] and a light-emitting element [fig. 2B @OLED] connected to the transistor [¶0086, “As shown in FIGS. 2B and 2C, FIG. 2B is a schematic circuit diagram of a pixel circuit 2”].
Regarding Claim 7 (Original), He in view of Park and Nishiyama teaches the display device of Claim 6, wherein the transistor [fig. 2B @T3] comprises:
an active pattern [fig. 5 @20] disposed on a substrate [fig. 5 @1];
a source electrode and a drain electrode respectively connected to the active pattern [fig. 2B @T3 illustrates source and drain electrodes]; and
a gate electrode [fig. 5 @30] overlapping the active pattern [fig. 5 @20] with a gate insulating layer [fig. 5 @21] interposed between the gate electrode and the active pattern.
Regarding Claims 8 and 15 (Original), He in view of Park and Nishiyama teaches the display device of Claims 1 and 15, further comprising
a first gate line [¶0094, “the second reset control signal may be the same as the scan signal, that is, the control electrode of the first reset transistor T7 may be electrically connected to the scan signal line Scan to receive the scan signal as the second reset control signal”] extending in the row direction and
providing a first initialization control signal to the sub-pixels [fig. 2B @Rst2].
Regarding Claim 20 (Original), He in view of Park and Nishiyama teaches the display device of Claim 10, wherein
Each of the active pixels [fig. 1 @2] includes a transistor [fig. 2B @T3] and a light-emitting element [fig. 2B @OLED] connected to the transistor [¶0086, “As shown in FIGS. 2B and 2C, FIG. 2B is a schematic circuit diagram of a pixel circuit 2”],
and the transistor comprises:
an active pattern [fig. 5 @20] disposed on a substrate [fig. 5 @1];
a source electrode and a drain electrode respectively connected to the active pattern [fig. 2B @T3 illustrates source and drain electrodes]; and
a gate electrode [fig. 5 @30] overlapping the active pattern [fig. 5 @20] with a gate insulating layer [fig. 5 @21] interposed between the gate electrode and the active pattern.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over He in view of Park, Nishiyama and Kim (US 2020/0410935). All reference is to He unless otherwise indicated.
Regarding Claim 9 (Original), He in view of Park and Nishiyama teaches the display device of Claim 8, further comprising
a second gate line extending in the row direction and providing a second initialization control signal to the sub-pixels [¶0006, “ the second gate control lines include at least some of a plurality of second scan lines, a plurality of second initialization control lines, and a plurality of second emission control lines, which control driving of the second pixels”]
Before the application was filed it would have been obvious to one of ordinary skill in the art to incorporate the concept of routing initialization power control signals over gate control lines, as taught by Kim, into the display panel taught by He in view of Park and Nishiyama in order to generate initialization control signals in the scan driver circuit and route several control signals from the driver on the same conductive layer.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Douglas Wilson whose telephone number is (571)272-5640. The examiner can normally be reached 1000-1700 EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Patrick Edouard can be reached at 571-272-7603. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Douglas Wilson/Primary Examiner, Art Unit 2622