Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 7 is objected to because of the following informalities: “with at first surface” should be corrected to “with a first surface.” Appropriate correction is required.
Claim 13 is objected to because of the following informalities: “wherein a surface of an electrically conductive material” should be corrected to “wherein a surface of the electrically conductive material.” Appropriate correction is required.
Claim Rejections - 35 USC § 112(a)
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 14 and 15 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the enablement requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to enable one skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention.
Regarding claims 14 and 15, the specification fails to describe the claimed process of concurrently depositing the blocking layer and the intermediary layer in sufficient detail to enable a person having ordinary skill in the art to perform this process. The “concurrent” deposition method described in paragraph [0049] of the specification is a process that selectively deposits the ammonia-based blocking layer and then subsequently deposits the intermediary layer. If these two layers are in fact deposited at the same time, detail sufficient to allow a person having reasonable skill in the art to perform this step must be added to the specification.
For purposes of compact prosecution, claims 14 and 15 will be assumed to claim subsequent deposition rather than concurrent deposition of the blocking layer and the intermediary layer.
Claim Rejections - 35 USC § 112(b)
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 7 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 7, MPEP 2111.02 states:
I. PREAMBLE STATEMENTS LIMITING STRUCTURE
Any terminology in the preamble that limits the structure of the claimed invention must be treated as a claim limitation. See, e.g., Corning Glass Works v. Sumitomo Elec. U.S.A., Inc., 868 F.2d 1251, 1257, 9 USPQ2d 1962, 1966 (Fed. Cir. 1989)
Here, the preamble limits the structure of the claimed invention to “a semiconductor substrate layer,” but the last limitation of the claim teaches that the semiconductor substrate layer comprises “a die coupled to the first layer.” Figure 7B of the disclosure plainly shows that the die coupled to the first layer is not a part of the semiconductor substrate layer claimed in the preamble; therefore, this claim limitation is not supported by the disclosure.
A possible way to correct this claim is to change the last limitation to state that the first layer is configured to couple to a die. For purposes of compact prosecution, the last limitation will be interpreted in this way.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Cheng et al. US 20110101527.
Regarding claim 1, Cheng discloses a semiconductor substrate comprising:
a layer having one or more openings (figure 1A, the layer comprising 101/109/110 has opening 120);
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a cavity extending from the one or more openings into the layer, the cavity having side walls and a base (the cavity and its sidewalls and base are shown in annotated figure 1A);
an electrically conductive material positioned proximate to the base of the cavity (figure 1, layer 105 is an electrically conductive material [0019] positioned near the base of the cavity),
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the electrically conductive material having a first surface facing the base and an exposed surface opposed to the first surface and the exposed surface faces the one or more openings (see the second annotated figure 1A below);
and an intermediary layer coupled to at least a portion of the exposed surface of the electrically conductive material (figure 1B illustrates an intermediary layer comprising 111/125/126 , which is coupled to the exposed surface of the electrically conductive layer 105).
Regarding claim 2, semiconductor substrate of claim 1, wherein the layer is a dielectric layer (paragraphs [0018 and 0022] disclose that the semiconductor substrate layer 101/109/110 is a dielectric layer).
Regarding claim 3, the semiconductor substrate of claim 1, wherein the intermediary layer includes nickel, palladium and gold (paragraph [0028] discloses that layer 126 may include nickel-palladium-gold, NiPdAu).
Regarding claim 4, the semiconductor substrate of claim 1, wherein the layer does not include an undercut in the cavity (see figure 1A, which does not have an undercut in the cavity below opening 120).
Regarding claim 5, the semiconductor substrate of claim 1, wherein the intermediary layer is coupled to at least a portion of the side walls of the cavity (figure 1C shows that intermediary layer 111/125/126 is coupled to the sidewalls of the cavity).
Regarding claim 6, the semiconductor substrate of claim 1, wherein the electrically conductive material includes copper (paragraph [0022] disclose that the electrically conductive material may include copper).
Regarding claim 7, Cheng discloses a semiconductor substrate layer comprising:
a first layer including: an opening in a first surface or a second opposing surface (figure 1A - first layer 101/109/110 comprises an opening 120);
one or more cavities (figure 1A shows a cavity associated with opening 120);
wherein the one or more cavities is recessed a specified distance into the first layer (figure 1B shows that the cavities are recessed a specified distance H into the first layer 101/109/110);
an electrically conductive material disposed within the one or more cavities with at first surface facing the opening (figure 1B shows electrically conductive material 105 is disposed in the cavity with a first surface facing the opening 120 [0019]);
a dry deposition layer positioned on at least one of an inner surface of the one or more cavities or on the first surface of the electrically conductive material [Since this claim is a product-by-process claim, the product covered by the claim (the layer) is not expressly limited by the process steps (dry deposition) set forth in the claim. The product may be limited by the structure that can be implied from the steps (MPEP 2113 I). Therefore, the method of manufacture of the layer implied by the description “dry deposition” does not limit the claimed layer. (Figure 1B shows layer 125/126 deposited on the inner surface of the cavity and on first surface of the electrically conductive material 105.)].
and a die coupled to the first layer (In accordance with the 112(b) rejection above, this claim is interpreted to mean that the first layer of the semiconductor substrate layer is configured to be coupled to a die. Paragraph [0017] describes the possibility of connecting dies to the semiconductor substrate by means of the electrical connections of figures 1A-1D.)
Regarding claim 8, Cheng discloses the semiconductor substrate layer of claim 7, wherein the first layer is made from glass (Paragraph [0018] discloses that the first layer of the substrate 101/109/110 in figure 1A may be un-doped silicate glass).
Regarding claim 9, Cheng discloses the semiconductor substrate layer of claim 7, wherein the first layer includes a polymer (paragraph [0024] discloses that 110, part of first layer 101/109/110, is a polymer layer).
Regarding claim 10, Cheng discloses the semiconductor substrate layer of claim 7, wherein the electrically conductive material is copper (Paragraph [0020] discloses that the conductive material of substrate layer 105 may be copper).
Regarding claim 11, Cheng discloses the semiconductor substrate layer of claim 7, wherein the dry deposition layer includes at least one of nickel, palladium and gold (paragraph [0028] discloses that layer 126 may include nickel-palladium-gold, NiPdAu) .
Regarding claim 12, Cheng discloses the semiconductor substrate layer of claim 7, wherein the dry deposition layer is chemically bonded with an exposed surface of the one or more cavities and the electrically conductive material. [Since this claim is a product-by-process claim, the product covered by the claim is not expressly limited by the process steps (chemically bonded) set forth in the claim. The product may be limited by the structure that can be implied from the steps (MPEP 2113 I). In this case, the exposed surface of the cavity 110 may be considered to be bonded to the “dry deposition layer” 125/126, as described in paragraph [0040]].
Regarding claim 13, Cheng discloses a method of forming a semiconductor substrate layer with an electrically conductive material comprising:
forming at least one cavity within the semiconductor substrate layer (figure 1A, the layer comprising 101/109/110 has a cavity associated with opening 120);
wherein a surface of an electrically conductive material is exposed within the at least one cavity (the surface of electrically conductive layer 105 is exposed within the cavity as shown in figure 1A);
depositing a blocking layer on a first surface of the semiconductor substrate layer (figure 1B shows blocking layer 111/112 is deposited on the first surface of the semiconductor substrate layer) ; and
applying an intermediary layer to at least the exposed surface of the electrically conductive material (figure 1B shows that intermediary layer 125/126 is applied to the surface of the electrically conductive material 105).
Regarding claim 14, Cheng discloses the method of claim 13, further comprising introducing the blocking layer concurrently with the intermediary layer. As discussed in the 112(a) rejection above, this claim will be interpreted as “the method of claim 13, further comprising the intermediary layer subsequent to introducing the blocking layer.” (Paragraphs [0024 and 0025] disclose the introduction of the blocking layer 111/112, and paragraphs [0026 and 0028] disclose the subsequent introduction of the intermediary layer 125/126).
Regarding claim 15, Cheng discloses the method of claim 13, further comprising depositing the blocking layer with physical vapor deposition concurrently with application of the intermediary layer. As discussed in the 112(a) rejection above, this claim will be interpreted as “the method of claim 13, further comprising applying the intermediary layer subsequent to depositing the blocking layer with physical vapor deposition.” (Paragraph [0024] discloses that blocking layer component 111 may be deposited by physical vapor deposition (PVD) and paragraphs [0026 and 0028] disclose the subsequent deposition of the intermediary layer 125/126).
Regarding claim 16, Cheng discloses the method of claim 13, further comprising depositing the blocking layer on the first surface and on surfaces within the at least one cavity (figure 1B shows that the blocking layer 111/112 is deposited on the first surface, 101/109/110, and on surfaces within the cavity, 110 and 105).
Regarding claim 17, Cheng discloses the method of claim 13, wherein the blocking layer is an ammonia-based material (paragraph [0024] discloses that blocking layer 111 may be formed of tantalum nitride, an ammonia-based material).
Regarding claim 18, Cheng discloses the method of claim 13, further comprising removing the blocking layer after the intermediary layer has been applied (paragraph [0032] discloses that blocking layer 111/112 may be removed).
Regarding claim 18, Cheng discloses the method of claim 13, further comprising applying the intermediary layer with at least one of chemical vapor deposition or atomic layer deposition (paragraph [0026] discloses that the component of the intermediary layer 125 may be formed by commonly used chemical vapor deposition (CVD) methods).
Regarding claim 20, Cheng discloses the method of claim 13, wherein the semiconductor substrate layer is formed from at least one of a glass or a polymer (Paragraph [0018] discloses that the first layer of the substrate 101/109/110 in figure 1A may be un-doped silicate glass, while paragraph [0024] discloses that 110, part of first layer 101/109/110, is a polymer layer).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure : Noma et al. US 10535585 and Aggarwal et al. US 20240038694 (disclose similar semiconductor substrates with interconnections), Koh et al. US 20010019891 (discloses a method of forming copper interconnections and thin films using chemical vaper deposition), Brovman et al. US 20150348831 (discloses a substrate with a selectively formed barrier layer).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KATRINA M H WALJESKI-MOSES whose telephone number is (571)272-0731. The examiner can normally be reached Mon- Fri 7:30 am- 5 pm.
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/KATRINA WALJESKI-MOSES/Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818
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