`DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over OCHIAI JP 2000/022072 A (hereinafter referred to as Ochiai) in view of Yamada et al.US 2003/0085469 A1 (hereinafter referred to as Yamada).
Regarding claim 1, Ochiai discloses a system comprising: an integrated circuit package (fig. 1-4, integrated circuit package 1, par. [0012], [0027]); and a testing device to of socket pins (fig. 1-4, input terminal group 11, par. [0014] ], [0027]) of the integrated circuit package corresponding to a first portion (see fig. 1-4, left half of package 1 including first semiconductor chip 2) of a die area (fig. 1-4, first semiconductor chip 2, par. [0014] ], [0027]); and test a second portion of socket pins (fig. 1, input terminal group 15, par. [0016] ], [0027]) of the integrated circuit package corresponding to a second portion (see fig. 1-4, right half of package 1 including first semiconductor chip 3) of the die area (fig. 2, first semiconductor chip 3, par. [0016] ], [0027]).
Ochiai does not disclose test a first portion using a socket during a first pass and test a second portion using the socket during a second pass
Yamada discloses test (fig. 7, S15, par. [0094]) a first portion (fig. 4, region R1, par. [0077]) using a socket (fig. 8, testing board 2, par. [0093]) during a first pass (fig. 7, region R1 is selected for testing in the step S13, par. [0092]-[0094]) and test a second portion (fig. 4, region R2, par. [0077]) using the socket during a second pass (fig. 7, s19 -s15, par. [0096]-[0098]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to test a semiconductor chip by rotating with respect to a testing board about an axis symmetry, such that a second set contact electrode is contacted with a first set of contact pins of the testing board, as taught in Yamada in modifying the apparatus of Ochiai. The motivation would be to reduce the cost of functional test by performing all functional tests by one test board and one test program. (see Yamada: par. [0031]).
Regarding claim 2, Ochiai and Yamada discloses the system of claim 1, wherein Yamada discloses wherein the socket (fig. 1, testing board, par. [0005]) is too small for both the first portion (fig. 1, LSI chip 1 region R1-R2, par. [0005] [0007]) and the second portion (fig. 1, LSI chip 1 region R3-R4, par. [0005] [0007]) to be positioned on the socket at the same time.
The references are combined for the same reason already applied in the rejection of claim 1.
Regarding claim 3, Ochiai and Yamada discloses the system of claim 1, Yamada discloses wherein testing the second portion (fig. 4, region R2, par. [0077]) comprises rotating the integrated circuit package (fig. 4, LSI chip 1, par. [0076]) before positioning the second portion on the socket (fig. 8, testing board 2, par. [0093]).
Regarding claim 4, Ochiai and Yamada discloses the system of claim 3, wherein Yamada discloses rotating the integrated circuit package (fig. 4, LSI chip 1, par. [0076]) comprises a rotation of 180 degrees (par. [0077]).
The references are combined for the same reason already applied in the rejection of claim 1.
Regarding claim 5, Ochiai and Yamada discloses the system of claim 4, wherein Yamada discloses wherein the first portion (fig. 4, region R1, par. [0077]) of the integrated circuit package (fig. 4, LSI chip 1, par. [0076]) comprises a pin configuration (fig. 4, contact electrodes 11-14, par. [0078]) and the rotated second portion(fig. 4, region R2, par. [0077]) also comprises the pin configuration (see fig. 4, par. [0078])
The references are combined for the same reason already applied in the rejection of claim 1.
Regarding claim 6, Ochiai and Yamada discloses the system of claim 1, Yamada discloses wherein the second portion (fig. 4, region R2, par. [0077]) does not receive any signals from the testing device during the first pass (par. 0082]) and the first portion (fig. 4, region R1, par. [0077]) does not receive any signals from the testing device during the second pass( par. 0082]).
The references are combined for the same reason already applied in the rejection of claim 1.
Regarding claim 7, Ochiai and Yamada discloses the system of claim 1, Ochiai discloses wherein the first portion comprises at least a first die (fig. 1-4, first semiconductor chip 2, par. [0014], [0027]) and the second portion comprises at least a second die (fig. 2, first semiconductor chip 3, par. [0016], [0027]) of the integrated circuit package.
Regarding claim 8, Ochiai and Yamada discloses the system of claim 1, Yamada discloses wherein the testing device (fig. 5, scan circuit 23, par. [0107]) is to test various parameters associated with each die (fig. 4, LSI chip 1, par. [0076]).
The references are combined for the same reason already applied in the rejection of claim 1.
Regarding claim 9, Ochiai and Yamada discloses the system of claim 8, Yamada discloses wherein the various parameters comprise timing, voltage levels, current compensation, signal integrity, or any combination thereof (fig. 5, scan circuit results, par. [0107]).
The references are combined for the same reason already applied in the rejection of claim 1.
Regarding claim 10, Ochiai and Yamada discloses the system of claim 1, Yamada discloses wherein the first portion (fig. 4, region R1, par. [0082]) is isolated from the second portion (fig. 4, region R2, par. [0082]) during the test of the first portion and the test of the second portion.
The references are combined for the same reason already applied in the rejection of claim 1.
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Spano in view of Yamada.
Regarding claim 11, Spano discloses a method comprising: positioning an integrated circuit package (fig. 1, integrated circuit packages 102a, 102b, 102c, and 102d, col. 3, ln. 38-39) in a first position (fig. 2, partial sockets 108b-d, col. 4, ln. 64-66) on a socket (fig. 1, sockets 108a, 108b, 108c, and 108d, col. 3, ln. 47-49); testing a first portion of the integrated circuit package using the socket during a first period (fig. 3, blk. 306, col. 5, ln. 19-25); receiving a first response (fig. 3, blk. 306, col. 5, ln. 22-24) from at least one die of the first portion; testing a second portion of the integrated circuit package using the socket during a second period (fig. 3, blk. 314, col. 5, ln. 30-37); and receiving a second response from at least one die of the second portion (fig. 3, blk. 314, col. 5, ln. 30-37).
Spano does not disclose rotating the integrated circuit package to a second position on the socket.
Yamada discloses rotating the integrated circuit package (fig. 4, LSI chip 1, par. [0076]) to a second position on the socket (fig. 8, testing board 2, par. [0041], [0093]). (col. 4, ln. 32-43).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Spano by rotating the integrated circuit package relative to the testing board about an axis of symmetry, as taught by Yamada, such that a second set of contacts is brought into contact with the testing board. The motivation would be to reduce the cost of functional test by performing all functional tests by one test board and one test program. (see Yamada: par. [0031]).
Claim(s) 12-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Spano in view of Yamada as applied to claim 11 above, and further in view of Trobough et al. US 2010/0252920 A1 (hereinafter referred to as Trobough).
Regarding claim 12, Yamada and Spano discloses the method of claim 11, Yamada and Spano do not disclose wherein at least one of a socket pin of the at least one die of the second portion is depopulated while testing the first portion.
Trobough discloses wherein at least one of a socket pin (fig. 1, pins 102, par. [0012]) of the at least one die (fig. 3, pins 302, par. [0022]) of the second portion is depopulated (fig. 1, pins 104, par. [0013]) while testing the first portion.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide an integrated circuit package that includes a plurality of system functional pins, at least one system functional pin depopulation zone, as taught in Trobough in modifying the apparatus of Yamada and Spano. The motivation would be pin depopulation zone is used to provide mechanical seating between the package and a socket while the non-system functional pin sends test signals (see Trobough: abs.).
Regarding claim 13, Yamada, Spano and Trobough discloses the method of claim 11, Yamada discloses rotating the integrated circuit package (fig. 4, LSI chip 1, par. [0076]) to the second position.
Trobough discloses at least one die (fig. 3, pins 302, par. [0022]) of the first portion to be depopulated while testing the second portion (fig. 1, pins 104, par. [0013]).
The references are combined for the same reason already applied in the rejection of claim 12.
Claim(s) 14-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Spano in view of Yamada as applied to claim 11 above, and further in view of Sogani US 8,055,966 B1.
Regarding claim 14, Spano and Yamada discloses the method of claim 11, Spano and Yamada do not disclose wherein a die-to-die interface between the at least one die of the first portion and the at least one die of the second portion are power isolated.
Sogani discloses wherein a die-to-die interface (fig. 3, elm. 306, col. 7, ln. 43-45) between the at least one die (fig. 3, elm. 302, col. 7, ln. 43-45) of the first portion (see fig. 2) and the at least one die (fig. 3, elm. 304, col. 7, ln. 53-55) of the second portion (see fig. 2) are power isolated (fig. 3, col. 7, ln. 52-67).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to test dies within a single multiple-integrated circuit package and method for isolating the power plane for each die in order to create a testing environment that enable each die to be tested individually, as taught in Sogani in modifying the apparatus of Spano and Yamada. The motivation would be to isolate the "test" die from the other electronic components in order to prevent the possibility of conflict during the testing. (see Sogani: col. 4, ln. 29-33).
Regarding claim 15, Spano Yamada and Sogani discloses the method of claim 11, Sogani discloses wherein testing the first portion and testing the second portion comprise sending testing signals (test pattern, col. 5, ln. 13-23) to the at least one die of the first portion and the at least one die of the second portion, wherein the testing signals are isolated in the at least one die of the first portion and the at least one die of the second portion (col. 5, ln. 13-23).
The references are combined for the same reason already applied in the rejection of claim 14.
Claim(s) 16, 18-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ochiai in view of Sogani.
Regarding claim 16, Ochiai discloses a receive a first response from a die (fig. 1-4, first semiconductor chip 2, par. [0014] ], [0027]) of a first portion (see fig. 1-4, left half of package 1 including first semiconductor chip 2) of an integrated circuit package (fig. 1-4, integrated circuit package 1, par. [0012], [0027]) from a test of a first portion of socket pins (fig. 4, groups 11, 12, 14, par. [0027]) of the integrated circuit package; receive a second response from a die (fig. 2, first semiconductor chip 3, par. [0016] ], [0027]) of a second portion (see fig. 1-4, right half of package 1 including first semiconductor chip 3) of the integrated circuit package from a test of a second portion of socket pins (fig. 4, groups 15, 17, 18, par. [0027]) of the integrated circuit package corresponding to a second portion of the die area; analyze the first response from the die of the first portion (par. [0030]); analyze the second response from the die of the second portion (par. [0031]).
Ochiai does not disclose a tangible, non-transitory, and computer-readable medium, storing instructions thereon that when executed are to cause a processor;
determine whether the die of the first portion and the die of the second portion are operating correctly.
Sogani discloses a tangible, non-transitory, and computer-readable medium, storing instructions thereon that when executed are to cause a processor (col. 3, ln. 22-39): determine whether the die of the first portion and the die of the second portion are operating correctly (fig. 5, step 502-516, col. 9, ln. 40-col. 10, ln.14).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to test dies within a single multiple-integrated circuit package and method for isolating the power plane for each die in order to create a testing environment that enable each die to be tested individually, as taught in Sogani in modifying the apparatus of Ochiai. The motivation would be to isolate the "test" die from the other electronic components in order to prevent the possibility of conflict during the testing. (see Sogani: col. 4, ln. 29-33).
Regarding claim 18, Ochiai and Sogani discloses the tangible, non-transitory, and computer-readable medium of claim 16, Sogani discloses wherein the instructions, when executed, are to cause the processor (col. 3, ln. 22-39) to in response to identifying that the die of the first portion is not operating correctly (fig. 5, step 502-516, col. 9, ln. 40-col. 10, ln.14), powering down the die of the first portion.
Regarding claim 19, Ochiai and Sogani discloses the tangible, non-transitory, and computer-readable medium of claim 16, Sogani discloses wherein the instructions, when executed, are to cause the processor (col. 3, ln. 22-39) to transmit an indication indicating that the dies of the integrated circuit package are operating correctly in response to determining that the die of the first portion and the die of the second portion are operating correctly (fig. 5, step 502-516, col. 9, ln. 40-col. 10, ln.14).
Claim(s) 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ochiai in view of Sogani as applied to claim 16 above, and further in view of
Chih et al. US 6,351,681 B1 (hereinafter referred to as Chih).
Regarding claim 17, Ochiai and Sogani discloses the tangible, non-transitory, and computer-readable medium of claim 16, Ochiai and Sogani do not disclose wherein determining whether the die of the first portion and the die of the second portion are operating correctly comprises comparing a first set of data from the first response and a second set of data from the second response to a specific set of data.
Chih discloses wherein determining whether the die of the first portion and the die of the second portion are operating correctly comprises comparing a first set of data from the first response and a second set of data from the second response to a specific set of data (fig. 3, step 129-step 130, col.8, ln.58-col. 9, ln. 30).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the testing arrangement of Ochiai and Sogani to compare response data obtained from the dies with specified expected data, as taught by Chih, in order to determine whether the respective dies are operating correctly and thereby permit reconfiguration of the multi-chip module based on the testing results. (see Chih: abs.).
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ochiai in view of Sogani as applied to claim 16 above, and further in view of
Louie et al. US 2006/0048033 A1 (hereinafter referred to as Louie).
Regarding claim 20, Ochiai and Sogani discloses the tangible, non-transitory, and computer-readable medium of claim 16, Sogani discloses wherein the instructions, when executed, are to cause the processor (col. 3, ln. 22-39) to: receive an invalid response from the die of the first portion, the die of the second portion, or any combination thereof (fig. 5, step 502-516, col. 9, ln. 40-col. 10, ln.14).
Ochiai and Sogani do not disclose and individually power down the die of the first portion, the die of the second portion, or any combination thereof based on the invalid response.
Louie disclose and individually power down the die of the first portion, the die of the second portion, or any combination thereof based on the invalid response (fig. 2, par. [0008], [0019]- [0022]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a method of operating an integrated circuit device that includes receiving a sequence of commands at the integrated circuit device, enabling a test mode of the integrated circuit device in response to the command sequence when all of the commands of the sequence are correct, and disabling the test mode upon receiving an incorrect command of the sequence, as taught in Louie in modifying the apparatus of Ochiai and Sogani. The motivation would be to prevent inadvertent access of the test mode of the integrated circuit device using the sequence of commands. (see Louie, par. [0005]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to COURTNEY G MCDONNOUGH whose telephone number is (571)272-6552. The examiner can normally be reached M-F 8 am-5 pm.
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/COURTNEY G MCDONNOUGH/Examiner, Art Unit 2858
/FARHANA A HOQUE/Primary Examiner, Art Unit 2858 /
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