DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This Office Action is in response to Applicant's amendments filed August 26, 2026. Claims 1, 3-4, 10, 12, and 16 have been amended. Claims 21-22 have been added. Claims 2 and 11 have been canceled. Currently, claims 1, 3-10, and 12-22 are pending.
Applicant’s Amendments to the drawings overcome the drawing objection outlined in the previous Office Action. The drawing objection has been withdrawn.
Applicant’s Amendment to claim 13 overcomes the 112(b) rejection outlined in the previous Office Action. The 112(b) rejection of claim 13 has been withdrawn.
Response to Arguments
Applicant’s arguments with respect to claims 1, 10, and 16 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 21 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 21, the claim recites the limitation "the gate structure" in line 2. There is insufficient antecedent basis for this limitation in the claim.
It is indefinite whether the gate structure refers to the first gate structure of claim 16, line 4 or some other gate structure. For the purposes of examination, the former interpretation will be used.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-7, 10-14, 16-17, 19, and 21-22 are rejected under 35 U.S.C. 103 as being unpatentable over Ren et al. (US 20220285274 A1) herein after “Ren” in view of Yang et al. (US 20140220777 A1) herein after “Yang”.
Regarding claim 1, Figs. 6 and 20 of Ren disclose an integrated circuit (Fig. 6, IC product 100, ¶ [0018]) comprising:
a semiconductor device having a semiconductor region (Fig. 20, active semiconductor layer 102C, ¶ [0018]) extending in a first direction from a source or drain region (Fig. 20, epitaxial semiconductor material 114, ¶ [0021]), and a gate electrode (Fig. 20, gate structures 106, ¶ [0019]) extending in a second direction over the semiconductor region (102C); and
a dielectric wall (Fig. 20, sidewall spacer 136, ¶ [0029]) adjacent to the semiconductor device along the second direction and extending in the third direction through the entire thickness of the gate electrode (106),
a conductive via (Fig. 20, conductive well tap 150, ¶ [0031]) extending in the third direction through an entire thickness of the dielectric wall (136) such that the dielectric wall (136) is between the conductive via (150) and the gate electrode (106) along the second direction (shown in Fig. 22), wherein the conductive via (150) comprises a conductive liner (“barrier layer”) and a conductive fill (150) on the conductive liner (“barrier layer”, ¶ [0031]),
the dielectric wall (136) between the conductive via (150) and the gate electrode (106).
Ren fails to explicitly disclose wherein the conductive liner comprises a pure elemental metal, and wherein the pure elemental metal of the conductive liner is also present in at least a portion of the dielectric wall.
In the similar field of endeavor of interconnect structures, Fig. 5 of Yang discloses wherein the conductive liner (Fig. 5, diffusion barrier 16, ¶ [0031]) comprises a pure elemental metal (“The diffusion barrier 16 includes..., W”, ¶ [0032]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify conductive via of Ren to include the conductive liner as disclosed by Yang, to improve the electrical properties of the via structure (see Yang, ¶ [0021]).
Yang fails to explicitly disclose wherein the pure elemental metal of the conductive liner is also present in at least a portion of the dielectric wall.
However, the instant application discloses, in ¶ [0054], that “a PVD process causes some of the metal atoms to penetrate into the sidewall”. Yang discloses the same materials for the dielectric wall (see Yang, ¶ [0028]) and the conductive liner (see Yang, ¶ [0032]). Yang further discloses depositing the conductive liner onto dielectric material using a PVD process (see Yang, ¶ [0033]). Therefore, the Examiner asserts that Yang inherently discloses the limitations of wherein the pure elemental metal of the conductive liner is also present in at least a portion of the dielectric wall.
Regarding claim 3, Ren and Yang together disclose the integrated circuit of claim 1 as applied above, and Ren further discloses wherein the conductive liner (“barrier layer”) is directly on the dielectric wall (136) (“one or more conformal barrier layers and/or seed layers (not separately shown) were formed so as to line the various openings with the barrier material”, ¶ [0034]).
Ren fails to disclose wherein the conductive liner consists essentially of the pure elemental metal.
In the similar field of endeavor of interconnect structures, Fig. 5 of Yang discloses wherein the conductive liner (16) consists essentially of the pure elemental metal (“The diffusion barrier 16 includes…, W”, ¶ [0032]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify conductive via of Ren to include the conductive liner as disclosed by Yang, to improve the electrical properties of the via structure (see Yang, ¶ [0021]) and/or because the use of conventional materials to perform their known function is prima-facie obvious (MPEP 2144.07).
Regarding claim 4, Ren and Yang together disclose the integrated circuit of claim 1 as applied above, but Ren and Yang fail to explicitly disclose wherein the pure elemental metal of the conductive liner penetrates about 4.5 nm into the dielectric wall.
However, the instant application discloses, in ¶ [0054], that “a PVD process causes some of the metal atoms to penetrate into the sidewall”.
In the similar field of endeavor of interconnect structures, Yang discloses the same materials for the dielectric wall (see Yang, ¶ [0028]) and the conductive liner (see Yang, ¶ [0032]). Yang further discloses depositing the conductive liner onto dielectric material using a PVD process (see Yang, ¶ [0033]). Therefore, the Examiner asserts that Yang inherently discloses the limitations of wherein the pure elemental metal of the conductive liner penetrates about 4.5 nm into the dielectric wall.
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify conductive via of Ren to include the conductive liner as disclosed by Yang, to improve the electrical properties of the via structure (see Yang, ¶ [0021]).
Regarding claim 5, Ren and Yang together disclose the integrated circuit of claim 1 as applied above, but Ren fails to disclose wherein the conductive fill comprises the pure elemental metal.
In the similar field of endeavor of interconnect structures, Fig. 5 of Yang discloses wherein the conductive fill (Fig. 5, interconnect conductive metal 20, ¶ [0036]) comprises the pure elemental metal (“the metal liner 18 may comprise…, W”, ¶ [0034]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify conductive via of Ren to include the conductive liner as disclosed by Yang, to improve the electrical properties of the via structure (see Yang, ¶ [0021]) and/or because the use of conventional materials to perform their known function is prima-facie obvious (MPEP 2144.07).
Regarding claim 6, Ren and Yang together disclose the integrated circuit of claim 1 as applied above, but Ren fails to disclose wherein the pure elemental metal is a first pure elemental metal, and wherein the conductive fill comprises a second pure elemental metal different from the first pure elemental metal.
In the similar field of endeavor of interconnect structures, Fig. 5 of Yang discloses wherein the pure elemental metal is a first pure elemental metal (“The diffusion barrier 16 includes…, W”, ¶ [0032]), and wherein the conductive fill (20) comprises a second pure elemental metal (“the metal liner 18 may comprise Cu”, ¶ [0034]) different from the first pure elemental metal.
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify conductive via of Ren to include the materials as disclosed by Yang, to improve the electrical properties of the via structure (see Yang, ¶ [0021]) and/or because the use of conventional materials to perform their known function is prima-facie obvious (MPEP 2144.07).
Regarding claim 7, Ren and Yang together disclose the integrated circuit of claim 1 as applied above, but Ren fails to explicitly disclose wherein no oxygen atoms exist at an interface between the conductive liner and the conductive fill.
However, the instant application discloses, in ¶ [0014], that the deposition of the conductive liner and conductive fill are performed in-situ such that no oxygen atoms exist at an interface.
In the similar field of endeavor of interconnect structures, Fig. 5 of Yang discloses a conductive liner (16) and a conductive fill (Fig. 5, interconnect conductive metal 20, ¶ [0036]) formed without breaking vacuum (“depositing the diffusion barrier 16, the metal liner 18, and performing the reflow anneal without breaking vacuum between these various processing steps”, ¶ [0040]) which “allows for the clean formation of a Cu/liner interface without air exposure”, ¶ [0021]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the conductive liner and conductive fill of Ren such that there were no oxygen atoms exist at the interface as disclosed by Yang, to improve the electrical properties of the via structure (see Yang, ¶ [0021]).
Regarding claim 10, Figs. 6 and 20 of Ren disclose an electronic device, comprising:
a chip package comprising one or more dies, at least one of the one or more dies comprising a semiconductor region (102C) extending in a first direction from a first source or drain region (114) to a second source or drain region (114);
a gate structure (106) extending in a second direction over the semiconductor region (102C); and
a dielectric wall (136) adjacent to the semiconductor region (102C) along the second direction and extending in the third direction through the entire thickness of the gate structure (106),
a conductive via (150) extending in the third direction through an entire thickness of the dielectric wall (136) such that the dielectric wall (136) is between the conductive via (150) and the gate electrode (106) along the second direction, wherein the conductive via (150) comprises a conductive liner (“barrier layer”) and a conductive fill (150) on the conductive liner (“barrier layer”),
the dielectric wall (136) between the conductive via (150) and the gate structure (106).
Ren fails to explicitly disclose wherein the conductive liner comprises a pure elemental metal, and wherein the pure elemental metal of the conductive liner is also present in at least a portion of the dielectric wall.
In the similar field of endeavor of interconnect structures, Fig. 5 of Yang discloses wherein the conductive liner (16) comprises a pure elemental metal (“The diffusion barrier 16 includes..., W”, ¶ [0032]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify conductive via of Ren to include the conductive liner as disclosed by Yang, to improve the electrical properties of the via structure (see Yang, ¶ [0021]).
Yang fails to explicitly disclose wherein the pure elemental metal of the conductive liner is also present in at least a portion of the dielectric wall.
However, the instant application discloses, in ¶ [0054], that “a PVD process causes some of the metal atoms to penetrate into the sidewall”. Yang discloses the same materials for the dielectric wall (see Yang, ¶ [0028]) and the conductive liner (see Yang, ¶ [0032]). Yang further discloses depositing the conductive liner onto dielectric material using a PVD process (see Yang, ¶ [0033]). Therefore, the Examiner asserts that Yang inherently discloses the limitations of wherein the pure elemental metal of the conductive liner is also present in at least a portion of the dielectric wall.
Regarding claim 12, Ren and Yang together disclose the integrated circuit of claim 10 as applied above, and Ren further discloses wherein the conductive liner (“barrier layer”) is directly on the dielectric wall (136) (“one or more conformal barrier layers and/or seed layers (not separately shown) were formed so as to line the various openings with the barrier material”, ¶ [0034]).
Regarding claim 13, Ren and Yang together disclose the electronic device of claim 10 as applied above, but Ren fails to disclose wherein the pure elemental metal is tungsten, molybdenum, or ruthenium.
In the similar field of endeavor of interconnect structures, Fig. 5 of Yang discloses wherein the pure elemental metal is tungsten, molybdenum, or ruthenium (“The diffusion barrier 16 includes…, W”, ¶ [0032]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify conductive via of Ren to include the conductive liner as disclosed by Yang, to improve the electrical properties of the via structure (see Yang, ¶ [0021]) and/or because the use of conventional materials to perform their known function is prima-facie obvious (MPEP 2144.07).
Regarding claim 14, Ren and Yang together disclose the electronic device of claim 10 as applied above, but Ren fails to explicitly disclose wherein no oxygen atoms exist at an interface between the conductive liner and the conductive fill.
However, the instant application discloses, in ¶ [0014], that the deposition of the conductive liner and conductive fill are performed in-situ such that no oxygen atoms exist at an interface.
In the similar field of endeavor of interconnect structures, Fig. 5 of Yang discloses a conductive liner (16) and a conductive fill (20) formed without breaking vacuum (“depositing the diffusion barrier 16, the metal liner 18, and performing the reflow anneal without breaking vacuum between these various processing steps”, ¶ [0040]) which “allows for the clean formation of a Cu/liner interface without air exposure”, ¶ [0021]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the conductive liner and conductive fill of Ren such that there were no oxygen atoms exist at the interface as disclosed by Yang, to improve the electrical properties of the via structure (see Yang, ¶ [0021]).
Regarding claim 16, Figs. 6 and 20 of Ren disclose an integrated circuit comprising:
a first semiconductor device having a first semiconductor region (102C) extending in a first direction from a first source or drain region (114) to a second source or drain region (114), and a first gate structure (106) extending in a second direction over the first semiconductor region (102C);
a second semiconductor device having a second semiconductor region (102C) extending in the first direction from a third source or drain region (114) to a fourth source or drain region (114),and a second gate structure (106) extending in the second direction over the second semiconductor region (102C), the third source or drain region (114) being aligned with the first source or drain region (114) along the second direction, and the fourth source or drain region (114) being aligned with the second source or drain region (114) along the second direction;
a dielectric structure (136) extending laterally between the first and second semiconductor devices and extending in a third direction through an entire thickness of the first gate structure and the second gate structure; and
a conductive via (150) extending in a third direction through an entire thickness of the dielectric structure (136) such that the dielectric structure (136) is between the conductive via (150) and the first gate structure (106) along the second direction and is between the conductive via (150) and the second gate structure (106) along the second direction, wherein the conductive via (150) comprises a conductive liner (“barrier layer”) and a conductive fill (150) on the conductive liner (“barrier layer”),
and wherein the conductive liner (“barrier layer”) directly on sidewalls of the dielectric structure (136) facing the first gate structure and the second gate structure along the second direction.
Ren fails to disclose wherein the conductive liner consists essentially of the pure elemental metal.
In the similar field of endeavor of interconnect structures, Fig. 5 of Yang discloses wherein the conductive liner (16) consists essentially of the pure elemental metal (“The diffusion barrier 16 includes…, W”, ¶ [0032]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify conductive via of Ren to include the conductive liner as disclosed by Yang, to improve the electrical properties of the via structure (see Yang, ¶ [0021]) and/or because the use of conventional materials to perform their known function is prima-facie obvious (MPEP 2144.07).
Regarding claim 17, Ren and Yang together disclose the integrated circuit of claim 16 as applied above, and Ren further discloses wherein the conductive fill (150) comprises the pure elemental metal (“conductive materials (e.g., copper”, ¶ [0034]).
Regarding claim 19, Ren and Yang together disclose the integrated circuit of claim 16 as applied above, but Ren fails to disclose wherein the pure elemental metal is a first pure elemental metal, and wherein the conductive fill comprises a second pure elemental metal different from the first pure elemental metal.
In the similar field of endeavor of interconnect structures, Fig. 5 of Yang discloses wherein the pure elemental metal is a first pure elemental metal (“The diffusion barrier 16 includes…, W”, ¶ [0032]), and wherein the conductive fill (20) comprises a second pure elemental metal (“the metal liner 18 may comprise Cu”, ¶ [0034]) different from the first pure elemental metal.
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify conductive via of Ren to include the materials as disclosed by Yang, to improve the electrical properties of the via structure (see Yang, ¶ [0021]) and/or because the use of conventional materials to perform their known function is prima-facie obvious (MPEP 2144.07).
Regarding claim 21, Ren and Yang together disclose the integrated circuit of claim 16 as applied above, and Ren further discloses the dielectric wall (136) between the conductive via (150) and the gate structure (106).
Ren fails to disclose wherein the pure elemental metal of the conductive liner is also present in at least a portion of the dielectric wall.
In the similar field of endeavor of interconnect structures, Fig. 5 of Yang discloses wherein the conductive liner (16) comprises a pure elemental metal (“The diffusion barrier 16 includes..., W”, ¶ [0032]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify conductive via of Ren to include the conductive liner as disclosed by Yang, to improve the electrical properties of the via structure (see Yang, ¶ [0021]).
Yang fails to explicitly disclose wherein the pure elemental metal of the conductive liner is also present in at least a portion of the dielectric wall.
However, the instant application discloses, in ¶ [0054], that “a PVD process causes some of the metal atoms to penetrate into the sidewall”. Yang discloses the same materials for the dielectric wall (see Yang, ¶ [0028]) and the conductive liner (see Yang, ¶ [0032]). Yang further discloses depositing the conductive liner onto dielectric material using a PVD process (see Yang, ¶ [0033]). Therefore, the Examiner asserts that Yang inherently discloses the limitations of wherein the pure elemental metal of the conductive liner is also present in at least a portion of the dielectric wall.
Regarding claim 22, Ren and Yang together disclose the integrated circuit of claim 1 as applied above, but Ren fails to disclose wherein the pure elemental metal is tungsten, molybdenum, or ruthenium.
In the similar field of endeavor of interconnect structures, Fig. 5 of Yang discloses wherein the pure elemental metal is tungsten, molybdenum, or ruthenium (“The diffusion barrier 16 includes…, W”, ¶ [0032]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify conductive via of Ren to include the conductive liner as disclosed by Yang, to improve the electrical properties of the via structure (see Yang, ¶ [0021]) and/or because the use of conventional materials to perform their known function is prima-facie obvious (MPEP 2144.07).
Claims 8, 15, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Ren (US 20220285274 A1) and Yang (US 20140220777 A1) in further view of Werkhoven et al. (US 20030129826 A1) herein after “Werkhoven”.
Regarding claim 8, Ren and Yang together disclose the electronic device of claim 1 as applied above, but Ren and Yang fail to explicitly disclose wherein no carbon, fluorine, or chlorine atoms exist within the conductive liner.
In the similar field of endeavor of integrated circuit manufacturing, Figs. 10-11 of Werkhoven disclose wherein no carbon, fluorine, or chlorine atoms exist within the conductive liner (436) (“Advantageously, the process employs an intermediate reduction phase to remove halide tails between metal and nitrogen source phases. This intermediate reduction phase avoids build up of hydrogen halides”, ¶ [0105]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the conductive liner of Ren with the material as disclosed by Werkhoven, to improve manufacturing quality of the subsequent metal layer (see Werkhoven, ¶ [0105]) and/or because the use of conventional materials to perform their known function is prima-facie obvious (MPEP 2144.07).
Regarding claim 15, Ren and Yang together disclose the electronic device of claim 10 as applied above, but Ren and Yang fail to explicitly disclose wherein no carbon, fluorine, or chlorine atoms exist within the conductive liner.
In the similar field of endeavor of integrated circuit manufacturing, Figs. 10-11 of Werkhoven disclose wherein no carbon, fluorine, or chlorine atoms exist within the conductive liner (436) (“Advantageously, the process employs an intermediate reduction phase to remove halide tails between metal and nitrogen source phases. This intermediate reduction phase avoids build up of hydrogen halides”, ¶ [0105]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the conductive liner of Ren with the material as disclosed by Werkhoven, to improve manufacturing quality of the subsequent metal layer (see Werkhoven, ¶ [0105]) and/or because the use of conventional materials to perform their known function is prima-facie obvious (MPEP 2144.07).
Regarding claim 18, Ren and Yang together disclose the electronic device of claim 16 as applied above, but Ren and Yang fail to explicitly disclose wherein no carbon, fluorine, or chlorine atoms exist within the conductive liner.
In the similar field of endeavor of integrated circuit manufacturing, Figs. 10-11 of Werkhoven disclose wherein no carbon, fluorine, or chlorine atoms exist within the conductive liner (436) (“Advantageously, the process employs an intermediate reduction phase to remove halide tails between metal and nitrogen source phases. This intermediate reduction phase avoids build up of hydrogen halides”, ¶ [0105]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the conductive liner of Ren with the material as disclosed by Werkhoven, to improve manufacturing quality of the subsequent metal layer (see Werkhoven, ¶ [0105]) and/or because the use of conventional materials to perform their known function is prima-facie obvious (MPEP 2144.07).
Claims 9 is rejected under 35 U.S.C. 103 as being unpatentable over Ren (US 20220285274 A1) and Yang (US 20140220777 A1) in further view of Ku et al. (US 20230178589 A1) herein after “Ku”.
Regarding claim 9, Ren and Yang together disclose the electronic device of claim 1 as applied above, but Ren and Yang fail to explicitly disclose a printed circuit board comprising the integrated circuit.
In the similar field of endeavor of semiconductor structures, Ku discloses a printed circuit board comprising the integrated circuit (“TSV 130 of semiconductor structure 100 is physically and/or electrically connected to …a printed circuit board (PCB)”, ¶ [0046]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the structure of Ren by incorporating the printed circuit board as disclosed by Ku. The claimed printed circuit board was known in the prior art and one skilled in the art could have combined the structure of Ren with that of Ku as claimed with no change in their respective functions, and the combination would have yielded the predictable result of creating an electronic device. See KSR International Co. V. Teleflex Inc., 82 USPQ2d 1385 (2007).
Claim 20 are rejected under 35 U.S.C. 103 as being unpatentable over Ren (US 20220285274 A1) and Yang (US 20140220777 A1) in further view of Seo et al. (US 20240178061 A1) herein after “Seo”.
Regarding claim 20, Ren and Yang together disclose the electronic device of claim 16 as applied above, but Ren and Yang fail to disclose wherein the conductive liner has a first thickness on sidewalls of the dielectric structure, and a second thickness on a bottom of the via, the second thickness being at least 2 nm thicker than the first thickness.
In the similar field of endeavor of integrated circuit devices, Fig. 2C of Seo discloses wherein the conductive liner (Fig. 2C, second metal liner 192B, ¶ [0057]) has a first thickness on sidewalls of the dielectric structure (Fig. 2C, capping insulating pattern 168, ¶ [0037]), and a second thickness on a bottom of the via (Fig. 2C, second metal plug 196B, ¶ [0057]) (“a portion of the second metal liner 192B, which covers a bottom surface of the second metal plug 196B, may have a greater thickness than a portion of the second metal liner 192B, which covers the sidewalls of the second metal plug 196B”, ¶ [0063]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the conductive liner of Ren with the thickness as disclosed by Seo, to obtain the desired electrical properties (see Seo, ¶ [0069-0070]).
Seo fails to explicitly disclose the second thickness being at least 2 nm thicker than the first thickness.
However, it has been held that where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed element, and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device (MPEP 2144.04).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention that a mere change in thickness of the conductive liner was within the level of ordinary skill in the art and/or because changes in size and shape are prima facie obvious absent persuasive evidence that the particular configuration is significant (MPEP 2144.04(IV)).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/C.A.N./Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893
