CTNF 18/217,208 CTNF 100146 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Drawings 06-22-02 AIA The drawings are objected to as failing to comply with 37 CFR 1.84(p)(4) because reference characters " 226 " and " 228 " have both been used to designate the bottom portion of the via in Figs. 2H and 2I . Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. 06-22-03 AIA The drawings are objected to as failing to comply with 37 CFR 1.84(p)(4) because reference character “ 226 ” has been used to designate both the bottom portion of the via before the metal fill is formed in Fig. 2H and the metal fill in Fig. 2I . Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Claim Rejections - 35 USC § 112 07-30-02 AIA The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. 07-34-01 Claim 13 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Regarding claim 13, the claim recites the limitation “wherein the pure elemental metal is tungsten, molybdenum, ruthenium, or a nickel aluminum alloy ” (emphasis added) which is indefinite because it is unclear how a nickel aluminum alloy falls into a group of pure elemental metals. Appropriate correction is required. Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-15 AIA Claim s 1-3, 5-6, 10-13, 16-17, and 19 are rejected under 35 U.S.C. 102( a)(1 ) as being anticipated by Vega et al. (US 20230093462 A1) herein after “Vega” . Regarding claim 1, Figs. 1-2 of Vega disclose an integrated circuit (Fig. 1, “a semiconductor device”, ¶ [0008]) comprising: a semiconductor device having a semiconductor region (Fig. 1, active semiconductor region 120, ¶ [0024]) extending in a first direction from a source or drain region (Fig. 2, source/drain 220, ¶ [0036]), and a gate electrode (Fig. 1, active gate structure 140, ¶ [0024]) extending in a second direction over the semiconductor region (120); and a conductive via (Fig. 1, gate contact 160, ¶ [0026]) extending in a third direction through an entire thickness of the gate electrode (140) and adjacent to the semiconductor device in the second direction, wherein the conductive via (160) comprises a conductive liner (Fig. 1, first conductive layer 162, ¶ [0027]) and a conductive fill (Fig. 1, second conductive material 165, ¶ [0027]) on the conductive liner (162), and wherein the conductive liner (162) comprises a pure elemental metal (“the first conductive layer 162 can be a metal, including…, molybdenum (Mo)”, ¶ [0028]). Regarding claim 2, Figs. 1-2 of Vega disclose the integrated circuit of claim 1 as applied above, and Fig. 1 of Vega further discloses comprising a dielectric wall (Fig. 1, gate cut dielectric 150, ¶ [0032]) extending in the third direction through the entire thickness of the gate electrode (140), wherein the conductive via (160) extends through an entire thickness of the dielectric wall (150) in the third direction (shown in Fig. 1). Regarding claim 3, Fig. 1 of Vega discloses the integrated circuit of claim 2 as applied above, and Fig. 1 of Vega further discloses wherein the conductive liner (162) consists essentially of the pure elemental metal (“the first conductive layer 162 can be a metal, including…, molybdenum (Mo)”, ¶ [0028]) and is directly on the dielectric wall (150). Regarding claim 5, Figs. 1-2 of Vega disclose the integrated circuit of claim 1 as applied above, and Fig. 1 of Vega further discloses wherein the conductive fill (165) comprises the pure elemental metal (“the second conductive material 165 can be a metal, including, but not limited to, copper (Cu), tungsten (W)”, ¶ [0029]). Regarding claim 6, Figs. 1-2 of Vega disclose the integrated circuit of claim 1 as applied above, and Fig. 1 of Vega further discloses wherein the pure elemental metal is a first pure elemental metal (“the first conductive layer 162 can be a metal, including…, molybdenum (Mo)”, ¶ [0028]), and wherein the conductive fill (165) comprises a second pure elemental metal different from the first pure elemental metal (“The second conductive material 165 can be a different conductive material from the first conductive layer 162”, ¶ [0029]). Regarding claim 10, Figs. 1-2 of Vega disclose an electronic device (“the chip is mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (such as a ceramic carrier that has either or both surface interconnections or buried interconnections)”, ¶ [0089]), comprising: a chip package comprising one or more dies, at least one of the one or more dies comprising a semiconductor region (120) extending in a first direction from a first source or drain region (220) to a second source or drain region (220); a gate structure (140) extending in a second direction over the semiconductor region (120); and a conductive via (160) extending in a third direction through an entire thickness of the gate structure (140) and adjacent to the semiconductor region (120) in the second direction, wherein the conductive via (160) comprises a conductive liner (162) and a conductive fill (165) on the conductive liner (162), and wherein the conductive liner (162) comprises a pure elemental metal (“the first conductive layer 162 can be a metal, including…, molybdenum (Mo)”, ¶ [0028]). Regarding claim 11, Figs. 1-2 of Vega disclose the electronic device of claim 10 as applied above, and Fig. 1 of Vega further discloses wherein the at least one of the one or more dies further comprises a dielectric wall (150) extending in the third direction through the entire thickness of the gate structure (140), wherein the conductive via (160) extends through an entire thickness of the dielectric wall (150) in the third direction (shown in Fig. 1). Regarding claim 12, Fig. 1 of Vega discloses the integrated circuit of claim 11 as applied above, and Fig. 1 of Vega further discloses wherein the conductive liner (162) is directly on the dielectric wall (150). Regarding claim 13, Figs. 1-2 of Vega disclose the electronic device of claim 10 as applied above, and Fig. 1 of Vega further discloses wherein the pure elemental metal is tungsten, molybdenum, ruthenium, or a nickel aluminum alloy (“the first conductive layer 162 can be a metal, including…, molybdenum (Mo)”, ¶ [0028]). Regarding claim 16, Figs. 1-2 of Vega disclose an integrated circuit comprising: a first semiconductor device having a first semiconductor region (120) extending in a first direction from a first source or drain region (220) to a second source or drain region (220), and a first gate structure (140) extending in a second direction over the first semiconductor region (120); a second semiconductor device having a second semiconductor region (120) extending in the first direction from a third source or drain region (220) to a fourth source or drain region (220),and a second gate structure (140) extending in the second direction over the second semiconductor region (120), the third source or drain region (220) being aligned with the first source or drain region (220) along the second direction, and the fourth source or drain region (220) being aligned with the second source or drain region (220) along the second direction; a dielectric structure (150) extending laterally between the first and second semiconductor devices; and a conductive via (160) extending in a third direction through an entire thickness of the dielectric structure (150), wherein the conductive via (160) comprises a conductive liner (162) and a conductive fill (165) on the conductive liner (162), and wherein the conductive liner (162) consists essentially of a pure elemental metal (“the first conductive layer 162 can be a metal, including…, molybdenum (Mo)”, ¶ [0028]) directly on sidewalls of the dielectric structure (150). Regarding claim 17, Figs. 1-2 of Vega disclose the electronic device of claim 16 as applied above, and Fig. 1 of Vega further discloses wherein the conductive fill (165) comprises the pure elemental metal (“the second conductive material 165 can be a metal, including, but not limited to, copper (Cu), tungsten (W)”, ¶ [0029]). Regarding claim 19, Figs. 1-2 of Vega disclose the electronic device of claim 16 as applied above, and Fig. 1 of Vega further discloses wherein the pure elemental metal is a first pure elemental metal, and wherein the conductive fill (165) comprises a second pure elemental metal different from the first elemental metal (“The second conductive material 165 can be a different conductive material from the first conductive layer 162”, ¶ [0029]) . Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim s 4, 8, 15, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Vega (US 20230093462 A1) in view of Werkhoven et al. (US 20030129826 A1) herein after “Werkhoven” . Regarding claim 4, Fig. 1 of Vega discloses the integrated circuit of claim 2 as applied above, but Vega fails to disclose wherein the pure elemental metal of the conductive liner penetrates about 4.5 nm into the dielectric wall. In the similar field of endeavor of integrated circuit manufacturing, Figs. 10-11 of Werkhoven disclose wherein the pure elemental metal of the conductive liner (Fig. 10, “The seed region 436 preferably comprises a highly conductive "elemental" metal”, ¶ [0101]) penetrates about 4.5 nm into the dielectric wall (Fig. 10, barrier region 432, transition region 434, ¶ [0101]) (Werkhoven discloses in Fig. 11 that the material of the conductive liner penetrates the transition region 434 and into the barrier region. Werkhoven further discloses that the transition region is “preferably between about 10 .ANG. and 80 .ANG.”, ¶ [0103]). It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the conductive liner of Vega with the penetrating region as disclosed by Werkhoven, to improve manufacturing quality (see Werkhoven, ¶ [0103]). Regarding claim 8, Figs. 1-2 of Vega disclose the electronic device of claim 1 as applied above, but Vega fails to disclose wherein no carbon, fluorine, or chlorine atoms exist within the conductive liner. In the similar field of endeavor of integrated circuit manufacturing, Figs. 10-11 of Werkhoven disclose wherein no carbon, fluorine, or chlorine atoms exist within the conductive liner (436) (“Advantageously, the process employs an intermediate reduction phase to remove halide tails between metal and nitrogen source phases. This intermediate reduction phase avoids build up of hydrogen halides”, ¶ [0105]). It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the conductive liner of Vega with the material as disclosed by Werkhoven, to improve manufacturing quality of the subsequent metal layer (see Werkhoven, ¶ [0105]) and/or because the use of conventional materials to perform their known function is prima-facie obvious (MPEP 2144.07). Regarding claim 15, Figs. 1-2 of Vega disclose the electronic device of claim 10 as applied above, but Vega fails to disclose wherein no carbon, fluorine, or chlorine atoms exist within the conductive liner. In the similar field of endeavor of integrated circuit manufacturing, Figs. 10-11 of Werkhoven disclose wherein no carbon, fluorine, or chlorine atoms exist within the conductive liner (436) (“Advantageously, the process employs an intermediate reduction phase to remove halide tails between metal and nitrogen source phases. This intermediate reduction phase avoids build up of hydrogen halides”, ¶ [0105]). It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the conductive liner of Vega with the material as disclosed by Werkhoven, to improve manufacturing quality of the subsequent metal layer (see Werkhoven, ¶ [0105]) and/or because the use of conventional materials to perform their known function is prima-facie obvious (MPEP 2144.07). Regarding claim 18, Figs. 1-2 of Vega disclose the electronic device of claim 16 as applied above, but Vega fails to disclose wherein no carbon, fluorine, or chlorine atoms exist within the conductive liner. In the similar field of endeavor of integrated circuit manufacturing, Figs. 10-11 of Werkhoven disclose wherein no carbon, fluorine, or chlorine atoms exist within the conductive liner (436) (“Advantageously, the process employs an intermediate reduction phase to remove halide tails between metal and nitrogen source phases. This intermediate reduction phase avoids build up of hydrogen halides”, ¶ [0105]). It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the conductive liner of Vega with the material as disclosed by Werkhoven, to improve manufacturing quality of the subsequent metal layer (see Werkhoven, ¶ [0105]) and/or because the use of conventional materials to perform their known function is prima-facie obvious (MPEP 2144.07) . 07-21-aia AIA Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Vega (US 20230093462 A1) in view of Ku et al. (US 20230178589 A1) herein after “Ku” . Regarding claim 9, Figs. 1-2 of Vega disclose the electronic device of claim 1 as applied above, but Vega fails to explicitly disclose a printed circuit board comprising the integrated circuit. In the similar field of endeavor of semiconductor structures, Ku discloses a printed circuit board comprising the integrated circuit (“TSV 130 of semiconductor structure 100 is physically and/or electrically connected to …a printed circuit board (PCB)”, ¶ [0046]). It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the structure of Vega by incorporating the printed circuit board as disclosed by Ku. The claimed printed circuit board was known in the prior art and one skilled in the art could have combined the structure of Vega with that of Ku as claimed with no change in their respective functions, and the combination would have yielded the predictable result of creating an electronic device. See KSR International Co. V. Teleflex Inc., 82 USPQ2d 1385 (2007) . 07-21-aia AIA Claim s 7 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Vega (US 20230093462 A1) in view of Yang et al. (US 20140220777 A1) herein after “Yang” . Regarding claim 7, Figs. 1-2 of Vega disclose the electronic device of claim 1 as applied above, but Vega fails to explicitly disclose wherein no oxygen atoms exist at an interface between the conductive liner and the conductive fill. However, the instant application discloses, in ¶ [0014], that the deposition of the conductive liner and conductive fill are performed in-situ such that no oxygen atoms exist at an interface. In the similar field of endeavor of interconnect structures, Fig. 5 of Yang discloses a conductive liner (Fig. 5, diffusion barrier 16, ¶ [0031]) and a conductive fill (Fig. 5, interconnect conductive metal 20, ¶ [0036]) formed without breaking vacuum (“depositing the diffusion barrier 16, the metal liner 18, and performing the reflow anneal without breaking vacuum between these various processing steps”, ¶ [0040]) which “allows for the clean formation of a Cu/liner interface without air exposure”, ¶ [0021]). It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the conductive liner and conductive fill of Vega such that there were no oxygen atoms exist at the interface as disclosed by Yang, to improve the electrical properties of the via structure (see Yang, ¶ [0021]). Regarding claim 14, Figs. 1-2 of Vega disclose the electronic device of claim 10 as applied above, but Vega fails to explicitly disclose wherein no oxygen atoms exist at an interface between the conductive liner and the conductive fill. However, the instant application discloses, in ¶ [0014], that the deposition of the conductive liner and conductive fill are performed in-situ such that no oxygen atoms exist at an interface. In the similar field of endeavor of interconnect structures, Fig. 5 of Yang discloses a conductive liner (16) and a conductive fill (20) formed without breaking vacuum (“depositing the diffusion barrier 16, the metal liner 18, and performing the reflow anneal without breaking vacuum between these various processing steps”, ¶ [0040]) which “allows for the clean formation of a Cu/liner interface without air exposure”, ¶ [0021]). It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the conductive liner and conductive fill of Vega such that there were no oxygen atoms exist at the interface as disclosed by Yang, to improve the electrical properties of the via structure (see Yang, ¶ [0021]) . 07-21-aia AIA Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Vega (US 20230093462 A1) in view of Seo et al. (US 20240178061 A1) herein after “Seo” . Regarding claim 20, Figs. 1-2 of Vega disclose the electronic device of claim 16 as applied above, but Vega fails to disclose wherein the conductive liner has a first thickness on sidewalls of the dielectric structure, and a second thickness on a bottom of the via, the second thickness being at least 2 nm thicker than the first thickness. In the similar field of endeavor of integrated circuit devices, Fig. 2C of Seo discloses wherein the conductive liner (Fig. 2C, second metal liner 192B, ¶ [0057]) has a first thickness on sidewalls of the dielectric structure (Fig. 2C, capping insulating pattern 168, ¶ [0037]), and a second thickness on a bottom of the via (Fig. 2C, second metal plug 196B, ¶ [0057]) (“a portion of the second metal liner 192B, which covers a bottom surface of the second metal plug 196B, may have a greater thickness than a portion of the second metal liner 192B, which covers the sidewalls of the second metal plug 196B”, ¶ [0063]). It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the conductive liner of Vega with the thickness as disclosed by Seo, to obtain the desired electrical properties (see Seo, ¶ [0069-0070]). Seo fails to explicitly disclose the second thickness being at least 2 nm thicker than the first thickness. However, it has been held that where the only different between the prior art and the claims was a recitation of relative dimensions of the claimed element, and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device (MPEP 2144.04). It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention that a mere change in thickness of the conductive liner was within the level of ordinary skill in the art and/or because changes in size and shape are prima facie obvious absent persuasive evidence that the particular configuration is significant (MPEP 2144.04(IV)). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to CORALIE NETTLES whose telephone number is (571)270-5374. The examiner can normally be reached Mon-Fri. 11:30am-7pm ET. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Yara J Green can be reached at (571) 270-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. 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If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /C.A.N./Examiner, Art Unit 2893 /YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893 Application/Control Number: 18/217,208 Page 2 Art Unit: 2893 Application/Control Number: 18/217,208 Page 3 Art Unit: 2893 Application/Control Number: 18/217,208 Page 4 Art Unit: 2893 Application/Control Number: 18/217,208 Page 5 Art Unit: 2893 Application/Control Number: 18/217,208 Page 6 Art Unit: 2893 Application/Control Number: 18/217,208 Page 7 Art Unit: 2893 Application/Control Number: 18/217,208 Page 8 Art Unit: 2893 Application/Control Number: 18/217,208 Page 9 Art Unit: 2893 Application/Control Number: 18/217,208 Page 10 Art Unit: 2893 Application/Control Number: 18/217,208 Page 11 Art Unit: 2893 Application/Control Number: 18/217,208 Page 12 Art Unit: 2893 Application/Control Number: 18/217,208 Page 13 Art Unit: 2893 Application/Control Number: 18/217,208 Page 14 Art Unit: 2893 Application/Control Number: 18/217,208 Page 15 Art Unit: 2893 Application/Control Number: 18/217,208 Page 16 Art Unit: 2893
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