DETAILED ACTION
Election/Restrictions
Applicant's election without traverse of Group I, claims 1 - 16 is acknowledged. Claims 17 – 20 withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected 17 - 20, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 17 – 20.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1 – 3, 14 - 16 is/are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by JUNG et al. (20220223768).
With regard to claim 1, JUNG et al. disclose a display panel (for example, paragraph [0058], see figs. 1, 3), comprising:
an array substrate (an array pixels PX forming in a display device 10, fig. 1 inherently having an array substrate) comprising a base substrate (SUB, fig. 3) and an encapsulation layer (layers IL1, IL2, fig. 3 covering a transistor having a gate G1, functioning as an encapsulation layer) located on a side (a top side) of the base substrate (SUB), wherein a side surface (a top surface) of the encapsulation layer (IL1, IL2) facing away from the base substrate (SUB) is provided with an accommodation groove (referred to as “A1” by examiner’s annotation shown in fig. 3 below); and
a light-emitting unit (ED) located in the accommodation groove (A1), wherein the accommodation groove (A1) is filled with a light-absorbing material (BM),
a protective film (an insulating layer PAS1 functions as a protective film) is formed on both a side surface (a top side surface) of the encapsulation layer (IL1, IL2) facing away from the base substrate (SUB) and a side surface (for example, on a bottom side surface) of the light-emitting unit (ED) facing away from the base substrate (SUB), and an etching rate of the protective film is less than an etching rate of the light-absorbing material under a same etching condition.
Applicant’s claim 1 does not distinguish over JUNG et al. reference regardless of the process used to form the protective film and the light-absorbing material because only the final product is relevant, not the process of making such as “an etching rate of the protective film is less than an etching rate of the light-absorbing material under a same etching condition”.
Note that a "product by process" claim is directed to the product per se, no matter how actually made, In re Hirao, 190 USPQ 15 at 17 (footnote 3). See also In re Brown, 173 USPQ 685; In re Luck, 177 USPQ 523; In re Wertheim, 191 USPQ 90 (209 USPQ 554 does not deal with this issue); In re Fitzgerald, 205 USPQ 594, 596 (CCPA); In re Marosi et al., 218 USPQ 289 (CAFC); and most recently, In re Thorpe et al., 227 USPQ 964 (CAFC, 1985) all of which make it clear that it is the final product per se which must be determined in a "product by process" claim, and not the patentability of the process, and that, as here, an old or obvious product produced by a new method is not patentable as a product, whether claimed in "product by process" claims or not. Note that Applicant has burden of proof in such cases, as the above case law makes clear.
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With regard to claim 2, JUNG et al. disclose the array substrate comprises a light-transmissive region (a region AA1, having a light emitting element ED for emitting the light, functions as a light transmissive region) and a light non-transmissive region (a region AA2, having no light emitting element ED, functions as a light non-transmissive region), and the light non-transmissive region (AA2) comprises a driver circuit region (a region having a driving transistor with the gate G1, and the active layer ACT1); the array substrate further comprises a thin film transistor array layer (the driving transistor structure connected to the light emitting device ED, having the gate G1, and the active layer ACT1 with a small thickness, functions as a thin film transistor array layer) located between the base substrate (SUB) and the encapsulation layer (IL1, IL2), the TFT array layer (the driving transistor structure) in the driver circuit region (the region having a driving transistor with the gate G1) comprises a drive transistor (a drive transistor with the gate G1, and the active layer ACT1), and the TFT array layer in the driver circuit region comprises a height drop (a height drop at the sidewall “SW1” as annotated in fig. 3 below) in a direction perpendicular to the base substrate (SUB) and forms a first side wall (referred to as “SW1” by examiner’s annotation shown in fig. 3 below); and a light-shielding structure (a structure, including a metal layer CAS, functions as a light-shielding structure) is disposed in the array substrate, the light-shielding structure comprises a first light-shielding segment (CAS), and the first light-shielding segment (CAS) covers (covering from the bottom area) at least a part of the first side wall (referred to as “SW1” by examiner’s annotation shown in fig. 3 below) of the TFT array layer (the driving transistor structure connected to the light emitting device ED, having the gate G1, and the active layer ACT1 with a small thickness, functions as a thin film transistor array layer).
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With regard to claim 3, JUNG et al. disclose the first light-shielding segment (CAS) comprises a first side edge (referred to as “CAS1” by examiner’s annotation shown in fig. 3 below) and a second side edge (referred to as “CAS1” by examiner’s annotation shown in fig. 3 below) away from each other in a first direction (X-direction), wherein the first direction (X-direction) is perpendicular to an edge line (a top side surface functioning as an edge line) of a side of the driver circuit region (the region having a driving transistor with the gate G1, and the active layer ACT1) and facing towards the light-transmissive region (AA1) and is parallel to a plane (a top surface plane of the substrate SUSB) where the first side wall (SW1 as shown in fig. 3 above) of the TFT array layer (the driving transistor structure connected to the light emitting device ED, having the gate G1, and the active layer ACT1 with a small thickness, functions as a thin film transistor array layer) is located; and the first side edge (CAS1) extends (extends up) to a side surface (a top surface) of the TFT array layer facing away from the base substrate (SUB), and the second side edge (CAS2) extends (extends down) to the base substrate (SUB).
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With regard to claim 14, JUNG et al. disclose the array substrate comprises a light-transmissive region (a region AA1, having a light emitting element ED for emitting the light, functions as a light transmissive region) and a light non-transmissive region (a region AA2, having no light emitting element ED, functions as a light non-transmissive region) comprises a driver circuit region (a region having a driving transistor with the gate G1, and the active layer ACT1), the array substrate further comprises a TFT array layer (the driving transistor structure connected to the light emitting device ED, having the gate G1, and the active layer ACT1 with a small thickness, functions as a thin film transistor array layer) located between the base substrate (SUB) and the encapsulation layer (IL1, IL2), the TFT array layer in the driver circuit region (the region having a driving transistor with the gate G1) comprises a drive transistor (a drive transistor with the gate G1, and the active layer ACT1) and a drive electrode (an electrode RME1, electrically connected to the drive transistor, functions as a drive electrode), an end of the drive transistor is coupled to the drive electrode (RME1), and the drive electrode (RME1) is exposed (as shown in fig. 3 below) to a side surface of the TFT array layer facing away from the base substrate (SUB); and a plurality of accommodation grooves (referred to as “A11” and “A12” by examiner’s annotation shown in fig. 3 below) are provided, the plurality of accommodation grooves (A11, A12) comprise a first accommodation groove (A11), the light-emitting unit (ED) is located in the first accommodation groove (A11), the first accommodation groove (A11) is filled with the light-absorbing material (BM), the light-emitting unit (ED) is electrically connected to the drive electrode (RME1), and a projection of the drive electrode (RME1) on a plane (a top surface plane) where the base substrate (SUB) is located is located in a projection of the first accommodation groove (A11) on the plane where the base substrate (SUB) is located.
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With regard to claim 15, JUNG et al. disclose the TFT array layer (TFT layer as shown in fig. 3 below) in the driver circuit region (the region having a driving transistor with the gate G1, and the active layer ACT1) comprises a height drop (a height drop at the sidewall “SW1” as annotated in fig. 3 below) in a direction perpendicular to the base substrate (SUB) and forms a first side wall (referred to as “SW1” by examiner’s annotation shown in fig. 3 below); at least a part of a projection of the first side wall (SW1) on the plane (the top surface plane) where the base substrate (SUB) is located is located in the projection of the first accommodation groove (A11) on the plane where the base substrate (SUB) is located; the plurality of accommodation grooves (A11, A12) further comprise a second accommodation groove (A12), and the second accommodation groove (A12) is filled with the light-absorbing material (BM); and the light non-transmissive region (AA2) further comprises a wire region (a region, including a conductive layer CNE1, functions as a wire region), the TFT array layer (the TFT layer as shown in fig. 3 below) in the wire region (the region, including a conductive layer CNE1, functions as a wire region) comprises at least one wire (the conductive layer CNE1 functions as at least one wire), and a projection of the at least one wire (CNE1) on the plane where the base substrate (SUB) is located is located in a projection of the second accommodation groove (A12) on the plane where the base substrate (SUB) is located.
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With regard to claim 16, JUNG et al. disclose a display device comprising a display panel (for example, paragraph [0058], see figs. 1, 3), comprising:
an array substrate (an array pixels PX forming in a display device 10, fig. 1 inherently having an array substrate) comprising a base substrate (SUB, fig. 3) and an encapsulation layer (layers IL1, IL2, fig. 3 covering a transistor having a gate G1, functioning as an encapsulation layer) located on a side (a top side) of the base substrate (SUB), wherein a side surface (a top surface) of the encapsulation layer (IL1, IL2) facing away from the base substrate (SUB) is provided with an accommodation groove (referred to as “A1” by examiner’s annotation shown in fig. 3 below); and
a light-emitting unit (ED) located in the accommodation groove (A1), wherein the accommodation groove (A1) is filled with a light-absorbing material (BM),
a protective film (an insulating layer PAS1 functions as a protective film) is formed on both a side surface (a top side surface) of the encapsulation layer (IL1, IL2) facing away from the base substrate (SUB) and a side surface (for example, on a bottom side surface) of the light-emitting unit (ED) facing away from the base substrate (SUB), and an etching rate of the protective film is less than an etching rate of the light-absorbing material under a same etching condition.
Applicant’s claim 16 does not distinguish over JUNG et al. reference regardless of the process used to form the protective film and the light-absorbing material because only the final product is relevant, not the process of making such as “an etching rate of the protective film is less than an etching rate of the light-absorbing material under a same etching condition”.
Note that a "product by process" claim is directed to the product per se, no matter how actually made, In re Hirao, 190 USPQ 15 at 17 (footnote 3). See also In re Brown, 173 USPQ 685; In re Luck, 177 USPQ 523; In re Wertheim, 191 USPQ 90 (209 USPQ 554 does not deal with this issue); In re Fitzgerald, 205 USPQ 594, 596 (CCPA); In re Marosi et al., 218 USPQ 289 (CAFC); and most recently, In re Thorpe et al., 227 USPQ 964 (CAFC, 1985) all of which make it clear that it is the final product per se which must be determined in a "product by process" claim, and not the patentability of the process, and that, as here, an old or obvious product produced by a new method is not patentable as a product, whether claimed in "product by process" claims or not. Note that Applicant has burden of proof in such cases, as the above case law makes clear.
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Claim Rejections - 35 USC § 103
4. The following is a quotation of 35 U.S.C. 103(a) which forms the basis for all obviousness rejections set forth in this Office action:
(a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102 of this title, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negatived by the manner in which the invention was made.
Claim 12 is rejected under 35 U.S.C. 103(a) as being unpatentable over JUNG et al. (20220223768).
With regard to claim 12, JUNG et al. disclose a sectional shape of the accommodation groove (V1) on a second plane (a bottom or top surface plane of the substrate SUB functioning as a second plane) comprises a bottom edge (a bottom surface of the groove V1) and two side edges (two sidewall surfaces of the groove V1), wherein the bottom edge (a bottom surface of the groove V1) is an edge of the sectional shape close to the base substrate (SUB), and the two side edges (two sidewall surfaces of the groove V1) are connected to the bottom edge (the bottom surface of the groove V1), respectively; and Fig. 3 of JUNG et al. appears to disclose an included angle (referred to as “V1” by examiner’s annotation shown in fig. 3 below) formed by an intersection of an extension line (referred to as “E1” by examiner’s annotation shown in fig. 3 below) of a side edge (sidewall) of the side edges (sidewalls) and an extension line (referred to as “E2” by examiner’s annotation shown in fig. 3 below) of the bottom edge (the bottom surface) and facing towards the accommodation groove (A1) about 110° as shown in fig. 3 in order to enhance a high light emitting efficiency of the device. However, since the patent drawings are not labeled as “to scale,” one cannot be certain that the included angle formed by an intersection of an extension line of a side edge of the side edges and an extension line of the bottom edge and facing towards the accommodation groove about 110° as seemingly shown [see MPEP 2125].
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It would have been obvious to one having ordinary skill in the art at the time of the claimed invention to form the included angle formed by an intersection of an extension line of a side edge of the side edges and an extension line of the bottom edge and facing towards the accommodation groove about 110°, because Fig. 3 suggests an included angle (referred to as “V1” by examiner’s annotation shown in fig. 3 above) formed by an intersection of an extension line (referred to as “E1” by examiner’s annotation shown in fig. 3 above) of a side edge (sidewall) of the side edges (sidewalls) and an extension line (referred to as “E2” by examiner’s annotation shown in fig. 3 above) of the bottom edge (the bottom surface) and facing towards the accommodation groove (A1) about 110° and a prima facie case of obviousness exists where device dimensions of the prior art are such that one of ordinary skill in the art would have expected them to have the same performance {MPEP 2144.04(IV)(A)}
Allowable Subject Matter
6. Claims 4 – 11, 13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 4 – 6 are allowable over the prior art of record, because none of these references disclose or can be combined to yield the claimed invention such as the TFT array layer comprises a planarization layer, and a side surface of the planarization layer facing away from the base substrate is provided with a groove; the array substrate further comprises a transition region located between the driver circuit region and the light-transmissive region, and a projection of the groove on a plane where the base substrate is located is located in the transition region; and the first side wall of the TFT array layer is also used as an inner wall of the groove, and the groove is filled with a part of the first light-shielding segment as recited in claim 4.
Claims 7 – 11 are allowable over the prior art of record, because none of these references disclose or can be combined to yield the claimed invention such as the light-shielding structure further comprises a second light-shielding segment, the second light-shielding segment is located on a side of the TFT array layer facing away from the base substrate, and a projection of the second light-shielding segment on the plane where the base substrate is located at least partially overlaps with and at most partially overlaps with a projection of the drive electrode on the plane where the base substrate is located; and the light-shielding structure comprises an electrode opening, and a projection of the electrode opening on the plane where the base substrate is located at least partially overlaps with the projection of the drive electrode on the plane where the base substrate is located as recited in claim 7.
Claim 13 is allowable over the prior art of record, because none of these references disclose or can be combined to yield the claimed invention such as an included angle, which is formed by an intersection of an extension line of a side edge and an extension line of a bottom edge in an accommodation groove where the second color light-emitting unit is located and faces towards the accommodation groove where the second color light-emitting unit is located, is a second included angle; in a case where the included angle formed by the intersection of the extension line of the side edge and the extension line of the bottom edge and facing towards the accommodation groove is less than or greater than 90°, the first included angle is greater than the second included angle; and in a case where the included angle formed by the intersection of the extension line of the side edge and the extension line of the bottom edge and facing towards the accommodation groove is equal to 90°, a distance between the side edge in the accommodation groove where the first color light-emitting unit is located and the first color light-emitting unit is greater than a distance between the side edge in the accommodation groove where the second color light-emitting unit is located and the second color light-emitting unit as recited in claim 13.
Conclusion
7. Any inquiry concerning this communication or earlier communications from the examiner should be directed to TAN N TRAN whose telephone number is (571) 272 - 1923. The examiner can normally be reached on 8:30-5:00PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached on (571) 272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TAN N TRAN/
Primary Examiner, Art Unit 2812
Prosecution Insights