DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I (claims 1–15) in the reply filed on December 9, 2025 is acknowledged. Claims 16-23 withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2, 7-8, 12-13, and 15 are rejected under 35 U.S.C. 102(a)(1) as being clearly anticipated by Kawabata; Kenichi (US 2018/0138131; hereinafter Kawabata).
Regarding claim 1, Kawabata discloses a semiconductor package (in particular example, Fig 20; ¶ [0126]; entire document) comprising:
a substrate (20; Fig 20; ¶ [0069]);
a semiconductor die (20; Fig 20; ¶ [0067-69]);
metal interconnects (24; Fig 20; ¶ [0069]), the semiconductor die being mounted to the substrate via the metal interconnects;
an inductor (coil 32; Fig 20; ¶ [0069]) mounted to the substrate;
a magnetic material (40; Figs 6,20; ¶ [0071,0079-94]) encapsulating the semiconductor die, the inductor, and the metal interconnects, the magnetic material including metal particles (5; Fig 6; ¶ [0081,0083-84]) suspended in a first insulation material (4; Fig 6; ¶ [0081-82]); and
a second insulation material (70; Fig 20; ¶ [0126]) covering the magnetic material, wherein the second insulation material is substantially free of metal particles (70 is described as an insulating film with no mention of metal particles, in contrast to the detailed description {including Fig 6 and associated text} of metal particles included in the first insulating film; in addition, 70 is described as being able to increase a surface resistivity which has been reduced because of the metal particles (5) being cut through and exposed by dicing; ¶ [0125-126]).
Regarding claim 2, Kawabata discloses the semiconductor package of claim 1, wherein the first insulation material (4; Fig 6) includes an epoxy resin (¶ [0081-82]).
Regarding claim 7, Kawabata discloses the semiconductor package of claim 1, wherein the metal particles (5; Fig 6) are coated with a third insulation material (7; Fig 6; ¶ [0088]).
Regarding claim 8, Kawabata discloses the semiconductor package of claim 7, wherein the third insulation material (7; Fig 6) includes one of a group consisting of: a silicon oxide material (formation of a silicon oxide coating film; ¶ [0088]); and a phosphate material.
Regarding claim 12, Kawabata discloses the semiconductor package of claim 1, wherein the metal interconnects (24; Fig 20; ¶ [0069]) are first metal interconnects, and the substrate (20; Fig 20) includes:
first metal pads (23; Fig. 20; ¶ [0070]) on a first side (21; Fig. 20; ¶ [0069]) of the substrate, the first metal pads coupled to the first metal interconnects and to the inductor (32; Fig 20);
second metal pads (26; Fig. 20; ¶ [0070]) on a second side (22; Fig. 20; ¶ [0069]) of the substrate opposite to the first side;
an insulation layer (20 can be one of various insulators; ¶ [0069]) between the first side and the second side; and
second metal interconnects (25; Fig. 20; ¶ [0070]) in the insulation layer and coupled between the first metal pads and the second metal pads (¶ [0070]).
Regarding claim 13, Kawabata discloses the semiconductor package of claim 12, wherein:
the first metal pads (23; Fig. 20) and the second metal interconnects (25; Fig. 20) include a copper metal (¶ [0070]);
the second metal pads (26; Fig. 20) include at least one of a palladium metal or a silver metal (¶ [0070]); and
the insulation layer (20; Fig 20) includes at least one of: a polymer material (thermoplastic resin; ¶ [0069]), an Ajinomoto Build-up Film, or a ceramic material.
Regarding claim 15, Kawabata discloses the semiconductor package of claim 1, wherein the substrate (20; Fig 20) is a routable leadframe (including internal wirings 25; Fig 20; ¶ [0070]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3-4 are rejected under 35 U.S.C. 103 as being unpatentable over Kawabata; Kenichi (US 2018/0138131; hereinafter Kawabata) in view of Chen; Hsien-Wei et al. (US 12500127; hereinafter Chen).
Regarding claim 3, Kawabata discloses the semiconductor package of claim 1, but does not disclose wherein the second insulation material is a deposition.
In the same field of endeavor, Chen discloses a semiconductor package comprising an insulation material (510a, including polyimide; Fig 5C; Col 10, lines 27-39) which encapsulates a semiconductor device (300; Fig 5C) wherein the insulation material is a deposition. Accordingly, it would have been obvious to a person having ordinary skill in the art that the second insulation material of Kawabata may be a deposition. One may have been motivated to come to this conclusion, with a reasonable expectation of success, because deposition is a well-known method of forming an insulation material in the art.
Regarding claim 4, Kawabata in view of Chen discloses the semiconductor package of claim 3, wherein the deposition selected from a group consisting of: a parylene; a glass; a polyimide; a cured epoxy resin; a silicone-based compound; a maleimide imide resin; and a fluoropolymer (as applied to claim 3).
Claims 5-6 are rejected under 35 U.S.C. 103 as being unpatentable over Kawabata; Kenichi (US 2018/0138131; hereinafter Kawabata) in view of Costa; Julio C. et al. (US 2021/0134699; hereinafter Sato)
Regarding claim 5, Kawabata discloses the semiconductor package of claim 1, but does not disclose wherein the second insulation material is an overmold.
In the same field of endeavor, Costa discloses a semiconductor package (10A; Fig 2) comprising an encapsulated semiconductor die (mold device 12; Fig 2; ¶ [0058,0043-57]) on a substrate (18; Fig 2; ¶ [0056]); and a second encapsulation material (60, comprising insulating material epoxy resin; Fig 2; ¶ [0058,0089]) over the encapsulated semiconductor die, wherein the second encapsulation material is an overmold (overmolding; Fig 19; ¶ [0089]).
Accordingly, it would have been obvious to a person having ordinary skill in the art to have used an overmold for the second insulation layer of Kawabata in the same manner as Costa has used the second encapsulation material 60 over the mold device 12. One would have been motivated to do this as a means to form the insulating film 70 of Kawabata, since Kawabata is silent on the method of formation (Kawabata; ¶ [0126]). One would have had a reasonable expectation of success because of the similar encapsulated die structures of Kawabata and Costa.
Regarding claim 6, Kawabata in view of Costa discloses the semiconductor package of claim 5, wherein the second insulation material includes an epoxy resin (as applied to claim 5).
Claims 9-11 are rejected under 35 U.S.C. 103 as being unpatentable over Kawabata; Kenichi (US 2018/0138131; hereinafter Kawabata) in view of Sato; Yuki et al. (US 2021/0343662; hereinafter Sato)
Regarding claim 9, Kawabata discloses the semiconductor package of claim 1, but does not disclose wherein the inductor includes a coil portion and a stilt portion, the stilt portion coupled to the substrate.
In the same field of endeavor, Sato discloses a semiconductor package comprising an inductor (810,812,822,830; Figs 8-9; ¶ [0035]), wherein the inductor includes a coil portion (810,812; Figs 8-9; ¶ [0035]) and a stilt portion (822,830; Figs 8-9; ¶ [0035]), the stilt portion coupled to a substrate (802, through 806,808; Figs 8-9; ¶ [0035]).
Accordingly, it would have been obvious to a person having ordinary skill in the art to combine the inductor structure including a coil portion and a stilt portion of Sato with the semiconductor package of Kawabata. One would have been motivated to do this in order to fit the inductor over another semiconductor component (Sato; 804; Figs 8-9; ¶ [0034]) on the substrate and thereby produce a semiconductor package having a smaller footprint (Sato; Figs 8-9; ¶ [0017-18]) as compared to the semiconductor package of Kawabata having the inductor laterally adjacent to another semiconductor component (Kawabata; Fig 20). One would have had a reasonable expectation of success because of the similar component types and packages, well-known in the art.
Regarding claim 10, Kawabata in view of Sato discloses the semiconductor package of claim 9, wherein the coil portion (Sato; 810,812; Figs 8-9) is over the semiconductor die (Sato; 804; Figs 8-9; as described for claim 9).
Regarding claim 11, Kawabata in view of Sato discloses the semiconductor package of claim 9, further comprising a capacitor encapsulated in the magnetic material, wherein the coil portion is over the capacitor (Sato; 804 may include a capacitor along with additional components; ¶ [0034]).
Claims 14 is rejected under 35 U.S.C. 103 as being unpatentable over Kawabata; Kenichi (US 2018/0138131; hereinafter Kawabata) in view of Albers; Sven et al. (US 2016/0358897; hereinafter Albers).
Regarding claim 14, Kawabata discloses the semiconductor package of claim 13, but does not disclose further comprising a solder resist layer on the second side (22; Fig. 20).
In the same field of endeavor, Albers discloses a similar semiconductor package (100; Fig 6; ¶ [0028]) comprising a solder resist layer (solder stop 180; Fig 6; ¶ [0033]) on a second side. Accordingly, it would have been obvious to a person having ordinary skill in the art to have included a solder resist layer on the second side of the semiconductor package of Kawabata. One would have been motived to do this in order to prevent shorting of solder connections between the second metal pads (Kawabata; 26; Fig. 20) when connecting the package externally, and would have had a reasonable expectation of success because using solder resist for this purpose is well-known the art.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Lee; Wei-Hsuan et al. (US 2016/0358862; the prior art discloses a semiconductor package having a first ferrimagnetic mold layer encapsulating electronic components, and a second ferrimagnetic mold layer encapsulating the first ferrimagnetic mold layer).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRAD KNUDSON whose telephone number is (703)756-4582. The examiner can normally be reached Telework 9:30 -18:30 ET; M-F.
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/B.A.K./Examiner, Art Unit 2817
/ELISEO RAMOS FELICIANO/Supervisory Patent Examiner, Art Unit 2817