DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The Amendment filed June 1, 2026 has been entered. Claims 1-15 and newly added claims 24-42 are pending in the application.
Response to Arguments
Applicant’s arguments, see pages 9-29, filed June 1, 2026, with respect to the rejection(s) of claim(s) 1-15 have been fully considered in view of the Amendment and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of a combination of previously cited references. Please see the claim rejections below.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claim 33, depending from claim 24, recites the limitation "wherein the metal particles are coated with a third insulation material”. There is insufficient antecedent basis for this limitation in the claim. For the purposes of examination, the claim will be interpreted as depending from claim 25.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 24-26, 28, 32-39 and 41-42 are rejected under 35 U.S.C. 103 as being unpatentable over Kawabata; Kenichi (US 2018/0138131; hereinafter Kawabata) in view of Sato; Yuki et al. (US 2021/0343662; hereinafter Sato).
Regarding claim 24, Kawabata discloses a semiconductor package (in particular example, Fig 20; ¶ [0126]; entire document) comprising:
a substrate (20; Fig 20; ¶ [0069]);
a semiconductor die (31; Fig 20; ¶ [0067-69]);
metal interconnects (24; Fig 20; ¶ [0069]), the semiconductor die being mounted to the substrate via the metal interconnects;
an inductor (coil 32; Fig 20; ¶ [0069]) mounted to the substrate and spaced horizontally from the semiconductor die;
a second semiconductor die (more electronic components are incorporated, besides 31,32 shown; ¶ [0068]); and
an insulating material (40, comprising 4 {¶ [0080-81}; Figs 6,20; ¶ [0071,0079-94]) encapsulating the semiconductor die, the inductor, the metal interconnects.
Kawabata does not disclose the second semiconductor die is vertically spaced between coils of the inductor and the substrate, the second semiconductor die being mounted to the substrate via second metal interconnects; and the insulating material encapsulating the second semiconductor die, and the second metal interconnects.
In the same field of endeavor, Sato discloses a semiconductor package comprising an inductor (810,812,814,822,830; Figs 8-9; ¶ [0035]) and a semiconductor die (804; Figs 8-9; ¶ [0034]) vertically spaced between coils of the inductor and a substrate (802; Figs 8-9; ¶ [0034]), the semiconductor die being mounted to the substrate via metal interconnects (806,808; Figs 8-9; ¶ [0034-35]), wherein an insulating material (834; Figs 8-9; ¶ [0036]) encapsulates the semiconductor die, the inductor, and the metal interconnects.
Accordingly, it would have been obvious to a person having ordinary skill in the art to combine the disclosure of Sato with that of Kawabata by substituting the structure of Sato for the inductor and second semiconductor die of Kawabata. One may have been motivated to consider a variety of configurations because Kawabata is silent in regards to the configuration of the additional electronic components (Kawabata; ¶ [0068]). One may have been motivated to select the structure of Sato in order to minimize a profile and reduce a footprint of a semiconductor package vs. spacing a second semiconductor die laterally adjacent to an inductor (Sato; Figs 8-9; ¶ [0017-18]), which is an on-going goal (miniaturization) in the industry. One may have had a reasonable expectation of success because of the similar components included in the similar magnetic mold semiconductor packages of Kawabata and Sato.
Regarding claim 25, Kawabata in view of Sato discloses the semiconductor package of claim 24, wherein the insulating material is a magnetic material (Kawabata; 40; Figs 6,20; ¶ [0071,0079-94]) including metal particles (Kawabata; 5; Fig 6; ¶ [0081,0083-84]) suspended in a first insulation material (Kawabata; 4; Fig 6; ¶ [0081-82]).
Regarding claim 26, Kawabata in view of Sato discloses the semiconductor package of claim 24, further including a second insulation material (Kawabata; 70; Fig 20; ¶ [0126]) covering the magnetic material, wherein the second insulation material is substantially free of metal particles (70 is described as a thin insulating film with no mention of metal particles, in contrast to the detailed description {including Fig 6 and associated text} of metal particles included in the first insulating film.)
Regarding claim 28, Kawabata in view of Sato discloses the semiconductor package of claim 25, wherein the insulation material (Kawabata; 4; Fig 6) includes an epoxy resin (Kawabata; ¶ [0081-82]).
Regarding claim 32, Kawabata in view of Sato discloses the semiconductor package of claim 26, but does not disclose wherein the second insulation material includes an epoxy resin (Kawabata; 70; Fig 20; Kawabata is silent in regards to material); however, it would have been obvious to a person having ordinary skill in the art that this may be the case because epoxy resin is well-known and commonly used as a packaging insulation material in the art, and is disclosed by Kawabata for other elements of the semiconductor package of claim 26 (for example, for example for the first insulation material 4). One may have been motivated to use epoxy resin for manufacturing reasons of convenience and/or cost, since the same material is already used in the semiconductor package, and would have had a reasonable expectation of success for the same reason, and because the material is well-known in the art.
Regarding claim 33, Kawabata in view of Sato discloses the semiconductor package of claim 25, wherein the metal particles (Kawabata; 5; Fig 6) are coated with a third insulation material (Kawabata; 7; Fig 6; ¶ [0088]).
Regarding claim 34, Kawabata in view of Sato discloses the semiconductor package of claim 33, wherein the third insulation material (Kawabata; 7; Fig 6) includes one of a group consisting of: a silicon oxide material (Kawabata; formation of a silicon oxide coating film; ¶ [0088]); and a phosphate material.
Regarding claim 35, Kawabata in view of Sato discloses the semiconductor package of claim 24, wherein the inductor (Sato; 810,812,814,822,830), includes a coil portion (Sato; 810,812; Figs 8-9; ¶ [0035]) and a stilt portion (Sato; 822,830; Figs 8-9; ¶ [0035]), the stilt portion coupled to the substrate (Sato; 802, through 806,808; Figs 8-9; ¶ [0035]; as applied to claim 24).
Regarding claim 36, Kawabata in view of Sato discloses the semiconductor package of claim 35, wherein the coil portion (Sato; 810,812; Figs 8-9) is over the semiconductor die (Sato; 804; Figs 8-9; as applied to claim 24).
Regarding claim 37, Kawabata in view of Sato discloses the semiconductor package of claim 24, further comprising a capacitor encapsulated in the magnetic material, wherein the coil portion is over the capacitor (Sato; 804 may include a capacitor along with additional components; ¶ [0034]; Kawabata; more electronic components…such as a capacitor ; ¶ [0068-69]); as applied to claim 24).
Regarding claim 38, Kawabata in view of Sato discloses the semiconductor package of claim 24, wherein substrate (Kawabata; 20; Fig 20) includes:
first metal pads (Kawabata; 23; Fig. 20; ¶ [0070]) on a first side (Kawabata; 21; Fig. 20; ¶ [0069]) of the substrate, the first metal pads coupled to the first metal interconnects (Kawabata; 24; Fig 20; ¶ [0069]), the second metal interconnects (Sato; 806,808; Figs 8-9; as applied to claim 24), and to the inductor (as applied to claim 24);
second metal pads (Kawabata; 26; Fig. 20; ¶ [0070]) on a second side (Kawabata; 22; Fig. 20; ¶ [0069]) of the substrate opposite to the first side;
an insulation layer (Kawabata; 20 can be one of various insulators; ¶ [0069]) between the first side and the second side; and
second metal interconnects (Kawabata; 25; Fig. 20; ¶ [0070]) in the insulation layer and coupled between the first metal pads and the second metal pads (¶ [0070]).
Regarding claim 39, Kawabata in view of Sato discloses the semiconductor package of claim 38, wherein:
the first metal pads (Kawabata; 23; Fig. 20) and the second metal interconnects (Kawabata; 25; Fig. 20) include a copper metal (Kawabata; ¶ [0070]);
the second metal pads (Kawabata; 26; Fig. 20) include at least one of a palladium metal or a silver metal (Kawabata; ¶ [0070]); and
the insulation layer (Kawabata; 20; Fig 20) includes at least one of: a polymer material (Kawabata; thermoplastic resin; ¶ [0069]), an Ajinomoto Build-up Film, or a ceramic material.
Regarding claim 41, Kawabata in view of Sato discloses the semiconductor package of claim 24, wherein the substrate (Kawabata; 20; Fig 20) is a routable leadframe (Kawabata; including internal wirings 25; Fig 20; ¶ [0070]).
Regarding claim 42, Kawabata discloses a semiconductor package (in particular example, Fig 20; ¶ [0126]; entire document) comprising:
a substrate (20; Fig 20; ¶ [0069]);
a semiconductor die (31; Fig 20; ¶ [0067-69]);
metal interconnects (24; Fig 20; ¶ [0069]), the semiconductor die being mounted to the substrate via the metal interconnects;
an inductor (coil 32; Fig 20; ¶ [0069]) mounted to the substrate and spaced horizontally from the semiconductor die;
a capacitor (more electronic components {¶ [0002]} are incorporated, besides 31,32 shown; ¶ [0068]; and, the electronic components may be passive components such as a capacitor; ¶ [0067,0002])); and
an insulating material (40, comprising 4 {¶ [0080-81}; Figs 6,20; ¶ [0071,0079-94]) encapsulating the semiconductor die, the inductor, the metal interconnects.
Kawabata does not disclose the capacitor is vertically spaced between coils of the inductor and the substrate, the capacitor being mounted to the substrate via second metal interconnects; and the insulating material encapsulating the capacitor, and the second metal interconnects.
In the same field of endeavor, Sato discloses a semiconductor package comprising an inductor (810,812,814,822,830; Figs 8-9; ¶ [0035]) and a capacitor (804; Figs 8-9; ¶ [0034]) vertically spaced between coils of the inductor and a substrate (802; Figs 8-9; ¶ [0034]), the capacitor being mounted to the substrate via metal interconnects (806,808; Figs 8-9; ¶ [0034-35]), wherein an insulating material (834; Figs 8-9; ¶ [0036]) encapsulates the capacitor, the inductor, and the metal interconnects.
Accordingly, it would have been obvious to a person having ordinary skill in the art to combine the disclosure of Sato with that of Kawabata by substituting the structure of Sato for the inductor and capacitor of Kawabata. One may have been motivated to consider a variety of configurations because Kawabata is silent in regards to the configuration of the additional electronic components (Kawabata; ¶ [0068]). One may have been motivated to select the structure of Sato in order to minimize a profile and reduce a footprint of a semiconductor package vs. spacing a capacitor laterally adjacent to an inductor (Sato; Figs 8-9; ¶ [0017-18]), which is an on-going goal (miniaturization) in the industry. One may have had a reasonable expectation of success because of the similar components included in the similar magnetic mold semiconductor packages of Kawabata and Sato.
Claim 40 is rejected under 35 U.S.C. 103 as being unpatentable over Kawabata; Kenichi (US 2018/0138131; hereinafter Kawabata) in view of Sato; Yuki et al. (US 2021/0343662; hereinafter Sato) and further in view of Albers; Sven et al. (US 2016/0358897; hereinafter Albers).
Regarding claim , Kawabata in view of Sato discloses the semiconductor package of claim 39, but does not disclose further comprising a solder resist layer on the second side (Kawabata; 22; Fig. 20).
In the same field of endeavor, Albers discloses a similar semiconductor package (100; Fig 6; ¶ [0028]) comprising a solder resist layer (solder stop 180; Fig 6; ¶ [0033]) on a second side. Accordingly, it would have been obvious to a person having ordinary skill in the art to have included a solder resist layer on the second side of the semiconductor package of Kawabata. One would have been motived to do this in order to prevent shorting of solder connections between the second metal pads (Kawabata; 26; Fig. 20) when connecting the package externally, as is known in the art, and would have had a reasonable expectation of success because using solder resist for this purpose is well-known the art.
Allowable Subject Matter
Claims 1-15 allowed.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 1, the prior art of record, either singularly or in combination, does not disclose or suggest the combination of limitations including “a second insulation material covering the magnetic material, wherein the second insulation material is substantially free of metal particles and is an outermost surface of the semiconductor package”.
Claims 27, 29-31 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 27, the prior art of record, either singularly or in combination, does not disclose or suggest the combination of limitations including “wherein the second insulation material is an outermost surface of the semiconductor package”, in combination with the additional limitations of the intervening claims.
Regarding claim 31, the prior art of record, either singularly or in combination, does not disclose or suggest the combination of limitations including “wherein the second insulation material is an overmold”, in combination with the additional limitations of the intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Bhushan; Bharat et al. (US 2016/0359100; the prior art discloses a semiconductor package comprising a magnetic shield structure encapsulating a magnetic random access memory {MRAM} die (¶ [0061]) and an encapsulation layer, such as an epoxy based material, encapsulating the magnetic shield structure encapsulation and the MRAM die (¶ [0062]);
Lee; Wei-Hsuan et al. (US 2016/0358862; the prior art discloses a semiconductor package having a first ferrimagnetic mold layer encapsulating electronic components, and a second ferrimagnetic mold layer encapsulating the first ferrimagnetic mold layer);
Liao; Wen-Shiang et al. (US 2018/0315706; the prior art discloses a first semiconductor die, a second semiconductor die vertically spaced between upper and lower portions of an inductor coil, a molding material encapsulating the first and second semiconductor die and vias which connect the upper and lower portions, and an insulating layer covering the molding material).
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRAD KNUDSON whose telephone number is (703)756-4582. The examiner can normally be reached Telework 9:30 -18:30 ET; M-F.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos Feliciano can be reached at 571-272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/B.A.K./Examiner, Art Unit 2817
/ELISEO RAMOS FELICIANO/Supervisory Patent Examiner, Art Unit 2817
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