Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species I in the reply filed on 12/22/2025 is acknowledged. Claims 16-20 are withdrawn as drawn to an unelected species. Additionally, Examiner is withdrawing Claim 12 as being drawn to unelected Species III. Note that the specification makes clear, both in Fig. 4 and Para. [0083]), that the Species III is unlike Species I due to the presence of the molding layers.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 9 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 9 states in part “…wherein a connection pad disposed on an upper surface of the interconnection region is contact with either of a lower surface of the first front pad or a lower surface of the first rear pad,” and “wherein the connection pad is in contact with either of a lower surface fo the second front pad or a lower surface of the second rear pad…”. Since it is clear from the Figures that the same connection pad can’t be in contact with the first and second pads of the first and second semiconductor devices, Examiner is assuming that the connection pads recited in this claim are all different.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 5-7, 9, 11, and 14 are rejected under 35 U.S.C. 103 as being unpatentable over US20160358899A1 (Jae Sik Lee) in view of US20120193779A1 (Chung-Sun Lee)
Regarding Claim 1, Jae Sik Lee discloses a semiconductor package (Fig. 1, el. 100, Para. [0024]), comprising: a substrate (Fig. 1, els. 120 and 114, Para. [0033]); a first lower semiconductor die (Fig. 1, el. 106, Para. [0032]) comprising a first front pad (Fig. 1, el. 190, Para. 0032]), a first circuit region (Para. [0026]); a second lower semiconductor die (Fig. 1, el. 104, Para. [0024]) comprising a second front pad (Fig. 1, el. 186, Para. [0032]), a second circuit region (Para. [0025]), an interposer (Fig. 1, Para. [0024]) comprising a third front pad (Fig. 1, el. 178, Para. [0029]) and a third rear pad (Fig. 1, el. 172, Para. [0028]), opposing each other (Fig. 1), and a third lower through-via (Fig. 1, el. 176, Para. [0029]) electrically connecting the third front pad and the third rear pad to each other (Fig. 1, Para. [0029]), wherein the interposer is disposed between the first lower semiconductor die and the second lower semiconductor die (Para. [0024]) so that the third front pad or the third rear pad faces in the upward direction (in this case, the third rear pad 172 would face in the upward direction – see Fig. 1), and is disposed on the substrate; an upper chip (Fig. 1, el. 102, Para. [0024]) disposed on the first lower semiconductor die, the second lower semiconductor die, and the interposer (Fig. 1, Para. [0028])), wherein the upper chip includes first connection pads (Fig. 1, el. 170, Para. [0028]) in contact with the third front pad or the third rear pad facing in the upward direction (Para. [0028]).
Jae Sik Lee does not disclose that the first semiconductor die, the second semiconductor die, and the interposer are separate chips, does not disclose that the first semiconductor die and the second semiconductor die each have a lower through via electrically connecting the rear pad to n integrated circuit of the circuit region, where the integrated circuit is electrically connected to the front pad, and does not disclose that the first semiconductor die and the second semiconductor die have rear pads that connect to the first connection pads of the upper chip.
Chung-Sun Lee discloses a semiconductor package (Figs. 1-3, el. 300, Para [0047]), with a lower semiconductor chip (Fig. 2, el. 10, Para. [0047]), an upper semiconductor chip (Fig. 2, el. 20, Para. [0047],) where the lower semiconductor chip has a rear pad (Fig. 3, el. 25, Para. [Para. [0052]), a front pad (Fig. 3, el. 15, Para. [0052]), where the rear pad and front pad oppose each other (Fig. 3), a circuit region (Fig. 3, el. 11a, Para. [0050]) that is disposed between the front pad and the rear pad (Fig. 3) and that contains an integrated circuit (Fig. 3, el. 111, Para. [0050]), a through via (Fig. 2, el. 12, Para. [0049]) electrically connecting the rear pad to the first integrated circuit (Fig. 3, Para. [0052]), and the integrated circuit is electrically connected to the front pad (Fig. 3, Para. [0052]).
First, it would have been obvious to one skilled in the art before the effective filing date of the
claimed invention to take the first and second semiconductor dies and the interposer of Jae Sik Lee and make them into separate chips. Doing so would have the benefit of protecting each of the dies and interposers from the environment.
Second, it would have been obvious to use the structure disclosed by Chung-Sun Lee in the first and second semiconductor dies of Jae Sik Lee. Placing the active side of the chip so that the interconnections is at the bottom allows for ease of routing, and using a through via to connect the integrated circuit allows for interconnection to the top, which is necessary in a stacked package structure as disclosed by both Jae Sik Lee and Chung-Sun Lee.
2. Regarding Claim 2, Jae Sik Lee in view of Chung-Sun Lee discloses the semiconductor package of claim 1, wherein the first lower semiconductor chip is disposed so that the first rear pad faces in the upward direction, and the upper chip is electrically connected to the first integrated circuit through the first rear pad and the first lower through-via (see analysis of claim 1), and
the second lower semiconductor chip is disposed so that the second rear pad faces in the upward direction, and the upper chip is electrically connected to the second integrated circuit through the second rear pad and the second lower through-via (see analysis of claim 1)
3. Regarding Claim 3, Jae Sik Lee in view of Chung-Sun Lee discloses the semiconductor package of claim 1, wherein the upper chip is configured to overlap at least a portion of each of the first lower semiconductor chip, the second lower semiconductor chip, and the interposer chip in a direction substantially perpendicular to an upper surface of the substrate (see Jae Sik Lee, Fig. 1).
4. Regarding Claim 5, Jae Sik Lee in view of Chung-Sun Lee, discloses the semiconductor package of claim 1, wherein the substrate comprises an interconnection structure (Jae Sik Lee, Fig. 1, el. 114, Paras. [0032] and [0033]), and wherein the upper chip is electrically connected to the interconnection structure through the third lower through via of the interposer chip (Fig. 1, Para. [0034]).
5. Regarding Claim 6, Jae Sik Lee in view of Chung-Sun Lee discloses the semiconductor package of Claim 1, wherein the substrate comprises an interconnection structure (Jae Sik Lee, Fig. 1, el. 114, Para. [0032] and [0033]), wherein either of the first front pad of the first rear pad, not contacting the first connection pads is electrically connected to the interconnection structure, and wherein either of the second front pad of the second rear pad, not contacting the first connection pads is electrically connected to the interconnection structure (Jae Sik Lee, Fig. 1, Para. [0032], where some of the front pads of the first and second dies only connect to the interconnection structure and not the upper chip).
6. Regarding claim 7, Jae Sik Lee in view of Chung-Sun Lee discloses the semiconductor package of claim 1, wherein the interposer chip does not comprise an active element (Jae Sik Lee, Para. [0029], which describes the structure of the interposer which only includes copper filled vias).
7. Regarding Claim 9, Jae Sik Lee in view of Chung-Sun Lee discloses the semiconductor package of Claim 1, wherein the substrate comprises an interconnection structure (Jae Sik Lee, Fig. 1, el. 182, Para. [0031]) and an interconnection region (Jae Sik Lee, Fig. 1, el. 120, Para. [0033]) including the interconnection structure (Jae Sik Lee, Fig. 1), wherein a connection pad disposed on an upper surface of the interconnection region is in contact with a lower surface of the first front pad (Jae Sik Lee, El. 184, Para. [0031]), wherein the connection pad is in contact with a lower surface of the second front pad (Fig. 1, Para. [0031]), and wherein the connection pad is in contact with a lower surface of the third front pad (Fig. 1, Para. [0031]).
8. Regarding Claim 11, Jae Sik Lee in view of Chung-Sun Lee discloses the semiconductor package of claim 1, wherein an upper surface of each of the first lower semiconductor chip, the second lower semiconductor chip, and the interposer chip is disposed at substantially the same level as one another (Jae Sik Lee, Fig. 1 – where the upper surface of the dies and interposer are disposed at the same level as one another).
9. Regarding Claim 14, Jae Sik Lee in view of Chung-Sun Lee discloses the semiconductor package of claim 1, wherein the substrate comprises: a substrate body (Jae Sik Lee, Fig. 1, el. 120, Para. [0033]) having a first surface (the bottom surface can be taken as the first surface), and a second surface (the top surface can be taken as the second surface), opposite to the first surface; an interconnection region (Jae Sik Lee, Fig. 1, el. 114, Para. [0033]) including an interconnection structure (Jae Sik Lee, Fig. 1, el. 182, Para. 0034]) disposed on the second surface of the substrate (Jae Sik Lee, Fig. 1, Para. [0033]); and a substrate through-via (Jae Sik Lee, Fig. 1, el. 194, Para. [0033]) penetrating through the substrate body (Fig. 1, Para. [0033]) and electrically connecting a lower connection bump (Fig. 1, el. 198, Para. [0033]) disposed on the first surface of the substrate body to the interconnection structure (see Fig. 1, where the two vias in the middle of the substrate 120 connect the lower connection bump to the interconnection structure), and wherein the first lower semiconductor chip, the second lower semiconductor clhip, and the interposer chip are disposed on the interconnection region (Jae Sik Lee, Fig. 1).
8. Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Jae Sik Lee in view of Chung-Sun Lee.
9. Regarding Claim 4, Jae Sik Lee in view of Chung-Sun Lee discloses the semiconductor package of claim 1.
10. Jae Sik Lee in view of Chung-Sun Lee does not disclose that the first lower semiconductor chip is provided as a plurality of the first lower semiconductor chips stacked on the substrate, and wherein the plurality of first lower semiconductor chips are electrically connected to each other through each of the first lower through-vias.
11. However, Chung-Sun Lee further discloses that the lower semiconductor chip can be broken up into a plurality of lower semiconductor chips stacked on a substrate (Fig. 15, Para. [0106]) that are electrically connected to each other through lower through vias (Fig. 15, els. 52, 72, and 82, Para. [0107]).
It would have been obvious to one skilled in the art before the effective filing date of the
claimed invention to modify the lower semiconductor chip of Jae Sik Lee in view of Chung-Sun Lee to include a plurality of semiconductor chips connected to each other with through vias. As disclosed by Chung-Sun Lee, this has the advantage of adding more functionality to the basic logic chip, such as DRAM capability (Para. [0097]).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Jae Sik Lee in view of Chung-Sun Lee.
Regarding Claim 8, Jae Sik Lee in view of Chung Sun Lee discloses the semiconductor package of claim 1, further comprising: lower connection bumps (Jae Sik Lee, Fig. 1, el. 198, Para. [0033] disposed on a lower surface of the substrate (Jae Sik Lee, Fig. 1, Para. [0033]); first intermediate connection bumps disposed on a lower surface of the first lower semiconductor chip (Jae Sik Lee, Fig. 1, el. 192, Para. [0032]), and second intermediate connection bumps disposes on a lower surface of the second lower semiconductor chip (Jae Sik Lee, Fig. 1, el. 188, Para. [0032]).
Jae Sik Lee in view of Chung Sun Lee does not disclose third intermediate connection bumps on a lower surface of the interposer chip.
However, Jae Sik Lee discloses third intermediate connection bumps (Fig. 1, el. 174, Para. [0034]) on an upper surface of the interposer.
It would have been obvious to one skilled in the art before the effective filing date of the
claimed invention to add third intermediate connection bumps on a lower surface of the interposer chip in the package disclosed by Jae Sik Lee an Chung Sun Lee. When the interposer is placed in a separate chip, adding connection bumps is a standard way of allowing connection between the interposer chip and the substrate below.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Jae Sik Lee in view of Chung-Sun Lee and US20190198489A1 (Kim).
Regarding Claim 10, Jae Sik Lee in view of Chung-Sun Lee discloses the semiconductor package of claim 1.
Jae Sik Lee in view of Chung-Sun Lee does not disclose a chip structure disposed on the substrate and adjacent to the second lower semiconductor chip, wherein the chip structure includes a plurality of memory chips electrically connected to the second lower semiconductor chip through the substrate.
Kim discloses a semiconductor package (Fig. 1, el. 10, Para. [0023]) including a substrate (Fig. 1, el. 400, Para. [0024]), a lower semiconductor chip (Fig. 1, el. 200, Para. [0025]), and a chip structure (Fig. 1, el. 300, Para. [0023]) adjacent to the to the lower semiconductor chip (Fig. 1), wherein the chip structure includes a plurality of memory chips (Fig. 1, Para. [0024]) electrically connected to the lower semiconductor chip through the substrate (Para. [0024]).
It would have been obvious to one skilled in the art before the effective filing date of the
claimed invention to add a chip structure with a plurality of memory chips adjacent to the second lower semiconductor chip. As disclosed by Kim, this architecture has the advantage of having a high bandwidth memory device in the package, which provide high performance such as high capacity and high speed operation (Para. [0003]).
19. Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Jae Sik Lee in view of Chung-Sun Lee.
9. Regarding Claim 13, Jae Sik Lee in view of Chung-Sun Lee discloses the semiconductor package of claim 1.
10. Jae Sik Lee in view of Chung-Sun Lee does not disclose that the upper chip further comprises second connection pads disposed opposite to the first connection pads, and wherein the semiconductor package further comprises an uppermost chip disposed on an upper surface of the upper chip to be electrically connected to the upper chip through the second connection pads.
11. However, Chung-Sun Lee further discloses that the upper semiconductor chip can be broken up into a plurality of upper semiconductor chips stacked on a substrate (Fig. 15, Para. [0106]) that are electrically connected to each by connection pads (Fig. 15, els. 52, 72, and 82, Para. [0107]). The chips can be memory chips (Para. [0106]).
It would have been obvious to one skilled in the art before the effective filing date of the
claimed invention to add an uppermost chip to the upper chip of Jae Sik Lee in view of Chung-Sun and connect it with top connection pads. Doing so has the benefit of adding extra memory capability to the stack (Chung-Sun Lee, Para. [0106]).
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Jae Sik Lee in view of Chung-Sun Lee and US20140203457A1 (Kim).
Regarding Claim 15, Jae Sik Lee in view of Chung-Sun Lee discloses the semiconductor package of claim 1.
Jae Sik Lee in view of Chung-Sun Lee does not disclose a third lower semiconductor chip overlapping at least a portion of the upper chip in a direction substantially perpendicular to an upper surface of the substrate, and disposed adjacently to the first lower semiconductor chip in a direction parallel to the upper surface of the substrate and electrically connected to the substrate and the upper chip, wherein the third lower semiconductor chip comprises a chip of a same type as that of the first lower semiconductor chip.
Kim discloses a semiconductor package (Figs. 7 and 8, el. 700, Para. [0076]) that includes four lower semiconductor devices (Fig. 8, els. 720, 750, 760, and 770, Para. [0077]), each overlapping at least a portion of an upper chip (Fig. 8, el. 740) in a direction substantially perpendicular to an upper surface of the substrate, and one chip (el. 760 for example) disposed adjacently to the another (el. 720 for example) in a direction parallel to the upper surface of the substrate, and electrically connected to the substrate and the upper chip, where the lower chips are of the same type (Para. [0054]).
It would have been obvious to one skilled in the art before the effective filing date of the
claimed invention to add another lower chip in the manner disclosed by Kim to the package of Jae Sik Lee in view of Chung-Sun Lee to have more functionality in the package structure if needed.
Conclusion
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/ROHIT PARTHASARATHY/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899