DETAILED ACTION
AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restriction
Applicants’ 17 NOV 2025 election of Invention I, claims 1-16, is acknowledged. Because applicants did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.03(a)).
Priority
Acknowledgment is made of applicants' claim for foreign priority based on applications filed in KOREA on 8 JUL 2022 and 7 OCT 2022. It is noted that applicants have filed a certified copy of said applications as required by U.S.C 119, which papers have been placed of record in the file. See 19 SEP 2023 submissions.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 3 JUL 2023 was filed before the mailing of a first Office action on the merits. The submission follows provisions of 37 CFR 1.97. Accordingly, the IDS is being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale
supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1 and 2 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by HWANG et al. (US 20200135699; below, “HWANG”).
RE 1, HWANG, in FIG. 10 and related text, Abstract, FIGS. 1-9D, paragraphs [0001] to [0117], claims 1-20, discloses a semiconductor package comprising:
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a redistribution substrate (200);
a first semiconductor chip (100A, e.g., [0020]) disposed on the redistribution substrate (200), the first semiconductor chip (100A) including a first semiconductor substrate (110 of 100A, e.g., [0021]), first through vias (130 of 100A, e.g., [0021]) penetrating through the first semiconductor substrate (110 of 100A), and a first bonding layer (154, 164, e.g., [0021], [0106]) disposed on the first semiconductor substrate (110 of 100A), the first bonding layer (154, 164) is electrically connected to the first through vias (130 of 100A);
a second semiconductor chip (100B, e.g., [0020]) including a second semiconductor substrate (110 of 100B, e.g., [0021]) and a second bonding layer (152, 162, e.g., [0021], [0106]) disposed on the second semiconductor substrate (110 of 100B), the second bonding layer (152, 162) is bonded to the first bonding layer (154, 164); and
a filling insulating film (180) disposed on the redistribution substrate (200), the filling insulating film (180) covering the first semiconductor chip (100A) and the second semiconductor chip (100B),
wherein an upper surface of the filling insulating film (180) is disposed on a level above an upper surface of the first semiconductor chip (100A) and an upper surface of the second semiconductor chip (100B).
Thus, HWANG anticipates this claim.
RE 2, HWANG discloses the semiconductor package of claim 1, wherein:
the first bonding layer (154, 164) includes a first bonding insulating film (164)
disposed on the first semiconductor substrate (110 of 100A) and first bonding pads (154) disposed in the first bonding insulating film (164, e.g., FIG. 1);
the second bonding layer (152, 162) includes a second bonding insulating film (162) disposed on the second semiconductor substrate (110 of 100B) and second bonding pads (152) disposed in the second bonding insulating film (162, e.g., FIG. 1));
the first bonding insulating film (164) is bonded to the second bonding insulating film (162, hybrid-bonding structure); and
the first bonding pads (154) are bonded to the second bonding pads (152).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103(a) are summarized as follows (Graham Factors):
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 3 is rejected under 35 U.S.C. 103 as obvious over HWANG with evidence from or in view of Chen et al. (US 8378480; below, “Chen” – 20 JUN 2024 IDS noted prior art reference). At least “combining prior art elements”, “simple substitution”, “obvious to try”, and “applying a known technique to a known device” rationales support a conclusion of obviousness. MPEP § 2143(A)-(G).
RE 3, HWANG is silent regarding the semiconductor package of claim 1, further comprising: a dummy bonding insulating film disposed on the filling insulating film (180), and a dummy chip disposed on the dummy bonding insulating film, wherein the dummy bonding insulating film is bonded to the filling insulating film (180).
Chen, in Figures 1 to 23 and related text, Abstract, columns 1-8, teaches a dummy bonding insulating film (30, e.g., Fig. 3B) disposed on a filling insulating film (32), and a dummy chip (24’) disposed on the dummy bonding insulating film (30), wherein the dummy bonding insulating film (30 is bonded to the filling insulating film (32).
HWANG and Chen are analogous art from the same field of endeavor as the claimed invention. It would have been obvious to a person having ordinary skill in the art before the effective filing date of the instant application to modify HWANG as taught by Chen because: 1. improved planarity (Chen col. 3, lines 28-31) and increased yield results; and 2. all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination would have yielded predictable results to one of ordinary skill in the art at the time of the invention. KSR International Co. v. Teleflex Inc. (KSR), 550 U.S. 398 (2007).
Claim 8 is rejected under 35 U.S.C. 103 as obvious over HWANG with evidence from or in view of KANG et al. (US 20210320058; below, “KANG” – 20 JUN 2024 IDS noted prior art reference). MPEP § 2143(A)-(G).
RE 8, HWANG is silent regarding the semiconductor package of claim 1, further comprising pillars penetrating through the filling insulating film (180) from the upper surface of the filling insulating film (180), the pillars are bonded to the first bonding layer (154, 164).
KANG, in FIGS. 1-17 and related text, Abstract, paragraphs [0001] to [0118], teaches pillars (190) penetrating through a filling insulating film (195) from the upper surface of the filling insulating film (195), the pillars (190) being bonded to a bonding layer (240).
HWANG and KANG are analogous art from the same field of endeavor as the
claimed invention. It would have been obvious to a person having ordinary skill in the art before the effective filing date of the instant application to modify HWANG as taught by KANG because: 1. power consumption is reduced; 2. overall form factor of integrated circuit is scaled down; and 3. all the claimed elements were known … and one … could have combined the elements …, and the combination would have yielded predictable results …. KSR, 550 U.S. 398 (2007).
Claims 4-7 and 9-16 are rejected under 35 U.S.C. 103 as obvious over HWANG with evidence from or in view of DU et al. (CN 114203563; below, “DU” – 3 JUL 2023 IDS noted prior art reference). MPEP § 2143(A)-(G).
RE 4, HWANG is silent regarding the semiconductor package of claim 1, further comprising: a dummy chip disposed on the first semiconductor chip, the dummy chip is spaced apart from the second semiconductor chip; and a dummy bonding insulating film disposed between the first semiconductor chip and the dummy chip, wherein the dummy bonding insulating film is bonded to the first bonding layer (154, 164), and the filling insulating film (180, e.g., conformal coating) extends along sidewalls and an upper surface of the dummy chip.
DU, in FIGS. 1-10 and related text, e.g., Abstract, claims, paragraphs [0001] to [0085], teaches a dummy chip (120, e.g., FIGS. 3, 6) disposed on the first semiconductor chip (130, e.g., FIG. 3) (The Office notes that a preferred angle, i.e., absolute reference frame, is not claimed.), the dummy chip (120) is spaced apart from a second semiconductor chip (non-coplanar 130); and a dummy bonding insulating film (160, e.g., FIG. 4) disposed between the first semiconductor chip (130) and the dummy chip (120), wherein the dummy bonding insulating film (160) is bonded to the first bonding layer (HWANG’s 154, 164), and the filling insulating film (180, e.g., conformal deposition) extends along sidewalls and an upper surface of the dummy chip (120).
HWANG and DU are analogous art from the same field of endeavor as the claimed invention. It would have been obvious to a person having ordinary skill in the art before the effective filing date of the instant application to modify HWANG as taught by DU because: 1. improved planarity and increased yield results; and 2. all the claimed elements were known … and one … could have combined the elements …, and the combination would have yielded predictable results …. KSR, 550 U.S. 398 (2007).
RE 5, modified HWANG discloses the semiconductor package of claim 4, wherein the sidewalls of the dummy chip (DU’s 120) are disposed on (The Office notes that a preferred angle, i.e., absolute reference frame, is not claimed.) the first semiconductor chip (DU’s 130). See base claim 4’s motivation-to-combine statement.
RE 6, modified HWANG is silent regarding the semiconductor package of claim 4, wherein the upper surface of the second semiconductor chip (non-coplanar 130) is disposed on a same plane as the upper surface of the dummy chip (120).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the instant application to modify the device of HWANG wherein the upper surface of the second semiconductor chip is disposed on a same plane as the upper surface of the dummy chip, as such modification would involve a mere change in configuration. It has been held that a change in configuration of shape of a device is obvious, absent persuasive evidence that a particular configuration is significant. In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
RE 7, modified HWANG teaches the semiconductor package of claim 4, wherein
the upper surface of the second semiconductor chip (non-coplanar 130) is disposed on
a different plane from the upper surface of the dummy chip (120). See base claim 4’s
motivation-to-combine statement.
RE 9, modified HWANG discloses the semiconductor package of claim 1, wherein:
the first semiconductor substrate (110 of 100A) includes a first surface and a second surface opposing each other;
the second semiconductor substrate (110 of 100B) includes a third surface opposing the second surface and a fourth surface opposing the third surface;
the first semiconductor chip (100A) further includes a first semiconductor element layer (120) disposed on the first surface of the first semiconductor substrate (110 of 100A) and a first chip wiring layer (140) disposed on the first semiconductor element layer (120),
the second semiconductor chip (100B) further includes a second semiconductor element layer (120) disposed on the third surface of the second semiconductor substrate (110 of 100B) and a second chip wiring layer (140) disposed on the second semiconductor element layer (120),
the first bonding layer (154, 164) is disposed on the second surface of the first
semiconductor substrate (110 of 100A), and
the second bonding layer (152, 162) is disposed on the second chip wiring layer (140, e.g., [0022]).
RE 10, modified HWANG discloses the semiconductor package of claim 1,
further comprising a third semiconductor chip (100C) disposed on the second
semiconductor chip (100B),
wherein the filling insulating film (180) covers the third semiconductor chip
(100C),
the upper surface of the filling insulating film (180) is disposed on a level above an upper surface of the third semiconductor chip (100C),
the second semiconductor chip (100B) includes a third bonding layer (154, 164) disposed between the second semiconductor substrate (110 of 100B) and the third semiconductor chip (100C) and second through vias (130, e.g., [0021]) penetrating through the second semiconductor substrate (110 of 100B), the second through vias (130) are electrically connected to the third bonding layer (154, 164), and
the third semiconductor chip (100C) includes a third semiconductor substrate (110 of 100C) and a fourth bonding layer (152, 162) disposed on the third semiconductor substrate (110 of 100C), the fourth bonding layer (152, 162) is bonded to the third bonding layer (154, 164).
RE 11, modified HWANG discloses the semiconductor package of claim 10, wherein the second semiconductor chip (100B) further includes a first semiconductor element layer (120) disposed on a first surface of the second semiconductor substrate (110 of 100B) and a first chip wiring layer (140) disposed between the first semiconductor element layer (120) and the second bonding layer (152, 162), and
the third semiconductor chip (100C) further includes a second semiconductor element layer (120) disposed on a second surface of the third semiconductor substrate (110 of 100C) facing the first surface of the second semiconductor substrate (110 of 100B) and a third chip wiring layer (140) disposed between the second semiconductor
element layer (120) and the fourth bonding layer (152, 162).
RE 12, modified HWANG discloses the semiconductor package of claim 10,
wherein the second semiconductor chip (100B) further includes a first semiconductor element layer (120) disposed on a first surface of the second semiconductor substrate (110 of 100B) and a first chip wiring layer (140) disposed between the first semiconductor element layer (120) and the second bonding layer (152, 162),
the third semiconductor chip (100C) further includes third through vias (130, e.g., [0021]) penetrating through the third semiconductor substrate (110 of 100C), the third through vias (130) are disposed on a second surface of the third semiconductor substrate (110 of 100C), the third through vias (130) are electrically connected to the fourth bonding layer (152, 162), a second semiconductor element layer (120) is disposed on a third surface of the third semiconductor substrate (110 of 100C), and a second chip wiring layer (140) is disposed on the second semiconductor element layer (120), and
the second surface of the third semiconductor substrate (110 of 100C) opposes the third surface of the third semiconductor substrate (110 of 100C) and faces the first surface of the second semiconductor substrate (110 of 100B).
the first semiconductor chip (100A), the first dummy chip and the second dummy chip are spaced apart from each other; a first dummy bonding insulating film disposed between the first semiconductor chip (100A) and the first-first dummy chip and between the first semiconductor chip (100A) and the first-second dummy chip, the first dummy bonding insulating film is bonded to the first bonding layer (154, 164).
RE 13, modified HWANG discloses the semiconductor package of claim 10,
further comprising (see DU for: a first dummy chip and a second dummy chip),
wherein the filling insulating film (180) includes a first filling insulating film (180 - parts orthogonal to 200) and a second filling insulating film (180 – parts planar to 200) disposed on the first filling insulating film (180 - parts orthogonal to 200),
(see Du for: the first dummy chip is disposed on the first semiconductor chip (100A), the first dummy chip is spaced apart from the second semiconductor chip (100B)),
the first filling insulating film (180 - parts orthogonal to 200) is disposed on the redistribution substrate (200), the first filling insulating film (180 - parts orthogonal to 200) surrounds the first semiconductor chip (100A) and (see DU for: the first dummy chip, covers an upper surface of the first dummy chip), and exposes the upper surface of the second semiconductor chip (100B),
(see DU for: the second dummy chip is disposed on the first filling insulating film (180 - parts orthogonal to 200), the second dummy chip is spaced apart (e.g., not coplanar with 100C) from the third semiconductor chip (100C)), and
the second filling insulating film (180 – parts planar to 200) is disposed on the first filling insulating film (180 - parts orthogonal to 200), the second filling insulating film (180 – parts planar to 200) surrounds the third semiconductor chip (100C) and (see DU for: the second dummy chip, and covers an upper surface of the second dummy chip) and the upper surface of the third semiconductor chip (100C).
HWANG is silent regarding a first dummy chip and a second dummy chip; the first dummy chip being disposed on the first semiconductor chip (100A), the first dummy chip is spaced apart from the second semiconductor chip (100B); the first filling insulating film (180 - parts orthogonal to 200) surrounds (The Office notes that a preferred angle, i.e., absolute reference frame, is not claimed.) the first dummy chip and covers an upper surface of the first dummy chip; the second dummy chip is disposed on the first filling insulating film (180 - parts orthogonal to 200), the second dummy chip is spaced apart (e.g., not coplanar with 100C) from the third semiconductor chip (100C)); and the second filling insulating film (180 – parts planar to 200) surrounds the second dummy chip, and covers an upper surface of the second dummy chip.
DU, in FIGS. 1-10 and related text, e.g., Abstract, claims, paragraphs [0001] to [0085], teaches a first-first dummy chip (120 Left-side; “120L”) and a first-second dummy chip (120 Right-side; “120R”); the first dummy chip (120L) being disposed on the first semiconductor chip (100A in lieu of 130), the first dummy chip (120L) is spaced apart (not coplanar) from the second semiconductor chip (100B); the first filling insulating film (180 - parts orthogonal to 200) surrounds (The Office notes that a preferred angle, i.e., absolute reference frame, is not claimed.) the first dummy chip (120L) and covers an upper surface of the first dummy chip (120L); the second dummy chip (120R) is disposed on the first filling insulating film (180 - parts orthogonal to 200), the second dummy chip (120R) is spaced apart (e.g., not coplanar with 100C) from the third semiconductor chip (100C)); and the second filling insulating film (180 – parts planar to 200) surrounds the second dummy chip (120R), and covers an upper surface of the second dummy chip (120R).
HWANG and DU are analogous art from the same field of endeavor as the claimed invention. It would have been obvious to a person having ordinary skill in the art before the effective filing date of the instant application to modify HWANG as taught by DU because: 1. improved planarity and increased yield results; and 2. all the claimed elements were known … and one … could have combined the elements …, and the combination would have yielded predictable results …. KSR, 550 U.S. 398 (2007).
RE 14, HWANG, in FIG. 10 and related text, Abstract, FIGS. 1-9D, paragraphs [0001] to [0117], claims 1-20, discloses a semiconductor package comprising:
a redistribution substrate (200);
a first semiconductor chip (100A) disposed on the redistribution substrate (200), the first semiconductor chip (100A) including a first semiconductor substrate (110 of 100A), first through vias (130 of 100A) penetrating through the first semiconductor substrate (110 of 100A), and a first bonding layer (154, 164) disposed on the first semiconductor substrate (110 of 100A), the first bonding layer (154, 164) is electrically connected to the first through vias (130 of 100A);
(see DU for: a first-first dummy chip and a first-second dummy chip disposed on the first semiconductor chip (100A), the first-first dummy chip and the first-second dummy chip are spaced apart from each other;
a first dummy bonding insulating film disposed between the first semiconductor chip (100A) and the first-first dummy chip and between the first semiconductor chip (100A) and the first-second dummy chip, the first dummy bonding insulating film is bonded to the first bonding layer (154, 164));
a second semiconductor chip (100B) disposed on the first semiconductor chip
(100A), the second semiconductor chip (100B) is positioned between the first-first dummy chip and the first-second dummy chip (see DU), the second semiconductor chip (100B) including a second semiconductor substrate (110 of 100B) and a second bonding layer (152, 162) disposed on the second semiconductor substrate (110 of 100B), the second bonding layer (152, 162) is bonded to the first bonding layer (154, 164); and
a filling insulating film (180) disposed on the redistribution substrate (200), the filling insulating film (180) covering the first semiconductor chip (100A), the first-first dummy chip, the first-second dummy chip (see DU), and the second semiconductor chip (100B),
wherein an upper surface of the filling insulating film (180) is disposed on a level above an upper surface of the first semiconductor chip (100A), an upper surface of the first-first dummy chip, an upper surface of the first-second dummy chip (see DU), and an upper surface of the second semiconductor chip (100B), and
an entirety of the first-first dummy chip and an entirety of the first-second dummy chip (300-2) overlap the first semiconductor chip (100A) in a direction from the first semiconductor chip (100A) towards the second semiconductor chip (100B).
HWANG is silent regarding a first-first dummy chip and a first-second dummy chip disposed on the first semiconductor chip (100A), the first-first dummy chip and the first-second dummy chip are spaced apart from each other; a first dummy bonding insulating film disposed between the first semiconductor chip (100A) and the first-first dummy chip and between the first semiconductor chip (100A) and the first-second dummy chip, the first dummy bonding insulating film is bonded to the first bonding layer (154, 164).
DU, in FIGS. 1-10 and related text, e.g., Abstract, claims, paragraphs [0001] to [0085], teaches a first-first dummy chip (120 Left-side; “120L”) and a first-second dummy chip (120 Right-side; “120R”) disposed on (The Office notes that a preferred angle, i.e., absolute reference frame, is not claimed.) the first semiconductor chip (100A in lieu of 130), the first-first dummy chip (120L) and the first-second dummy chip (120R) are spaced apart from each other (e.g., FIG. 6); a first dummy bonding insulating film (160, e.g., FIG. 4) disposed between the first semiconductor chip (100A) and the first-first dummy chip (120L) and between the first semiconductor chip (100A) and the first-second dummy chip (120R), the first dummy bonding insulating film (160) is bonded to the first bonding layer (154, 164).
HWANG and DU are analogous art from the same field of endeavor as the claimed invention. It would have been obvious to a person having ordinary skill in the art before the effective filing date of the instant application to modify HWANG as taught by DU because: 1. improved planarity and increased yield results; and 2. all the claimed elements were known … and one … could have combined the elements …, and the combination would have yielded predictable results …. KSR, 550 U.S. 398 (2007).
RE 15, modified HWANG teaches the semiconductor package of claim 14, wherein:
the redistribution substrate (200) includes a redistribution layer (210, e.g., [0047])
and a substrate bonding layer (254, 264, e.g., [0047]) disposed on the redistribution layer; the first semiconductor chip (100A) further includes a third bonding layer (152, 162) disposed on the first semiconductor substrate (110 of 100A), the third bonding layer (152, 162) is bonded to the substrate bonding layer (254, 264); and
the semiconductor package further comprising connection terminals (170, e.g.,
FIG. 5) disposed on the redistribution substrate (200), the connection terminals (170)
are electrically connected to the redistribution layer (e.g., [0039]).
RE 16, modified HWANG teaches the semiconductor package of claim 15, wherein the substrate bonding layer (254, 264) and the first bonding layer (154, 164), and the first bonding layer (154, 164) and the second bonding layer (152, 162) are bonded to each other by a metal-oxide hybrid bonding method. Regarding the underlined portion of claim 16, the Office understands applicants’ desire to use broad method language instead of claim terms limited to a particular structural embodiment. Applicants are reminded that the method of forming a device is not germane to the issue of patentability of the device itself. "[E]ven though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process." In re Thorpe, 777 F.2d 695,698,227 USPQ 964, 966 (Fed. Cir. 1985).
Claims 1-16 are rejected.
Conclusion
The prior art made of record and not relied upon, Hu et al. (US 20200343218), is considered pertinent to applicants’ disclosure. Hu et al. does not teach, inter alia, a second semiconductor chip (200) including a second semiconductor substrate (210) and a second bonding layer (150) disposed on the second semiconductor substrate (210), the second bonding layer (150) is bonded to the first bonding layer (140); and a filling insulating film (400-1) disposed on the redistribution substrate (600), the filling insulating film (400-1) covering the first semiconductor chip (100) and the second semiconductor chip (200), wherein an upper surface of the filling insulating film (400-1) is disposed on a level above an upper surface of the first semiconductor chip (100) and an upper surface of the second semiconductor chip (200).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Walter Swanson whose telephone number is (571) 270-3322. The examiner can normally be reached Monday to Thursday, 8:30 to 17:30 EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joshua Benitez, can be reached on (571)270-1435. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
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/WALTER H SWANSON/Primary Examiner, Art Unit 2815