DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 6-10, 26-29 is/are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected invention, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 2/4/26.
Response to Arguments
Applicant's arguments filed 5/26/26 have been fully considered but they are not persuasive.
Applicant argues that McKnight-MacNeil teaches a die mounted within a modified PCB and that Edwards teaches a die mounted in a laminated sheet-like substrate, rather than a die arranged between separate first and second PCBs.
The argument is not persuasive because the rejections does not rely upon either McKnight-MacNeil or Edwards for the basic arrangement of die Di between the opposed first and second PCBs Pcba and Pcbbe. Degrenne is relied upon for that arrangement. McKnight-MacNeil and Edwards are relied upon for their teachings of conductive structures that electrically and thermally connect a die-facing contact to an opposite terminal contact through a PCB.
The test for obviousness is what the combined teachings of the references would have suggested on one of ordinary skill in the art, rather than whether the features of a secondary reference may be bodily incorporated into the prior reference without modification. The proposed combination therefore does not require the single-PCB structure of McKnight-MacNeil or the complete laminated structure of Edwards to replace the opposed-PCB arrangement of Degrenne. Rather, their teachings concerning through-PCB electrical and thermal connections are applied to the respective PCBs of Degrenne.
Applicant further argues that the cited references do not teach the features of the wherein clause.
This argument is also not persuasive. In the proposed combination, Degrenne provides die Di, first PCB Pcba, second PCB Pcbb3, first and second die contacts Cua, and source/drain elements So/Dr; McKnight-MacNeil and Edwards provide the electrical and thermal through-PCB connections between the respective die contacts and terminal contacts. When die Di is in its conducting operational mode, those connected elements collectively provide the claimed current path from the terminal contact of the first PCB, through the first PCB, source So, die Di, drain Dr, the second PCB, and to the terminal contact of the second PCB.
Accordingly, Applicant’s arguments have been fully considered but are not persuasive.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1, 3, 5, 24 is/are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication No. 2019/0320534 (Degrenne) in view of U.S. Patent Application Publication No. 2022/0020669 (McKnight-MacNeil) and U.S. Patent Application Publication No. 2008/0122061 (Edwards).
Degrenne discloses (Figs. 1a-4)
1. (Currently Amended) An electronic device, comprising:
a die Di mounted between a first printed circuit board (PCB) Pcba (top unlabeled) and a second printed circuit board (PCB) Pcbb3, the die Di including:
a first die element So at a first side of the die Di;
a second die element Dr at a second side of the die Di opposite the first side of the die Di;
the first PCB Pcba (top unlabeled) including:
a first PCB die contact Cua on a first side of the first PCB Pcba, the first PCB die contact Cua electrically and thermally connected to the first die element So; and
a first PCB terminal contact Cub on a second side of the first PCB Pcba opposite the first side of the first PCB Pcba;
the second PCB Pcbb3 including:
a second PCB die contact Cua on a first side of the second PCB Pccb3, the second PCB die contact Cua electrically and thermally connected to the second die element Dr; and
a second PCB terminal contact Cub on a second side of the second PCB Pcbb3 opposite the first side of the second PCB Pccb3.
Degrenne fails to disclose
the first PCB terminal contact electrically and thermally connected to the first PCB die contact;
the second PCB terminal contact electrically and thermally connected to the second PCB die contact.
McKnight- MacNeil teaches (Fig. 7)
An electronic device comprising:
the first substrate terminal contact 132-3 / 180-4 / 134-3 electrically and thermally connected to the first PCB die contact 130-2 / 180-2.
It would have been obvious to a person of ordinary skill in the art at the time the invention was made to provide electrical and thermal connections between a PCB terminal contact and a PCB die contact in Degrenne. The motivation would be to provide improved or alternative embedded die packaging for power semiconductor devices and to provide improved structural integrity, reliability and electrical isolation performance as taught by McKnight-MacNeil ([0047], [0114]-[0116]).
Edwards teaches (Figs. 2)
An electronic device comprising:
the first PCB terminal contact 260 electrically and thermally connected to the first PCB die contact 143; and
the second PCB terminal contact 150 electrically and thermally connected to the second PCB die contact 144.
It would have been obvious to a person of ordinary skill in the art at the time the invention was made to provide electrical and thermal connections for a die embedded between two substrates in the modified device of Degrenne. The motivation would be to provide heat extraction from opposite sides of an embedded die to improve thermal management as taught by Edwards ([0005]-[0008], [0114]).
The combination of references teaches
wherein the first PCB, the die, and the second PCB collectively define a conductive path allowing a communication of current from the first PCB terminal contact to the second PCB terminal contact through the first PCB, the die, and the second PCB, during at least one operational mode of the die.
In the modified device of Degrenne, the path extends from the PCB terminal contact Cub, through the conductive structure of PCB Pcba to PCB die contact Cua, through die element So, die Di, and die Dr, through PCB die contact Cua and conductive structure of PCB Pcbbe, to PCB terminal contact Cub.
Degrenne further teaches that die Di is a semiconductor switching device having die elements So and Dr at opposing sides. During a conducting operational state of die Di, current is communicated between So and Dr. Thus, when the electrically conductive through PCB connections taught by McKnight-MacNeil and Edward are incorporated into Degrenne, the limitations of the wherein clause are met. Conversely, when the semiconductor device is in its OFF state, the die interrupts that conductive path.
McKnight-MacNeil and Edwards teach
3. (Currently Amended) The electronic device of Claim 1, comprising:
a first PCB integrated conductive structure (includes PCB and contacts) extending through a thickness of the first PCB Pcbb3 to electrically and thermally connect the first PCB die contact with the first PCB terminal contact; and
a second PCB integrated conductive structure (includes PCB and contacts) extending through a thickness of the second PCB 104 to electrically and thermally connect the second PCB die contact with the second PCB terminal contact.
McKnight-MacNeil ([0084]) and Edwards ([0020]) teach
Degrenne discloses (Figs. 1a-4)
5. (Currently Amended) The electronic device of Claim 1, wherein:
the die Di comprises a vertical transistor ([0059]);
the first die element So comprises a source of the vertical transistor;
the second die element Dr comprises a drain of the vertical transistor;
the first PCB die contact Cua on the first side of the first PCB Pcba comprises a source contact; and
the second PCB die contact Cua on the first side of the second PCB Pcbb3 comprises a drain contact.
McKnight-MacNeil and Edwards teach (because if the die is in an “OFF” state there is no conductive path)
McKnight-MacNeil and Edwards teach
24. (Currently Amended) The electronic device of Claim 5, comprising:
a first PCB integrated conductive structure (includes PCB and contacts) extending through a thickness of the first PCB Pcbb3 to electrically and thermally connect the first PCB die contact 130-2 /180-2 with the first PCB terminal contact 132-3 / 180-4 / 134-3 (Fig. 7, [0084]); and
a second PCB integrated conductive structure (includes PCB and contacts) extending through a thickness of the second PCB 104 to electrically and thermally connect the second PCB die contact 150 with the second PCB terminal contact 144 (Fig. 2, [0020]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. U.S. Patent Application Publication Nos. 2023/0395464 (Du), 2021/0267044 (Frauwallner), 2013/0020694 (Liang) teach two-sided thermal and electrical conductivity for a die.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TERESA M ARROYO whose telephone number is (703)756-1576. The examiner can normally be reached Monday - Friday (8:30 A.M. E.T. - 5:00 P.M. E.T.).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached at 571.272.1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TERESA M. ARROYO/Primary Examiner, Art Unit 2893
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