Prosecution Insights
Last updated: April 19, 2026
Application No. 18/217,800

ELECTRONIC DEVICE INCLUDING A DIE ARRANGED BETWEEN FIRST AND SECOND SUBSTRATES

Non-Final OA §103
Filed
Jul 03, 2023
Examiner
ARROYO, TERESA M
Art Unit
2893
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Microchip Technology Inc.
OA Round
1 (Non-Final)
72%
Grant Probability
Favorable
1-2
OA Rounds
3y 3m
To Grant
96%
With Interview

Examiner Intelligence

Grants 72% — above average
72%
Career Allow Rate
352 granted / 489 resolved
+4.0% vs TC avg
Strong +24% interview lift
Without
With
+23.5%
Interview Lift
resolved cases with interview
Typical timeline
3y 3m
Avg Prosecution
37 currently pending
Career history
526
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
57.6%
+17.6% vs TC avg
§102
18.6%
-21.4% vs TC avg
§112
19.0%
-21.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 489 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Election/Restrictions Applicant’s election without traverse of Group I (claims 1-11) in the reply filed on 2/4/26 is acknowledged. Applicant's provisional election with traverse of one or more of the sub - combinations in the reply filed on 2/4/26 is acknowledged. The traversal is on the ground(s) that the sub-combinations do not have separate utility and there is no serious burden to examine the sub-combination together . This is not found persuasive because the previous Examiner showed separate utility (e.g., use in a different device) and a serious burden (e.g., a distinct, separate, and non-obvious search) . For example, sub-combinations including the gate driver (claim s 6, 7) and the busbar (claim s 8-11, 26-29 ) are not necessary to make the combination (claim 1) work. The gate driver can be used in a different device such as IGBTs, motors, converters, power supplies, inverters. The busbar can be used in a different device such as electrical distribution panels, substations, electric vehicle systems. Further, contrary to Applicant’s arguments, the electronic device limitations in claims 1- 5 , 23-25 (generally H10W 90/00) are not classified with the gate driver limitations in claims 6, 7 ( generally H03K 17/00) or with the busbar limitations in claims 8-11, 26-29 (generally H02G 5/00) . Applicant is not permitted to provisionally elect or cancel claims in response to a restriction requirement, even if traversed. Additionally, the features in claims 2-4 appear to be essential to make the combination work. Finally, adding claims 23-25 while provisionally electing not to examine claims 2-4, which are essentially identical , does not support Applicant’s arguments as to which claims should be examined together. Accordingly, claims 1- 5 and 23-25 are examined below , and claims 6, 7 (gate driver) , 8 -11 (busbar) , 26-29 (bus bar) are withdrawn from consideration. The requirement is still deemed proper and is therefore made FINAL. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis ( i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claim(s) 1 -5, 23-25 is/are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication No. 2019 / 0320534 (Degrenne) in view of U.S. Patent Application Publication No. 2022 / 0020669 (McKnight- M acN e i l ) and U.S. Patent Application Publication No. 2008 / 0122061 (Edwards). Degrenne discloses (Figs. 1a-4) 1. (Original) An electronic device, comprising: a die Di mounted between a first substrate Pcba (top unlabeled) and a second substrate Pcbb3 , the die Di including: a first die element So at a first side of the die Di ; a second die element Dr at a second side of the die Di opposite the first side of the die Di ; the first substrate Pcba (top unlabeled) including: a first substrate die contact Cua on a first side of the first substrate Pcba , the first substrate die contact Cua electrically and thermally connected to the first die element So ; and a first substrate terminal contact Cub on a second side of the first substrate Pcba opposite the first side of the first substrate Pcba ; the second substrate Pcbb3 including: a second substrate die contact Cua on a first side of the second substrate Pccb3 , the second substrate die contact Cua electrically and thermally connected to the second die element Dr ; and a second substrate terminal contact Cub on a second side of the second substrate Pcbb3 opposite the first side of the second substrate Pccb3 ,. Degrenne fails to disclose the first substrate terminal contact electrically and thermally connected to the first substrate die contact ; the second substrate terminal contact electrically and thermally connected to the second substrate die contact . McKnight- MacNeil teaches (Fig. 7) An electronic device comprising: the first substrate terminal contact 132-3 / 180-4 / 134-3 electrically and thermally connected to the first substrate die contact 130-2 / 180-2 . It would have been obvious to a person of ordinary skill in the art at the time the invention was made to provide electrical and thermal connections between a substrate terminal contact and a substrate die contact in Degrenne. The motivation would be to provide improved or alternative embedded die packaging for power semiconductor devices and to provide improved structural integrity, reliability and electrical isolation performance as taught by McKnight- MacNeil ([0047], [0114]-[0116]) . Edwards teaches (Fig s . 2 ) An electronic device comprising: the first substrate terminal contact 260 electrically and thermally connected to the first substrate die contact 143. the second substrate terminal contact 150 electrically and thermally connected to the second substrate die contact 144 . It would have been obvious to a person of ordinary skill in the art at the time the invention was made to provide electrical and thermal connections for a die embedded between two substrates in the modified device of Degrenne. The motivation would be to provide two-way heat extraction as taught by Edwards ([0005]-[0008], [0114]). McKnight- MacNeil and Edwards teach (because if the die is in an “OFF” state there is no conductive path) 2. (Original) The electronic device of Claim 1, wherein the first substrate, the die, and the second substrate collectively define a conductive path allowing a communication of current from the first substrate terminal contact to the second substrate terminal contact through the first substrate, the die, and the second substrate, during at least one operational mode of the die. McKnight- MacNeil and Edwards teach 3. (Original) The electronic device of Claim 1, comprising: a first substrate integrated conductive structure (includes substrate and contacts) extending through a thickness of the first substrate Pcbb3 to electrically and thermally connect the first substrate die contact with the first substrate terminal contact; and a second substrate integrated conductive structure (includes substrate and contacts) extending through a thickness of the second substrate 104 to electrically and thermally connect the second substrate die contact with the second substrate terminal contact. McKnight- MacNeil ([0084]) and Edwards ([0020]) teach 4. (Original) The electronic device of Claim 1, wherein the first substrate comprises a first printed circuit board, and the second substrate comprises a second printed circuit board. Degrenne discloses 5. (Original) The electronic device of Claim 1, wherein: the die Di comprises a vertical transistor ([0059]) ; the first die element So comprises a source of the vertical transistor; the second die element Dr comprises a drain of the vertical transistor; the first substrate die contact Cua on the first side of the first substrate Pcba comprises a source contact; and the second substrate die contact Cua on the first side of the second substrate Pcbb3 comprises a drain contact. McKnight- MacNeil and Edwards teach (because if the die is in an “OFF” state there is no conductive path) 23. (New) The electronic device of Claim 5, wherein the first substrate, the die, and the second substrate collectively define a conductive path allowing a communication of current from the first substrate terminal contact to the second substrate terminal contact through the first substrate, the die, and the second substrate, during at least one operational mode of the die. McKnight- MacNeil and Edwards teach 24. (New) The electronic device of Claim 5, comprising: a first substrate integrated conductive structure (includes substrate and contacts) extending through a thickness of the first substrate Pcbb3 to electrically and thermally connect the first substrate die contact with the first substrate terminal contact; and a second substrate integrated conductive structure (includes substrate and contacts) extending through a thickness of the second substrate 104 to electrically and thermally connect the second substrate die contact with the second substrate terminal contact. McKnight- MacNeil ([0084]) and Edwards ([0020]) teach 25. (New) The electronic device of Claim 5, wherein the first substrate comprises a first printed circuit board, and the second substrate comprises a second printed circuit board. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. U.S. Patent Nos. 12 , 062 , 593 (Joshi), 9,059,127 (Lamorey), 7 , 030 , 317 (Oman) , and U.S. Patent Application Publication No s . 2013 / 0020694 (Liang), 2006 / 0261468 (Sobhani), 2004 / 0067617 (Hower) teach two-sided thermal and electrical conductivity for a die . Any inquiry concerning this communication or earlier communications from the examiner should be directed to FILLIN "Examiner name" \* MERGEFORMAT TERESA M ARROYO whose telephone number is FILLIN "Phone number" \* MERGEFORMAT (703)756-1576 . The examiner can normally be reached FILLIN "Work Schedule?" \* MERGEFORMAT Monday - Friday (8:30 A.M. E.T. - 5:00 P.M. E.T.) . Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, FILLIN "SPE Name?" \* MERGEFORMAT Sue Purvis can be reached at FILLIN "SPE Phone?" \* MERGEFORMAT 571.272.1236 . The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /TERESA M. ARROYO/ Primary Examiner, Art Unit 2893
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Prosecution Timeline

Jul 03, 2023
Application Filed
Feb 21, 2026
Non-Final Rejection — §103 (current)

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Prosecution Projections

1-2
Expected OA Rounds
72%
Grant Probability
96%
With Interview (+23.5%)
3y 3m
Median Time to Grant
Low
PTA Risk
Based on 489 resolved cases by this examiner. Grant probability derived from career allow rate.

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