DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of group I in the reply filed on 2/2/2026 is acknowledged. Claims 16-20 are withdrawn. Claims 1-15 are examined on the merits.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 1-3, 5-6, 8-10, and 12-13 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Pat. Pub. No. US 20160042998 A1 to Pueschner et al. (hereinafter “Pueschner”) in view of U.S. Pat. No. US 5736424 A to Prybyla et al. (hereinafter “Prybyla”) and further in view of U.S. Pat. Pub. No. US 20080185361 A1 to Summers (hereinafter “Summers”).
Regarding claim 1, Pueschner teaches a method of making a semiconductor device assembly (figs. 2A-2F), comprising:
attaching a first semiconductor device (204a, 204b; fig. 2B) [0038] to an upper surface (vertically upper) of a substrate (carrier 206; fig. 2B) [0035];
disposing a stencil (fin pattern 210; fig. 2B) [0033] over the upper surface (vertically) of the substrate (206), wherein the stencil (210) includes an opening (opening giving access to device 204a and 204b) and a cavity (space occupied by device 204a and 204b; fig. 2B) in which the first semiconductor device (204a and 204b) is disposed (fig. 2C);
depositing an epoxy material (material of encapsulating thermosetting resin 212; fig. 2C) [0039] into the opening (access opening) and onto the upper surface (vertical) of the substrate (206) to form an epoxy spacer (212);
removing the stencil (210; fig. 2E) [0040]; and
Pueschner does not teach:
planarizing an upper surface of the epoxy material to form an epoxy spacer.
Prybyla, however, teaches planarizing an epoxy material using contact planarization (pressing as recited in claims 1 & 5).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the method of Pueschner with a planarizing process for the epoxy material to produce a planar surface, increasing surface quality as taught by Prybyla (abstract).
Pueschner in view of Prybyla does not teach that the epoxy material is deposited in the opening through screen printing.
Summers, however, teaches screen-printing [0065] using epoxy materials [0033] to assist in forming semiconductor devices (abstract).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the method of Pueschner in view of Prybyla to comprise a screen-printing process to deposit the epoxy material to increase the number of simultaneous deposition of spacers (20 minimum), thus increasing efficiency as taught by Prybyla [0065].
Regarding claim 2, Pueschner in view of Prybyla and Summers teaches the method of claim 1, wherein the cavity (space occupied by devices 204a and 204b) extends only partially through (not extending on the other vertical side thereof) the stencil (210) from a lower surface thereof (vertically lower surface).
Regarding claim 3, Pueschner in view of Prybyla and Summers teaches the method of claim 1, wherein planarizing the upper surface (vertically upper) of the epoxy material (212) comprises pressing a planar surface of a pressing tool (tool of Prybyla, as used to modify Puschner, see claims 1 & 5) into the upper surface of the epoxy material (212).
Regarding claim 5, Pueschner in view of Prybyla and Summers, as presently modified, does not teach the method of claim 1, further comprising applying heat to partially cure the epoxy material before planarizing the upper surface of the epoxy material.
Prybyla, however, teaches applying heat to partially cure (col. 7 ln. 45-60) the epoxy material before (at least before completing planarization) planarizing (col. 7 ln. 45-60) the upper surface of the epoxy material.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the method of Pueschner in view of Prybyla and Summers to partially cure the material before planarizing the upper surface of the material to result in increased surface planarity as taught by Prybyla (col. 3 ln. 1-10).
Regarding claim 6, Pueschner in view of Prybyla and Summers, as presently modified, does not teach the method of claim 1, further comprising applying heat to fully cure the epoxy spacer.
Prybyla, however, teaches applying heat to fully cure the epoxy spacer (col. 6 ln. 34-50).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the method of Pueschner in view of Prybyla and Summers to apply heat to the spacer to fully cure the spacer to induce polymerization as taught by Prybyla (col. 6 ln. 34-50).
Regarding claim 8, Pueschner teaches a method of making a plurality of semiconductor device assemblies,
comprising:
attaching a plurality of first semiconductor devices (204a, 204b; fig. 2B) [0038] to an upper surface (vertically upper) of a panel (carrier 206; fig. 2B) [0035];
disposing a stencil (fin pattern 210; fig. 2B) [0033] over the upper surface (vertically) of the panel (206), wherein the stencil (210) includes a plurality of openings (opening giving access to device 204a and 204b) and a plurality of cavities (space occupied by device 204a and 204b; fig. 2B) in which the plurality of first semiconductor devices (204a and 204b) are disposed (fig. 2C);
depositing an epoxy material (material of encapsulating thermosetting resin 212; fig. 2C) [0039] into the plurality of openings (access opening) and onto the upper surface (vertical) of the panel (206);
removing the stencil (210; fig. 2E) [0040]; and
Pueschner does not teach:
planarizing an upper surface of the epoxy material to form a plurality of epoxy spacers.
Prybyla, however, teaches planarizing an epoxy material using contact planarization (pressing as recited in claims 1 & 5).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the method of Pueschner with a planarizing process for the epoxy material to produce a planar surface, increasing surface quality as taught by Prybyla (abstract).
Pueschner in view of Prybyla does not teach that the epoxy material is deposited in the opening through screen printing.
Summers, however, teaches screen-printing [0065] using epoxy materials [0033] to assist in forming semiconductor devices (abstract).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the method of Pueschner in view of Prybyla to comprise a screen-printing process to deposit the epoxy material to increase the number of simultaneous deposition of spacers (20 minimum), thus increasing efficiency as taught by Prybyla [0065].
Regarding claim 9, Pueschner in view of Prybyla and Summers teaches the method of claim 8, wherein the cavity (space occupied by devices 204a and 204b) extends only partially through (not extending on the other vertical side thereof) the stencil (210) from a lower surface thereof (vertically lower surface).
Regarding claim 10, Pueschner in view of Prybyla and Summers teaches the method of claim 8, wherein planarizing the upper surfaces (vertically upper) of the epoxy material (212) comprises pressing a planar surface of a gang-pressing tool (tool of Prybyla, as used to modify Puschner, the tool pressing multiple locations of material at the same time, see claims 1 & 5) into the upper surfaces (vertically upper) of the epoxy material.
Regarding claim 12, Pueschner in view of Prybyla and Summers, as presently modified, does not teach the method of claim 8, further comprising applying heat to partially cure the epoxy material before planarizing the upper surface of the epoxy material.
Prybyla, however, teaches applying heat to partially cure (col. 7 ln. 45-60) the epoxy material before (at least before completing planarization) planarizing (col. 7 ln. 45-60) the upper surface of the epoxy material.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the method of Pueschner in view of Prybyla and Summers to partially cure the material before planarizing the upper surface of the material to result in increased surface planarity as taught by Prybyla (col. 3 ln. 1-10).
Regarding claim 13, Pueschner in view of Prybyla and Summers, as presently modified, does not teach the method of claim 8, further comprising applying heat to fully cure the plurality of epoxy spacers.
Prybyla, however, teaches applying heat to fully cure the plurality of epoxy spacers (col. 6 ln. 34-50).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the method of Pueschner in view of Prybyla and Summers to apply heat to the spacer to fully cure the spacer to induce polymerization as taught by Prybyla (col. 6 ln. 34-50).
Claims 7 & 14 are rejected under 35 U.S.C. 103 as being unpatentable over Pueschner in view of Prybyla and Summers as applied to claim 1 above, and further in view of U.S. Pat. Pub. No. US 20150311185 A1 to Ng et al. (hereinafter “Ng”).
Regarding claim 7. Pueschner in view of Prybyla and Summers, does not teach the method of claim 1, further comprising attaching a second semiconductor device to the epoxy spacer and over the first semiconductor device.
Ng, however, teaches a method (figs. 3A-3C) comprising attaching a second semiconductor device (memory die 106a; fig. 3B) [0013] to the epoxy spacer (support member 130a; fig. 3B) [0013] and over the first semiconductor device (controller die 103; fig. 3A) [0013].
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the method of Pueschner in view of Prybyla and Summers to attach a second device above the first device to form a stacked die structure, thus increasing die density as taught by Ng [0003].
Regarding claim 14, Pueschner in view of Prybyla and Summers, does not teach the method of claim 8, further comprising attaching a plurality of second semiconductor devices to the plurality of epoxy spacers and over the plurality of first semiconductor devices.
Ng, however, teaches a method (figs. 3A-3C) comprising attaching a plurality of second semiconductor devices (memory die 106a; fig. 3B) [0013] to the epoxy spacer (support member 130a; fig. 3B) [0013] and over the first semiconductor device (controller die 103; fig. 3A) [0013].
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the method of Pueschner in view of Prybyla and Summers to attach a second device above the first device to form a stacked die structure, thus increasing die density as taught by Ng [0003].
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Pueschner in view of Prybyla and Summers as applied to claim 8 above, and further in view of U.S. Pat. Pub. No. US 20210358888 A1 to Boo et al. (hereinafter “Boo”).
Regarding claim 15, Pueschner in view of Prybyla and Summers does not teach the method of claim 8, further comprising singulating the panel into a plurality of substrates, each including a corresponding first semiconductor device and at least one of the plurality of epoxy spacers.
Boo, however, teaches a method of forming a semiconductor die stack (fig. 1A) comprising singulating the panel (carrier) [0009] into a plurality of substrates (singulated carriers) [0009], each including a corresponding first semiconductor device (IC die 104a; fig. 1A) [0017] and at least one of the plurality of epoxy spacers (128a; fig. 1A) [0017].
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the method of Pueschner in view of Prybyla and Summers to singulate the panel into a plurality of substrates including the elements of claim 15 to allow for testing of individual assemblies as taught by Boo [0009].
Allowable Subject Matter
Claims 4 and 11 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding reasons for allowance, it is not found, in the context of claims 4 and 11, some reference which may be used to modify the cited references to meet the limitations of these claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ETHAN EDWARD CUTLER whose telephone number is (703)756-5415. The examiner can normally be reached Monday-Friday 7:30 am - 5:00 pm Eastern Time.
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/ETHAN EDWARD CUTLER/Examiner, Art Unit 2892
/NORMAN D RICHARDS/ Supervisory Patent Examiner, Art Unit 2892
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