DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment of claims 1, 9 and 17 filed on November 19, 2025 has been entered and considered by examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2, 6-10, 14-18 and 22-24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kimura et al (U.S. Patent Pub. No. 2013/0264574; already of record) and in view of Jang (U.S. Patent Pub. No. 2018/0366067).
Regarding claim 1, Kimura discloses a semiconductor device (fig. 12, [0186]), comprising:
a first transistor (1202);
a second transistor (1202B);
a third transistor (1201); and
a first capacitor (1204), (fig. 12),
wherein the other of the source and the drain of the third transistor (1201) is directly connected to a gate of the first transistor (1202) and a first terminal of the first capacitor (1204), and
wherein one of a source and a drain of the first transistor (1202) is directly connected to one of a source and a drain of the second transistor (1202B) via VDD,
wherein the other of the source and the drain of the first transistor (1202) is directly connected to the other of the source and the drain of the second transistor (1202B) and a second terminal of the first capacitor (1204), (fig. 12, [0136-0140]).
However, Kimura does not mention wherein one of a source and a drain of the third transistor is directly connected to a gate of the second transistor.
In a similar field of endeavor, Jang teaches
wherein one of a source and a drain of the third transistor (T4) is directly connected to a gate of the second transistor (Tu2), and
wherein the other of the source and the drain of the third transistor (T4) is directly connected to a gate of the first transistor (Tu1), (fig. 9, [0149 and 0162-0163]).
Therefore, it would have been obvious to one of ordinary skills in the art at the effective filing date of the claimed invention to modify Kimura, by specifically providing the one of a source and a drain of the third transistor is directly connected to a gate of the second transistor, as taught by Jang, for the purpose of having a stably output signals, [0022].
Regarding claim 2, Kimura discloses further comprising a fifth transistor (1203),
wherein one of a source and a drain of the fifth transistor (MN7) is electrically connected to the other of the source and the drain of the first transistor (1202), (fig. 12, [0137]).
Regarding claim 6, Kimura discloses a display apparatus (fig. 28), comprising:
a driver circuit (2810); and
a display device (2801), (fig. 28, [0188]),
wherein the driver circuit (2810) comprises the semiconductor device according to claim 1, and
wherein the driver circuit (2810) is configured to transmit a signal (video signals) for image display to the display device (2801), (fig. 28, [0188-0191]).
Regarding claim 7, Kimura discloses wherein the display device (2801) comprises one of a light-emitting device (organic EL) and a liquid crystal display device (LCD), (fig. 28, [0188]).
Regarding claim 8, Kimura discloses an electronic device (fig. 32a) comprising:
the display apparatus (DSP) according to claim 7; and
a housing (13001), (fig. 32a, [0210]).
Regarding claim 9, Kimura discloses a semiconductor device (fig. 12, [0186]), comprising:
a first transistor (1202);
a second transistor (1202B);
a third transistor (1201);
a fourth transistor (1206); and
a first capacitor (1204), (fig. 12),
wherein one of a source and a drain of the third transistor (1201) is directly connected to a gate of the third transistor,
wherein the other of the source and the drain of the third transistor (1201) is directly connected to a gate of the first transistor (1202), one of a source and a drain of the fourth transistor (1206), and a first terminal of the first capacitor (1204),
wherein one of a source and a drain of the first transistor (1202) is directly connected to one of a source and a drain of the second transistor (1202B) via VDD, and
wherein the other of the source and the drain of the first transistor (1202) is directly connected to the other of the source and the drain of the second transistor (1202B) and a second terminal of the first capacitor (1204), (fig. 12, [0136-0140]).
However, Kimura does not mention wherein one of a source and a drain of the third transistor is directly connected to a gate of the second transistor and a gate of the third transistor.
In a similar field of endeavor, Jang teaches
wherein one of a source and a drain of the third transistor (T4) is directly connected to a gate of the second transistor (Tu2) and a gate of the third transistor (T4), and
wherein the other of the source and the drain of the third transistor (T4) is directly connected to a gate of the first transistor (Tu1), (fig. 9, [0149 and 0162-0163]).
Therefore, it would have been obvious to one of ordinary skills in the art at the effective filing date of the claimed invention to modify Kimura, by specifically providing the one of a source and a drain of the third transistor is directly connected to a gate of the second transistor, as taught by Jang, for the purpose of having a stably output signals, [0022].
Regarding claims 10 and 14-16, please refer to claims 2 and 6-8, respectively for details.
Regarding claim 17, Kimura discloses a semiconductor device (fig. 12, [0186]), comprising:
a first transistor (1202);
a second transistor (1202B);
a third transistor (1201);
a fourth transistor (1206); and
a first capacitor (1204), (fig. 12),
wherein one of a source and a drain of the third transistor (1201) is directly connected to a gate of the first transistor (1202), one of a source and a drain of the fourth transistor (1206), and a first terminal of the first capacitor (1204),
wherein one of a source and a drain of the first transistor (1202) is directly connected to one of a source and a drain of the second transistor (1202B) via VDD, and
wherein the other of the source and the drain of the first transistor (1202) is directly connected to the other of the source and the drain of the second transistor (1202B) and a second terminal of the first capacitor (1204), (fig. 12, [0136-0140]).
However, Kimura does not mention wherein a gate of the third transistor is directly connected to a gate of the second transistor.
In a similar field of endeavor, Jang teaches
wherein a gate of the third transistor (T4) is directly connected to a gate of the second transistor (Tu1), and
wherein one of a source and a drain of the third transistor (T4) is directly connected to a gate of the first transistor (Tu2), (fig. 9, [0149 and 0162-0163]).
Therefore, it would have been obvious to one of ordinary skills in the art at the effective filing date of the claimed invention to modify Kimura, by specifically providing the one of a source and a drain of the third transistor is directly connected to a gate of the second transistor, as taught by Jang, for the purpose of having a stably output signals, [0022].
Regarding claims 18 and 22-24, please refer to claims 2 and 6-8, respectively for details.
Claim(s) 3, 11 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kimura in view of Jang and in view of Umezaki et al (U.S. Patent Pub. No. 2017/0132985).
Regarding claim 3, Kimura discloses everything as specified above in claim 2. However, Kimura in view of Jang does not mention a sixth-eighth transistors.
In a similar field of endeavor, Umezaki teaches further comprising:
a sixth transistor (121);
a seventh transistor (126);
an eighth transistor (125); and
a second capacitor (124), (fig. 8),
wherein one of a source and a drain of the eighth transistor (125) is directly connected to a gate of the sixth transistor (121) and a first terminal of the second capacitor (124),
wherein a gate of the seventh transistor (126) is directly connected to the other of the source and the drain of the first transistor (111),
wherein one of a source and a drain of the sixth transistor (121) is directly connected to one of a source and a drain of the seventh transistor (126) and a second terminal of the second capacitor (124), (fig. 8, [0216-0217]).
Therefore, it would have been obvious to one of ordinary skills in the art at the effective filing date of the claimed invention to modify Kimura in view of Jang, by specifically providing, a gate of the seventh transistor is directly connected to the other of the source and the drain of the first transistor, as taught by Umezaki, for the purpose of suppressing distortion of a signal, [0014].
Regarding claims 11 and 19, please refer to claim 3 for details.
Allowable Subject Matter
Claims 4-5, 12-13 and 20-21 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Reasons for Allowance
Claim 4, Umezaki discloses further comprising: a sixth transistor (121); a seventh transistor (126); an eighth transistor (125); and a second capacitor (124), wherein one of a source and a drain of the eighth transistor is electrically directly connected to a gate of the sixth transistor and a first terminal of the second capacitor, (fig. 12).
However, none of the prior art of record teaches alone or in combination the limitation “wherein the other of the source and the drain of the eighth transistor is electrically directly connected to the other of the source and the drain of the first transistor, wherein one of a source and a drain of the sixth transistor is electrically directly connected to one of a source and a drain of the seventh transistor and a second terminal of the second capacitor, and wherein a gate of the seventh transistor is electrically directly connected to a gate of the fifth transistor.”
Claim 5 is dependent upon claim 4 and is allowed for the reason mentioned above in claim 4.
Claims 12 and 20 are allowed for similar reason as mentioned above in claim 4.
Claims 13 and 21 are dependent upon claims 12 and 20, respectively and are allowed for the reason mentioned above in claims 12 and 20, respectively.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 9 and 17 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
In view of amendment, the reference of Jang has been added for new grounds of rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/LONG D PHAM/Primary Examiner, Art Unit 2623