DETAILED ACTION
Table of Contents
I. Notice of Pre-AIA or AIA Status 3
II. Election/Restrictions 3
III. Information Disclosure Statement 3
IV. Claim Rejections - 35 USC § 103 3
A. Claims 1-9, 12, and 13 are rejected under 35 U.S.C. 103 as being unpatentable over US 2021/0082767 (“Kim”) in view of US 2017/0040214 (“Lai”). 4
B. Claims 10, 11, and 17-20 are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Lai, as applied to claim 1, above, and further in view of US 2011/0003468 (“Song”). 10
V. Pertinent Prior Art 13
Conclusion 14
[The rest of this page is intentionally left blank.]
I. Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
II. Election/Restrictions
Applicant’s election without traverse of invention group I, claims 1-13 and 17-20 in the reply filed on 12/26/2025 is acknowledged.
Claims 14-16 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim.
III. Information Disclosure Statement
The document lined through in the IDS filed 09/03/2024 has not been considered because no copy of the document was provided. See 37 C.F.R. 1.98(2).
IV. Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
A. Claims 1-9, 12, and 13 are rejected under 35 U.S.C. 103 as being unpatentable over US 2021/0082767 (“Kim”) in view of US 2017/0040214 (“Lai”).
Claim 1 reads,
1. A method of manufacturing a semiconductor device, the method comprising steps of:
[1] providing a semiconductor substrate having one or more trenches;
[2] forming a gate insulating layer on the semiconductor substrate inside the one or more trenches; and
[3] forming a buried gate electrode layer on the gate insulating layer to at least partially fill the one or more trenches,
[4a] wherein the step of forming the buried gate electrode layer comprises a step of repeating a unit cycle a plurality of times, the unit cycle comprising
[4b] an atomic layer deposition (ALD) process for forming a conductive layer on the gate insulating layer to serve as the buried gate electrode layer, and
[4c] an atomic layer etching (ALE) process for preferentially etching portions of the conductive layer formed near the one or more trenches and portions of the conductive layer formed on upper ends of the one or more trenches over other portions of the conductive layer inside the one or more trenches.
With regard to claim 1, Kim discloses, generally in Figs. 3A-3H,
1. A method of manufacturing a semiconductor device 100 [¶ 48], the method comprising steps of:
[1] providing a semiconductor substrate 11 [¶¶ 28, 49] having one or more trenches 15 [¶ 50; Fig. 3A];
[2] forming a gate insulating layer 17 on the semiconductor substrate 11 inside the one or more trenches 15 [¶ 52; Fig. 3B]; and
[3] forming a buried gate electrode layer 18 [e.g. tungsten (¶ 53)] on the gate insulating layer 17 to at least partially fill the one or more trenches 15 [¶¶ 53, 55; Figs. 3C-3D],
[4a] wherein the step of forming the buried gate electrode layer 18 [e.g. tungsten] comprises a step of repeating a unit cycle a plurality of times, the unit cycle comprising
[4b] an atomic layer deposition (ALD) process for forming a conductive layer 18' on the gate insulating layer 17 to serve as the buried gate electrode layer 18 [¶ 53], and
[4c] … [not taught] …
With regard to feature [4c] of claim 1,
[4c] an atomic layer etching (ALE) process for preferentially etching portions of the conductive layer formed near the one or more trenches and portions of the conductive layer formed on upper ends of the one or more trenches over other portions of the conductive layer inside the one or more trenches.
Kim does not teach that the unit cycle includes ALE in addition to ALD.
Lai is directed filling trenches with tungsten 216 that prevents void formation due to overhang at the opening of the trench 212 that includes unit cycles of ALD and ALE (Lai: ¶¶ 31-57; Figs. 1-3, 5). With regard to features [4a]-[4c] of claim 1, Lai teaches,
[4a] wherein the step of forming the buried …[tungsten]… layer 216 [¶ 35; Fig. 2] comprises a step of repeating a unit cycle a plurality of times [Fig. 3; ¶¶ 36-57; ¶ 61], the unit cycle comprising
[4b] an atomic layer deposition (ALD) process [step 303 in Fig. 3] for forming a conductive [i.e. tungsten] layer 216 … [¶¶ 43, 61; frame 201 in Fig. ], and
[4c] an atomic layer etching (ALE) process [step 305(=315 + 335) in Fig. 3 (¶ 61)] for preferentially etching portions of the conductive layer 216 formed near the one or more trenches 212 and portions of the conductive layer 216 formed on upper ends of the one or more trenches 212 over other portions of the conductive layer 216 inside the one or more trenches 212 [as shown in frames 201 to 203 to 205 in Fig. 2 (¶ 35)].
The process of ALD/ALE tungsten filling taught in Lai further teaches the process limitations of claims 2-5, 7, 8, and 13, as follows:
2. The method of claim 1, wherein the ALE process within the unit cycle comprises steps of:
[1] adsorbing an etchant onto the conductive layer 216 [e.g. Cl2 (frame 172b in Fig. 1; frame 203 in Fig. 2 (¶ 35); step 315 in Fig. 3 (¶¶ 53, 61)]; and
[2] removing portions of the conductive layer 216 from the … substrate 210 [¶ 35] by activating portions of the etchant adsorbed onto the conductive layer 216 by supplying ions [e.g. Ar+ in frame 172d in Fig. 1; frame 203 in Fig. 2; step 335 in Fig. 3] onto the conductive [tungsten] layer 216 in a direction perpendicular [i.e. “normal”] to the … substrate 210 [¶¶ 3, 5, 58-59].
3. The method of claim 2, wherein the etchant comprises a halogen-containing gas [e.g. Cl2, supra; ¶¶ 5, 14].
4. The method of claim 2,
[1] wherein the step of adsorbing the etchant [e.g. Cl2] comprises a step of supplying a first purge gas [e.g. Ar, Ne, He (¶ 46)] onto the … substrate 210 [525A in Fig. 5 (¶ 62); frame 172c in Fig. 1 (¶ 33)] after the step of supplying the etchant onto the substrate 210 [515A in Fig. 5 (¶ 62); 172b in Fig. 1 (¶ 33)], and
[2] wherein the step of removing the portions of the conductive layer 216 comprises a step of supplying a second purge gas [e.g. Ar, Ne, He (¶ 46)] onto the … substrate 210 [¶ 60; 545A in Fig. 5 (¶ 62); 172e in Fig. 1 (¶ 33)] after the step of supplying the ions [Ar+] onto the … substrate 210 [535A in Fig. 5 (¶ 62); 172d in Fig. 1 (¶ 33)].
5. The method of claim 4, wherein the first and second purge gases comprise an inert gas [e.g. Ar, Ne, He (¶ 46)].
7. The method of claim 6, wherein the ions comprise argon (Ar) ions [e.g. Ar+ in frame 172d in Fig. 1; frame 203 in Fig. 2].
8. The method of claim 2, wherein, in the step of removing the portions of the conductive [i.e. tungsten] layer 216,
[1] the ions [e.g. Ar+] activate portions of the etchant [Cl2] adsorbed onto the conductive layer 216 near the one or more trenches 212, portions of the etchant adsorbed onto the conductive layer 216 on upper side walls of the one or more trenches 212, and portions of the etchant adsorbed onto the conductive layer 216 on lower ends of the one or more trenches, based on an ion bombardment effect [¶¶ 53, 55; step 335 in Fig. 3; frame 203 in Fig. 2], and
[2] the activated portions of the etchant preferentially remove portions of the conductive layer 216 near the one or more trenches 212, portions of the conductive layer 216 on the upper side walls of the one or more trenches 212, and portions of the conductive layer 216 on the lower ends of the one or more trenches over other portions of the conductive layer 216 [¶¶ 53, 55; step 335 in Fig. 3; frame 205 in Fig. 2].
13. The method of claim 1, wherein, in the step of repeating the unit cycle the plurality of times, a time of the ALD process within the unit cycle is adjusted in such a manner that portions of the conductive layer on both side walls at the upper ends of the one or more trenches 212 are not in contact with but spaced apart from each other [as shown in the sequence of frames in Fig. 2].
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to use the ALD/ALE tungsten-deposition process taught in Lai (i.e. including all of the process steps and parameters taught by Lai explained in features [4a]-[4c] of claim 1 and claims 2-5, 7, and 8) in place of the process in Kim that uses only ALD, in order to form a void-free tungsten gate electrode. As such, Lai may be seen as an improvement to Kim in this aspect. (See MPEP 2143.)
This is all of the limitations of claims 1-5, 7, 8, and 13.
Claim 6 reads,
6. The method of claim 2, wherein the ions supplied during the ALE process have an energy lower than or equal to 10 eV (and higher than 0 eV).
With regard to the energy provided to the Ar+, Lai explains that the “bias power is selected to prevent sputtering” (infra) of the tungsten metal, stating in this regard,
[0057] During removal, a bias may be optionally applied to facilitate directional ion bombardment. The bias power is selected to prevent sputtering but allow the removal gas [e.g. Ar] to enter the feature and etch the tungsten at or near the opening of the feature to thereby open it. The bias power may be selected depending on the threshold sputter yield of the activated removal gas with the deposited metal on the substrate. Sputtering as used herein may refer to physical removal of at least some of a surface of a substrate. Ion bombardment may refer to physical bombardment of a species onto a surface of a substrate.
[0059] The figure shows the calculated normal incidence sputter yield of tungsten with argon atoms versus argon ion energy (or threshold bias power). The calculation used a value of 32 eV for the sputter threshold. Slightly above the threshold, namely at 40 eV argon ion energy, the sputter yield seems to be about 0.001 atoms/ion. However, at 80 eV ion energy, it has increased by a factor of 30. This example curve indicates the maximum argon ion energy sufficient to etch the metal while preventing sputtering of argon on the substrate. While FIG. 4 provides a qualitative representation of a sputter threshold curve, a sputter threshold may be experimentally determined for a particular system and maximum tolerable sputter yield. For one system, sputtering of tungsten is observed at 80 Vb for argon ions. As such, the bias power during tungsten removal using argon ions may be set at less than about 80 Vb, or less than about 50 Vb, or between about 50 Vb and 80 Vb. In some embodiments, operation 335 may be performed above the threshold bias power if some small amount of sputtering is tolerable. There may also be a removal threshold voltage, below which removal does not occur, depending on the particular process. It should be noted that the sputter threshold varies according to the metal, metal compound, or other material to be etched.
(Lai: ¶¶ 57, 59; emphasis added)
Thus, Lai explains that the bias power may be “less than about 50 Vb” giving than Ar+ ions an energy less than about 50 eV, which overlaps the claimed range of greater than 0 eV but less than 10 eV. However, the data discussed in association with Fig. 4 of Lai is a calculation (id.). Lai further explains that the actual values can be determined “experimentally determined” (id.) and varies according to the sputtering “system” (id.); therefore, the bias power depends upon the sputtering system used for the ALE process.
With the above evidence in mind, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to use an Ar+ ions an energy “less than about 50 eV” in the process of Lai used in Kim because Lai suggests this range.
In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); MPEP 2144.05(I)). In such a situation, Applicant must show that the particular ranges are critical, generally by showing that the claimed range achieves unexpected results relative to the prior art range. See In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). (See MPEP 2144.05(III)(A); emphasis added.)
With regard to claim 9, Kim in view of Lai further teaches,
9. The method of claim 1,
[1] wherein the one or more trenches 15 [of Kim] are further defined by a hard mask layer 16 [of Kim] formed on the semiconductor substrate 11 [of Kim] outside the one or more trenches 15 [Kim: Fig. 3A],
[2] wherein, in the ALD process [of Lai used in Kim], the conductive [tungsten] layer 18 [of Kim/Lai] is further formed on the hard mask layer 16 [because the ALD deposition is non-selective as shown in Fig. 2 of Lai], and
[3] wherein, in the ALE process [of Lai used in Kim], portions of the conductive [tungsten] layer formed on the hard mask layer 16 are removed [because the tungsten deposited on the top surface of the substrate in Lai is removed during ALE, as shown in frames 203 to 205 of Lai].
With regard to Kim further discloses,
12. The method of claim 1, wherein lower portions of the one or more trenches 15 have a U shape [Figs. 3A-3H].
B. Claims 10, 11, and 17-20 are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Lai, as applied to claim 1, above, and further in view of US 2011/0003468 (“Song”).
Claim 10 reads,
10. The method of claim 1, wherein the step of forming the buried gate electrode layer further comprises a step of performing wet etching to etch portions of the conductive layer remaining on both side walls at the upper ends of the one or more trenches after the step of repeating the unit cycle the plurality of times.
The prior art of Kim in view of Lai, as explained above, teaches each of the limitations of claim 1.
Kim discloses that, in the step of forming the buried tungsten gate electrode layer 18, the tungsten layer 18' deposited by ALD (Kim: Fig. 3C) is etched back using a dry etch (Kim: Fig. 3D; ¶ 55). The ALE process of Lai used in Kim is also a dry etch process. In addition, as shown frame 205 in Fig. 2 of Lai, the ALE process, removes some but not all of the tungsten deposited on the to surface and sidewalls of the partially filled via. Thus, even after one having ordinary skill in the art at least partially fills the gate trench 15 of Kim using the ALD/ALE process of Lai, there would still be some tungsten on the top and upper sidewall surfaces, that would need to be removed by the dry etching in Kim to set the height of the bottom portion of the gate electrode of Kim that is tungsten 18.
Neither of Kim and Lai teaches using a wet each after the dry-etch recessing process to recess the tungsten layer 18'.
Song, like Kim, is drawn to forming a buried tungsten gate electrode 27E. Song teaches a recessing of the tungsten that includes a dry etch (Song: ¶¶ 36-37; Figs. 3H to 3I) followed by a wet cleaning/etching that etches both TiN and tungsten from the sidewalls (Song: ¶¶ 38-42; Fig. 5A).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to perform a wet cleaning/etching using the sulfuric acid and hydrogen peroxide solution of Song, after the dry recess etching of Kim and or Kim/Lai because Song teaches that it is known to perform a wet cleaning/etching after a dry recess etch of tungsten. The benefit would be to remove any tungsten residue above a height within the gate trench that is unwanted, as taught in Song. As such, Song may be seen as a benefit to Kim in this aspect. (See MPEP 2143.)
This is all of the limitations of claim 10.
With regard to claim 11, Kim further discloses,
11. The method of claim 10, wherein the step of forming the buried gate electrode layer further comprises a step of forming a polysilicon layer 21' on the conductive layer 18 to fill the one or more trenches 15 [Kim: Fig. 3H; ¶ 64, last sentence: “the upper gate layer 21′ may be made of or include a low work function metal or low work function polysilicon.”].
Claim 17 reads,
17. A method of manufacturing a semiconductor device, the method comprising steps of:
[1] providing a semiconductor substrate having one or more trenches defined by a hard mask layer;
[2] forming a gate insulating layer on the semiconductor substrate inside the one or more trenches; and
[3] forming a buried gate electrode layer on the gate insulating layer to at least partially fill the one or more trenches,
[4a] wherein the step of forming the buried gate electrode layer comprises steps of: repeating a unit cycle a plurality of times, the unit cycle comprising
[4b] an atomic layer deposition (ALD) process for forming a conductive layer on the gate insulating layer and the hard mask layer to serve as the buried gate electrode layer, and
[4c] an atomic layer etching (ALE) process for preferentially etching portions of the conductive layer formed near the one or more trenches and portions of the conductive layer formed on upper ends of the one or more trenches over other portions of the conductive layer inside the one or more trenches;
[5] performing wet etching to etch portions of the conductive layer remaining on both side walls at the upper ends of the one or more trenches; and
[6] forming a polysilicon layer on the conductive layer to fill the one or more trenches, and
[7a] wherein the ALE process within the unit cycle comprises steps of:
[7b] adsorbing an etchant onto the conductive layer; and
[7c] removing portions of the conductive layer from the semiconductor substrate by activating portions of the etchant adsorbed onto the conductive layer by supplying ions onto the conductive layer in a direction perpendicular to the semiconductor substrate.
Claim 17 is a combination of the limitations recited in claims 1, 2, 6, 10, and 11, each of said limitations addressed above.
Claim 18 reads,
18. The method of claim 17,
[1] wherein the step of adsorbing the etchant comprises a step of supplying a first purge gas onto the semiconductor substrate after the step of supplying the etchant onto the semiconductor substrate, and
[2] wherein the step of removing the portions of the conductive layer comprises a step of supplying a second purge gas onto the semiconductor substrate after the step of supplying the ions onto the semiconductor substrate.
See discussion under claim 4 which applies equally here.
Claim 19 reads,
19. The method of claim 17, wherein, in the step of repeating the unit cycle the plurality of times, a time of the ALD process within the unit cycle is adjusted in such a manner that portions of the conductive layer on both side walls at the upper ends of the one or more trenches are not in contact with but spaced apart from each other.
See discussion under claim 13 which applies equally here.
Claim 20 read
20. The method of claim 17,
[1] wherein the ions supplied during the ALE process have an energy lower than or equal to 10 eV (and higher than 0 eV), and
[2a] wherein, in the step of removing the portions of the conductive layer,
[2b] the ions activate portions of the etchant adsorbed onto the conductive layer near the one or more trenches, portions of the etchant adsorbed onto the conductive layer on upper side walls of the one or more trenches, and portions of the etchant adsorbed onto the conductive layer on lower ends of the one or more trenches, based on an ion bombardment effect, and
[2c] the activated portions of the etchant preferentially remove portions of the conductive layer near the one or more trenches, portions of the conductive layer on the upper side walls of the one or more trenches, and portions of the conductive layer on the lower ends of the one or more trenches over other portions of the conductive layer.
Claim 20 is a combination of the limitations recited in claims 6 and 8, , each of said limitations addressed above.
V. Pertinent Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Each of the following references is cited for teaches a buried gate electrode including a lower tungsten portion and an upper polysilicon portion directly contacting the tungsten portion:
(1) US 2021/0183865 (“Neelapala”): 106 may be tungsten and 136 may be polysilicon (¶ 22)
(2) US 2020/0168611 (“Jeon”): 110M may be tungsten (¶ 62) and 110P may be polysilicon (¶ 63)
(3) US 2016/0056160 (“Jang”): 210 may be tungsten (¶¶ 38-39) and 212a may be polysilicon (¶ 41)
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIK KIELIN whose telephone number is (571)272-1693. The examiner can normally be reached Mon-Fri: 10:00 AM-7:00 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Wael Fahmy can be reached on 571-272-1705. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
Signed,
/ERIK KIELIN/
Primary Examiner, Art Unit 2814