DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Regarding claims 1-14 are rejected under 35 U.S.C. 112(b), applicant amendment has been fully considered. The amendment overcomes the 35 U.S.C. 112(b) rejections, hence 35 U.S.C. 112(b) rejection is withdrawn for claims 1-14.
Applicant's arguments filed on 01/21/2026, with respect to claims 1 and 11 have been fully considered but they are not persuasive. The Examiner respectfully disagrees for at least the following reasons:
Applicant argues Khandros fails to teach the FPCB configured to embed a plurality of circuit lines. However, in Figs. 7-8, Khandros clearly shows that interposer 42 has circuit lines (terminals and lead) 48/50/56, and the contact end 56 is embedded in the interposer 42 with encapsulation 60.
Applicant further argues that Khandros fails to teach the FPCB extends to enable electrical connection to an outside of the power module. However, in ¶ [0059] and Figs. 1-2, Khandros clearly teaches interposer 42 has plurality of circuit lines 48/50/56 and the circuit line 48/50/56 of the interposer 42 are clearly shown to extend across surface 46 as shown in Fig. 2 and 7-8 to enable the electrical connection of the outside module via bump 52, 26 and 34. The applicant’s argument is not commensurate in scope with claim 1 as presently written.
Hence, the rejection under 35 U.S.C. 103 has been maintained.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5 are rejected under 35 U.S.C. 103 as being unpatentable over Khandros (US 20050218495 A1).
Re: Independent Claim 1 (Currently amended), Khandros discloses a power module comprising:
a substrate (Khandros, Fig 1, substrate 20);
chips connected to the substrate (Khandros, Fig 1, chips 28 connected to 20);
and a Flexible Printed Circuit Board (FPCB) provided between the substrate and the chips (although Khandros does not explicitly disclose FPCB, however, in Fig. 1, flexible sheetlike dielectric interposer 42 is disposed between the chip and the substrate; it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to recognize that this interposer is a flexible circuit board layer), and
being configured to embed a plurality of circuit lines, wherein the plurality of circuit lines include a plurality of patterns formed for electrical connection of each of the chips (Khandros, Fig. 2 and Fig. 7, ¶ [0059], patterned conductive sheet (with aperture 54) on the interposer and it clearly shows that interposer 42 has circuit lines (terminals and lead) 48/50/56, and the contact end 56 is embedded in the interposer 42 with encapsulation 60), and wherein the FPCB extends to enable electrical connection to an outside of the power module (Khandros, in Fig 1/ Fig 2. ¶ [0059], teaches interposer 42 has plurality of circuit lines 48/50/56 and the circuit line 48/50/56 of the interposer 42 are clearly shown to extend across surface 46 as shown in Fig. 2 and 7-8 to enable the electrical connection of the outside module via bump 52, substrate conductors 26 and external pins 34).
Re: Claim 2 (Original), Khandros discloses all the limitations of claim 1 on which this claim depends. Khandros further discloses,
wherein the FPCB includes the plurality of chips (Khandros, Fig 1, chips 28 and 30), and the circuit lines form the patterns for the electrical connection of each chip (Khandros, Fig. 2, ¶ [0059], the interposer has patterned conductors (e.g., terminals 48 and leads 50), each lead having a contact end connected to chip contact 40 and a terminal end connected to a substrate pad 24).
Re: Claim 3 (Original), Khandros discloses all the limitations of claim 1 on which this claim depends. Khandros further discloses,
wherein, in a state of being provided between the substrate and the chips (Khandros , Fig. 1/ Fig. 2, 42 is between chip 28 and substrate 20), the FPCB includes through holes formed on the FPCB at respective portions of the FPCB, which match the chips (Khandros, Fig. 2, ¶ [0060], apertures 54 in the interposer 42; the chip is aligned with the interposer so that each aperture 54 is aligned with a contact 40 of the chip, and the contacts are received in the apertures 54. These apertures are through-holes in the flexible interposer located within the chip footprint area).
Re: Claim 4 (Original), Khandros discloses all the limitations of claim 3 on which this claim depends. Khandros further discloses,
wherein, in the FPCB, each size of the through holes is formed smaller than the respective chips (Khandros, Fig 2, aperture 54 is smaller than the respective chip 28), so that portions to which the chips and the circuit lines are connected are covered and insulated (Khandros, Fig. 2, ¶ [0060], Khandros shows patterned conductors on the interposer (leads 50/terminals 48) bonded to the chip contacts 40 within each aperture, after which encapsulant 60 is deposited in the aperture 54 to cover/protect the bond area).
Re: Claim 5 (Currently amended), Khandros discloses all the limitations of claim 1 on which this claim depends. Khandros further discloses,
wherein the plurality of circuit lines are configured to be insulated in the FPCB (Khandros, in Figs. 2 and 7, and ¶ [0105], the interposer itself may include multiple layers of terminals and leads 48/50/56 and further teaches that the multiple layers of terminals and leads are separated from one another by intermediate dielectric layers, i.e., the plurality of circuit lines are insulated in the FPCB).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Khandros (US 20050218495 A1) in view of Jeon (US 7121874 B1).
Re: Claim 6 (Original), Khandros discloses all the limitations of claim 1 on which this claim depends. Khandros is silent regarding,
wherein a connector is provided at a terminal of the FPCB, and the respective circuit lines electrically connected to the chips are connected to the connector.
However, Jeon teaches wherein a connector is provided at a terminal of the FPCB, and the respective circuit lines electrically connected to the chips are connected to the connector (Khandros teaches FPCB/interposer 42 carrying patterned circuit lines (leads 50/terminals 48) that connect each chip contact 40 to interposer terminals 48 (i.e., chip-connected circuit lines terminating at the FPCB's terminal region). Jeon teaches, in Fig. 4, flexible printed circuit (FPC) edge connector 100 where an edge of an FPC is insertable into a slot and contact beams press on corresponding FPC conductors, establishing an electrical path from an FPC conductor, through the connector, to a PCB conductor. i.e., a connector provided at a terminal of the FPCB with the FPCB conductors connected to the connector).
Khandros and Jeon both teach flexible Circuit board, hence analogous art. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to terminate Khandros's FPCB at a standard FPC edge/ZIF connector taught by Jeon in order to improve the manufacturability and reworkability and testing of the overall PCB assembly (Jeon, Column 8, lines 35-37).
Claims 7-9 are rejected under 35 U.S.C. 103 as being unpatentable over Khandros (US 20050218495 A1) in view of Park (US 20210265235 A1).
Re: Claim 7 (Original), Khandros discloses all the limitations of claim 1 on which this claim depends. Khandros is silent regarding,
wherein the substrate includes an upper substrate and a tower substrate, wherein the chips are connected to the upper substrate or the lower substrate,
wherein spacers on which the respective chips are disposed are provided to be connected to the upper substrate and the lower substrate,
and wherein the FPCB is provided between the chips and the upper substrate or the lower substrate.
However, Park teaches wherein the substrate includes an upper substrate and a lower substrate (Park, Fig 2, ¶¶ [0045] - [0046], upper substrate 100 and lower substrate 200), wherein the chips are connected to the upper substrate or the lower substrate (chip 300 connected to 100 or 200),
wherein spacers on which the respective chips are disposed are provided to be connected to the upper substrate and the lower substrate (Park, Fig 2, ¶¶ [0043], [0048], spacer 400 is disposed between the upper and lower substrate (and thus connected to) the upper and lower substrate, with chips 300 disposed between the spacer and the upper or lower substrate).
Khandros teaches wherein the FPCB is provided between the chips and the upper substrate or the lower substrate (Khandros Fig 1/Fig.2, flexible sheet like dielectric interposer that is assembled between chip and the substrate, with terminals bonded to substrate pads and a gap between interposer and substrate i.e., the flexible printed structure sits between the chip and the substrate to make electrical connections and provide insulation).
Khandros and Park both teach power modules, hence analogous art. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to combine the flexible interposer of Khandros and double-sided module of Park in order to achieve heat dissipation characteristic and durability (Park, ¶ [0002]).
Re: Claim 8 (Original), Khandros and Park disclose all the limitations of claim 7 on which this claim depends.
Khandros and Park further teach,
wherein the chips and the FPCB are provided between the upper substrate and the spacers (Park teaches, in Fig 2, a double-sided cooling power module having upper substrate 100, a lower substrate 200, and spacer 400, with a stacked structure in which the chip is disposed between the spacer and the upper substrate. Khandros teaches flexible interposer 42 disposed between chip 28 and substrate 20, used to route chip connections via leads 50/ terminals 48),
the upper substrate is disposed to be connected to an upper side of the FPCB (Khandros, in Fig 2., ¶ [0060] teaches that the interposer 42 has a first face 44 (chip side) and a second face 46 (substrate side), and that the assembly is oriented so that the second face (with terminals 48) faces the substrate and is bonded to substrate pads 24. Thus, the substrate connects to the "upper side" of the interpose. Applying this teaching of Khandros in Park's structure, it would be obvious that the upper substrate 100 would be connected to the upper side of the FPCB),
and the chips are disposed to be connected to a lower side of the FPCB (Khandros teaches chip 28 aligned so that the contacts 40 are received in apertures 54 of the interposer 42 and bonded to lead contact ends 56 at the first face 44-i.e., the chip connects on the lower side of the FPCB/interposer).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Khandros' FPCB into the chip-upper-substrate region of Park such that the leads and the interposer are constructed and arranged so that the contact ends of the leads are moveable relative to the terminals at least to the extent required to compensate for differential thermal expansion of components, and most preferably, the interposer itself is flexible so as to facilitate such movement (Khandros, ¶ [0016]).
Re: Claim 9 (Original), Khandros and Park disclose all the limitations of claim 7 on which this claim depends.
Khandros further teaches,
wherein, in a state of being provided between the upper substrate and the chips, the FPCB includes through holes formed on the FPCB at respective portions of the FPCB, which match the chips (As shown in claim 7, the chip-upper-substrate/spacer geometry is met. The additional limitation " in a state of being provided between the upper substrate and the chips, the FPCB includes through holes formed on the FPCB at respective portions of the FPCB, which match the chips" is taught by Khandros, which discloses a flexible interposer/FPCB 42 with apertures (through-holes) 54 extending through the film and aligned to the chip's features (e.g., contacts 40) within the chip footprint (Figs. 1,2, ¶ [0060], terminals 48/leads 50 around the openings).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Khandros (US 20050218495 A1) in view of Park (US 20210265235 A1) and further in view of Jeon (US 7121874 B1).
Re: Claim 10 (Original), Khandros and Park disclose all the limitations of claim 7 on which this claim depends. Both Khandros and Park are silent regarding,
wherein a connector is provided at a terminal of the FPCB, and the respective circuit lines electrically connected to the chips are connected to the connector.
However, Jeon teaches, wherein a connector is provided at a terminal of the FPCB, and the respective circuit lines electrically connected to the chips are connected to the connector (Khandros teaches FPCB/interposer 42 carrying patterned circuit lines (leads 50/terminals 48) that connect each chip contact 40 to interposer terminals 48 (i.e., chip-connected circuit lines terminating at the FPCB's terminal region). Jeon teaches, in Fig. 4, flexible printed circuit (FPC) edge connector 100 where an edge of an FPC is insertable into a slot and contact beams press on corresponding FPC conductors, establishing an electrical path from an FPC conductor, through the connector, to a PCB conductor. i.e., a connector provided at a terminal of the FPCB with the FPCB conductors connected to the connector).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to terminate Khandros' FPCB in view of Park at a standard FPC edge/ZIF connector taught by Jeon in order to improve the manufacturability and reworkability and testing of the overall PCB assembly (Jeon, Column 8, lines 35-37).
Claims 11-13 are rejected under 35 U.S.C. 103 as being unpatentable over Park (US 20210265235 A1) in view of Khandros (US 20050218495 A1).
Re: Independent Claim 11 (Currently amended), Park discloses a power module comprising:
an upper substrate and a lower substrate (Park, Fig 2, ¶¶ [0045] - [0046], upper substrate 100 and lower substrate 200);
chips connected to the upper substrate or the lower substrate (chip 300 connected to 100 or 200);
spacers provided to be connected to the upper substrate and the lower substrate and on which the respective chips are disposed (Park, Fig 2, ¶¶ [0043], [0048], spacer 400 is disposed between the upper and lower substrate (and thus connected to) the upper and lower substrate, with chips 300 disposed between the spacer and the upper or lower substrate).
Park is silent regarding, a Flexible Printed Circuit Board (FPCB) provided between the chips and the upper substrate or the lower substrate, being configured to embed a plurality of circuit lines, wherein the plurality of circuit lines include a plurality of patterns formed for electrical connection of each of the chips, and wherein the FPCB extends to enable electrical connection to an outside of the power module.
However, Khandros teaches a Flexible Printed Circuit Board (FPCB) provided between the chips and the upper substrate or the lower substrate (although Khandros does not explicitly disclose FPCB, however, in Fig. 1, flexible sheetlike dielectric interposer 42 is disposed between the chip and the substrate; it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to recognize that this interposer is a flexible circuit board layer), and
being configured to embed a plurality of circuit lines, wherein the plurality of circuit lines include a plurality of patterns formed for electrical connection of each of the chips (Khandros, Fig. 2 and Fig. 7, ¶ [0059], patterned conductive sheet (with aperture 54) on the interposer and it clearly shows that interposer 42 has circuit lines (terminals and lead) 48/50/56, and the contact end 56 is embedded in the interposer 42 with encapsulation 60), and wherein the FPCB extends to enable electrical connection to an outside of the power module (Khandros, in Fig 1/ Fig 2. ¶ [0059], teaches interposer 42 has plurality of circuit lines 48/50/56 and the circuit line 48/50/56 of the interposer 42 are clearly shown to extend across surface 46 as shown in Fig. 2 and 7-8 to enable the electrical connection of the outside module via bump 52, substrate conductors 26 and external pins 34).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to adopt the flexible interposer/FPCB between the chip and substrate taught by Khandros in double-sided stack of Park in order to achieve the ability of the terminals to move with respect to the chip in directions parallel to the chip surfaces that provides compensation for differential thermal expansion of the chip and substrate (Khandros, ¶ [0011]).
Re: Claim 12 (Original), Park and Khandros disclose all the limitations of claim 11 on which this claim depends.
Park and Khandros further teach,
wherein the chips and the FPCB are provided between the upper substrate and the spacers (Park teaches, in Fig 2, a double-sided cooling power module having upper substrate 100, a lower substrate 200, and spacer 400, with a stacked structure in which the chip is disposed between the spacer and the upper substrate. Khandros teaches flexible interposer 42 disposed between chip 28 and substrate 20, used to route chip connections via leads 50/ terminals 48),
the upper substrate is disposed to be connected to an upper side of the FPCB (Khandros, in Fig 2., ¶ [0060] teaches that the interposer 42 has a first face 44 (chip side) and a second face 46 (substrate side), and that the assembly is oriented so that the second face (with terminals 48) faces the substrate and is bonded to substrate pads 24. Thus, the substrate connects to the "upper side" of the interpose. Applying this teaching of Khandros in Park's structure, it would be obvious that the upper substrate 100 would be connected to the upper side of the FPCB),
and the chips are disposed to be connected to a lower side of the FPCB (Khandros teaches chip 28 aligned so that the contacts 40 are received in apertures 54 of the interposer 42 and bonded to lead contact ends 56 at the first face 44 - i.e., the chip connects on the lower side of the FPCB/interposer).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Khandros's FPCB into the chip-upper-substrate region of Park such that the leads and the interposer are constructed and arranged so that the contact ends of the leads are moveable relative to the terminals at least to the extent required to compensate for differential thermal expansion of components, and most preferably, the interposer itself is flexible so as to facilitate such movement (Khandros, ¶ [0016]).
Re: Claim 13 (Original), Park and Khandros disclose all the limitations of claim 11 on which this claim depends.
Khandros further teaches,
wherein, in a state of being provided between the upper substrate and the chips, the FPCB includes through holes formed on the FPCB at respective portions of the FPCB, which match the chips (As shown in claim 11, the chip-upper-substrate/spacer geometry is met. The additional limitation " in a state of being provided between the upper substrate and the chips, the FPCB includes through holes formed on the FPCB at respective portions of the FPCB, which match the chips" is taught by Khandros, which discloses a flexible interposer/FPCB 42 with apertures (through-holes) 54 extending through the film and aligned to the chip's features (e.g., contacts 40) within the chip footprint (Figs 1,2, ¶ [0060], terminals 48/leads 50 around the openings).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Park (US 20210265235 A1) in view of Khandros (US 20050218495 A1) and further in view of Jeon (US 7121874 B1).
Re: Claim 14 (Original), Park and Khandros disclose all the limitations of claim 11 on which this claim depends.
Park and Khandros are silent regarding,
wherein a connector is provided at a terminal of the FPCB, and the respective circuit lines electrically connected to the chips are connected to the connector.
However, Jeon teaches wherein a connector is provided at a terminal of the FPCB, and the respective circuit lines electrically connected to the chips are connected to the connector (Khandros teaches FPCB/interposer 42 carrying patterned circuit lines (leads 50/terminals 48) that connect each chip contact 40 to interposer terminals 48 (i.e., chip-connected circuit lines terminating at the FPCB's terminal region). Jeon teaches, in Fig 4, flexible printed circuit (FPC) edge connector 100 where an edge of an FPC is insertable into a slot and contact beams press on corresponding FPC conductors, establishing an electrical path from an FPC conductor, through the connector, to a PCB conductor. i.e., a connector provided at a terminal of the FPCB with the FPCB conductors connected to the connector).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to terminate Khandros's FPCB at a standard FPC edge/ZIF connector taught by Jeon in order to improve the manufacturability and workability and testing of the overall PCB assembly (Jeon, Column 8, lines 35-37).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BIPANA ADHIKARI DAWADI whose telephone number is (571)272-4149. The examiner can normally be reached Monday-Friday 11:30am-7:30pm.
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/BIPANA ADHIKARI DAWADI/ Examiner, Art Unit 2898
/JESSICA S MANNO/SPE, Art Unit 2898
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