DETAILED ACTION
This Office Action is in response to Amendment filed January 30, 2026.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicants’ election without traverse of Group II, claims 1-6, 8 and 9, in the reply filed on March 27, 2026 is acknowledged.
Claim Objections
Claims 1, 3, 4 and 27 are objected to because of the following informalities:
On line 14 of claim 1, “bandcap” should be replaced with “bandgap”.
On lines 2, 4 and 5 of claim 3, “a barrier layer”, “a deep well layer” and “a shallow well layer” should be replaced with “the barrier layer”, “the deep well layer” and “the shallow well layer”, respectively.
On lines 3 and 4-5 of claim 3, “a potential well layer” should be replaced with “the potential well layer”.
On line 4 of claim 4, “a shallow well layer” should be replaced with “the shallow well layer”.
Regarding claim 27, there is no claim 27.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-6, 8 and 9 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
(1) Regarding claim 1, it is not clear how “the electron confinement layer comprises a deep well layer or shallow well layer (emphasis added)” as recited on line 9, and then “a changing range of a bandgap of a bandgap of the shallow well layer is greater than a bandgap of a potential well layer; and wherein the deep well layer comprises a region having a bandgap smaller than the bandgap of the potential well layer” as recited on lines 12-15, because (a) the former limitation recites that only one of the deep well layer and the shallow well layer is present inside the electron confinement layer, while the latter limitation requires both the shallow well layer and the deep well layer, and (b) therefore, it is not clear whether the former limitation is correct, and the latter limitation should be replaced with “a changing range of a bandgap of a bandgap of the shallow well layer is greater than a bandgap of a potential well layer; or wherein the deep well layer comprises a region having a bandgap smaller than the bandgap of the potential well layer (emphasis added)”, or the former limitation should be replaced with “the electron confinement layer comprises a deep well layer and shallow well layer (emphasis added)”.
(2) Also regarding claim 1, it is not clear what the limitation “at least one of the deep well layer or the shallow well layer comprises a material layer with a gradually changing bandgap (emphasis added)” recited on lines 10-11 suggests, because (a) the phrase “at least one” and the word “or” do not agree with each other grammatically, i.e. it should be a pair “at least one” and “and” that need to be used, and (b) even if arguendo Applicants had intended to claim that at least one of the deep well layer and the shallow well layer comprises a material layer with a gradually changing bandgap, it is not clear whether this hypothetical limitation suggests that both the deep well layer and the shallow well layer are formed of “a material layer with a gradually changing bandgap” or a single layer with a gradually changing bandgap, i.e. a single material composition for both the deep and shallow well layer, which would fail to comply with the written description requirement since, as indicated in Fig. 4 of current application, the deep well layer 32 and the shallow well layer 34 are formed of different material compositions.
(3) Further regarding claim 1, it is not clear whether “the potential well layer” recited on line 15 refers to “a potential well layer” recited on line 7 or “a potential well layer” recited on line 13, because (a) Applicants do not claim whether “a potential well layer” recited on line 7 is the same with or different from “a potential well layer” recited on line 13, and (b) “a potential well layer” recited on line 7 is associated with the growth temperature transition layer, and “a potential well layer” recited on line 13 is associated with the shallow well layer, and thus the electron confinement layer.
Claims 2-6, 8 and 9 depend on claim 1, and therefore, claims 2-6, 8 and 9 are also indefinite.
(4) Regarding claim 3, the amended claim 3 is indefinite for the same reason stated above, see the item (1) above, i.e. while claim 2 from which claim 3 depends requires either the first transition layer or the second transition layer, claim 3 recites that both the first and second transition layer should be present in the claimed semiconductor epitaxial structure. Claims 4-6, 8 and 9 depend on claim 3, and therefore, claims 4-6, 8 and 9 are also indefinite.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Hertkorn et al. (US 9,502,607) in view of Park et al. (US 9,537,055)
In the below prior art rejection of claim 1, the limitation “growth temperature transition layer” recited on line 6 is a product-by-process limitation that does not structurally distinguish the claimed invention over the prior art, because (a) the claimed invention of claim 1 is directed to a semiconductor epitaxial structure rather than a method of forming a semiconductor epitaxial structure, (b) in an epitaxial growth process, there are numerous growth parameters including a growth temperature, a growth rate, a material composition, a surface orientation, how a growth temperature varies during the epitaxial growth process, a growth technique such as MBE, CVD, ALD and sputtering, etc. that would determine the growth kinetics of the semiconductor epitaxial structure, (c) therefore, the limitation “growth temperature transition layer” does not correspond to any specific structure or any specific material composition since Applicants do not claim any of the other growth parameters that would also dictate what the “growth temperature transition layer” would be in the claimed semiconductor epitaxial structure, (d) if Applicants intend to claim a specific structure of the claimed “growth temperature transition layer”, Applicants first should claim all the other growth parameters such that one of ordinary skill in the art would be able to understand what the structure of the claimed “growth temperature transition layer” is, and (e) as can be seen clearly in Fig. 4 of current application, the cooling layer 31 and the heating layer 35, which Applicants claim as the growth temperature transition layer in claim 1, have the same barrier height as the barrier layer 36, and therefore, it does not appear that the growth temperature transition layer would have any distinct material property in comparison to the barrier layer 36 that is epitaxially grown at a constant temperature as shown in Fig. 3 of current application.
In the below prior art rejection of claims 4 and 5, the limitations “a growth temperature of the deep well layer is lowered from a growth temperature of the first transition layer to a temperature lower than a growth temperature of a potential well layer, or, a growth temperature of a shallow well layer is increased from a growth temperature of a potential well layer to a growth temperature of a heating layer” recited in claim 4, and “a growth temperature of the second transition layer is lower than a growth temperature of the barrier layer” recited in claim 5 are product-by-process limitations that do not structurally distinguish the claimed invention over the prior art for the same reasons that the limitation “growth temperature transition layer” recited in claim 1 is directed to a product-by-process limitation.
Note that a product by process claim is directed to the product per se, no matter how actually made, In re Hirao, 190 USPQ 15 at 17 (footnote 3). See also In re Brown, 173 USPQ 685; In re Luck, 177 USPQ 523; In re Fessmann, 180 USPQ 324; In re Avery, 186 USPQ 161; In re Wertheim, 191 USPQ 90 (209 USPQ 554 does not deal with this issue); and In re Marosi et al, 218 USPQ 289, all of which make it clear that it is the patentability of the final product per se which must be determined in a product by process claim, and not the patentability of the process, and that an old or obvious product by a new method is not patentable as a product, whether claimed in product by process claims or not. Note that applicant has the burden of proof in such cases, as the above case law makes clear.
Regarding claim 1, Hertkorn et al. disclose a semiconductor epitaxial structure (Figs. 1 and 2) (col. 2, lines 13-15, and col. 6, lines 53-57), comprising: an active region (2; active zone) (col. 5, line 39) comprising at least one quantum layer (composite layer of 20-24), because (a) as Applicants claim on line 4 of claim 1, “a quantum layer comprises barrier layers and potential well layers”, and (b) therefore, the composite layer of the quantum well layers 20, and the first through fourth barrier layers 21-24 shown in Fig. 2 of Hertkorn et al. can be referred to as a “quantum layer”, especially when the energy band structures of the composite layer of the quantum well layer 20 and the first barrier layer 21, and the composite layer of the quantum well layer 20 and the fourth barrier layer 24 shown in Fig. 2 of Hertkorn et al. look similar to the energy band structure shown in Fig. 4 of current application; wherein a quantum layer comprises barrier layers (21, 22, 23 and/or 24) (col. 5, lines 44 and 47-49) and potential well layers (20) (col. 5, line 45), and the barrier layers are alternately stacked with the potential well layers, and wherein the quantum layer (composite layer of 20-24) further comprises a growth temperature transition layer (portion of 22 or 23) between a barrier layer (remainder of 22 or 23) and a potential well layer (20), because (a) as discussed above, the limitation “growth temperature transition layer” is directed to a product by process limitation, and (b) Applicants’ cooling layer 31 and heating layer 35 or the growth temperature transition layers have the same barrier height as the barrier layer 36 as shown in Fig. 4 of current application, or an electron confinement layer (21 or 24) between a barrier layer ((remainder of) 22 or 23) and a potential well layer (20), because (a) as disclosed in paragraph [0029] of current application, Applicants originally disclosed that “the deep well layer 32 and the shallow well layer 34 are used for electron confinement to the barrier layer 36”, and (b) therefore, the first and fourth barrier layer 21/24 of Hertkorn et al. would also function as an electron confinement layer since the first and fourth barrier layer 21/24 of Hertkorn et al. have an energy level higher than the potential well layer 20; wherein the electron confinement layer comprises a deep well or a shallow well layer, which does not have to be considered because (a) Applicants claim that “the quantum layer further comprises a growth temperature transition layer between a barrier layer and a potential well layer, or an electron confinement layer between a barrier layer and a potential well layer (emphasis added)” on lines 6-8, and (b) therefore, the underlined limitation cited above does not have to be considered when the claimed semiconductor epitaxial structure comprises the claimed growth temperature transition layer, wherein at least one of the deep well layer or the shallow well layer comprises a material layer with a gradually changing bandgap, which does not have to be considered when the claimed semiconductor epitaxial structure does not include the electron confinement layer; wherein a changing range of a bandgap of the shallow well layer is greater than a bandgap of a potential well layer, which does not have to be considered when the claimed semiconductor epitaxial structure does not include the electron confinement layer; and wherein the deep well layer comprises a region having a bandcap smaller than the bandgap of the potential well layer, which does not have to be considered when the claimed semiconductor epitaxial structure does not include the electron confinement layer.
Hertkorn et al. differ from the claimed invention by not comprising a substrate, a first-type semiconductor layer, and a second-type semiconductor layer sequentially stacked on a surface of the substrate.
Park et al. disclose a semiconductor epitaxial structure (Fig. 1) (col. 4, line 66 - col. 5, line 4), comprising a substrate (101), a first-type semiconductor layer (122) (col. 4, lines 37-38), an active region (124) comprising at least one quantum layer (col. 4, lines 38-39 and 54-56), and a second-type semiconductor layer (126) (col. 4, lines 39-40) sequentially stacked on a surface of the substrate.
Since both Hertkorn et al. and Park et al. teach a semiconductor epitaxial structure, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the semiconductor epitaxial structure disclosed by Hertkorn et al. can comprise a substrate, a first-type semiconductor layer, and a second-type semiconductor layer sequentially stacked on a surface of the substrate as disclosed by Park et al., because (a) an epitaxial structure comprising a substrate, a first-type semiconductor layer, and a second-type semiconductor layer sequentially stacked on a surface of the substrate disclosed by Park et al. has been one of the most commonly employed light emitting device structures where a quantum layer is sandwiched by the first- and second-type semiconductor layer to improve light emitting efficiency by confining charge carriers inside the quantum layer, and (b) the first- and second-type semiconductor layer disclosed by Park et al. would also function as optical guide layers to further improve light emitting efficiency.
Regarding claims 2-6 and 9, Hertkorn et al. further disclose that the growth temperature transition layer (portion of 22 or 23) comprises a first transition layer grown at a gradually cooling temperature, which is also directed to a product by process limitation, or a second transition layer grown at a gradually heating temperature, which is also directed to a product by process limitation, because the limitations “cooling” and “heating” are directed to product-by-process limitations (claim 2), wherein a barrier layer comprises a first surface close to the first-type semiconductor layer, and a second surface close to the second-type semiconductor layer, the first transition layer and a deep well layer are disposed above the second surface, and a shallow well layer and the second transition layer are disposed below the first surface, because these limitations do not have to be considered when the quantum layer does not comprise the electron confinement layer as discussed above as well as claim 3 being indefinite as discussed above under 35 USC 112(b) rejections (claim 3), wherein a growth temperature of the deep well layer is lowered from a growth temperature of the first transition layer to a temperature lower than a growth temperature of a potential well layer, or, a growth temperature of a shallow well layer is increased from a growth temperature of a potential well layer to a growth temperature of the second transition layer, which is directed to a product-by-process limitation as discussed above especially when Applicants do not claim any other growth process parameters as well, because these limitations do not have to be considered when the quantum layer does not comprise the electron confinement layer as discussed above (claim 4), a growth temperature of a second transition layer (portion of 23 or 22) is lower than a growth temperature of the barrier layer (remainder of 22 or 23), which is directed to a product-by-process limitation as discussed above especially when Applicants do not claim any other growth process parameters (claim 5), either of the deep well layer (21 or 24) and the shallow well layer (24 or 21) comprises an AlxGayIn1-x-yN layer with a gradually changing composition of In, wherein each of x, y, and z is no less than 0 and no greater than 1, which implies that the AlxGayIn1-x-yN layer can be a binary or tertiary compound semiconductor such as InGaN when x = 0, see Fig. 2 of Hertkorn et al., and the limitation recited in claim 6 does not have to be considered when the quantum layer comprises the growth temperature transition layer rather than the electron confinement layer as discussed above (claim 6), and either the second transition layer (portion of 22 or 23) or the first transition layer (portion of 23 or 22) comprises an AlaGabN layer, wherein each of a and b is no less than 0 and no greater than 1, because the portions of the second and third barrier 22/23 are formed of GaN, to which the AlaGabN layer would correspond when a = 0 and b = 1, both of which read on the claimed ranges; or a thickness of the potential well layer is 3 times or more than a thickness of the deep well layer or the shallow well layer; or both the deep well layer and the shallow well layer have a thickness of 0~10 nm; or a thickness of the at least one barrier layer is 4 times or more than a thickness of the heating layer or cooling layer; or thicknesses of both the heating layer and the cooling layer are 0~20 nm (claim 9).
Response to Arguments
Applicants’ arguments with respect to claim 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
As discussed above in current Office Action, with the previously presented limitation “the quantum layer further comprises a growth temperature transition layer between a barrier layer and a potential well layer, or an electron confinement layer between a barrier layer and a potential well layer (emphasis added)” recited on lines 6-8 of the amended claim 1 in conjunction with the newly added limitations recited on lines 9-15 solely directed to the features of the electron confinement layer, Hertkorn et al. in view of Park et al. still reads on the amended claim 1, because any limitations involving the electron confinement layer and the deep and shallow well layer may not be considered as long as “the quantum layer further comprises a growth temperature transition layer between a barrier layer and a potential well layer”.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Wang et al., “Shallow–Deep InGaN Multiple-Quantum-Well System for Dual-Wavelength Emission Grown on Semipolar (11-22) Facet GaN,” Journal of ELECTRONIC MATERIALS 40 (2011) pp. 1572-1577.
Zhou et al., “InGaN quantum well with gradually varying indium content for high-efficiency GaN-based green light-emitting diodes,” Optics Letters 47 (2022) pp. 1291-1294.
Li et al., “Electroluminescence properties of InGaN/GaN multiple quantum well-based LEDs with different indium contents and different well widths,” Scientific Reports 7 (2017) 15301.
Karan et al., “Step multiple quantum well enabled performance enhancement in InGaN/GaN based light-emitting diodes,” Microsystem Technology 26 (2020) 26 pp. 3055-3062.
Applicants' amendment necessitated the new grounds of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicants are reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAY C KIM whose telephone number is (571) 270-1620. The examiner can normally be reached 8:00 AM - 6:00 PM EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joshua Benitez can be reached at (571) 270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JAY C KIM/Primary Examiner, Art Unit 2815
/J. K./Primary Examiner, Art Unit 2815 April 14, 2026
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