DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Status of Application
In response to Office action mailed 09/11/2025, Applicants amended claims 1-15, cancelled claims 16-25 and added claims 26-30 in the response filed 11/26/2025.
Claim(s) 1-15 and 26-30 are pending examination.
Response to Arguments
Applicants’ arguments with regards to the previous drawing objection is persuasive; as such the previous rejection is withdrawn.
Applicant’s arguments with respect to claim(s) 1-15 and 26-30 have been considered but are moot because the arguments do not apply to the new combination of references being used in the current rejection.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
1. Claim(s) 1-2, 5-9, 11-12, 14-15 and 26-29 are rejected under 35 U.S.C. 103 as being unpatentable over Yu et al. (PG Pub 2020/0176387; hereinafter Yu) and Yamasaki et al. (PG Pub 2017/0186684; hereinafter Yamasaki).
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Regarding claim 1, refer to the Examiner’s mark-up of Fig. 23 provided above, Yu teaches a semiconductor package comprising:
a first redistribution substrate 122 including a first body layer (124, 128, 132, and 136) and a first wiring layer (126, 130, and 134) in the first body layer (see Fig. 23);
a semiconductor chip 50 on the first redistribution substrate (see Fig. 23);
a through post 116 at a side (e.g. left side) of the semiconductor chip and on the first redistribution substrate (see Fig. 23); and
a second redistribution substrate 106 on the semiconductor chip and the through post (see Fig. 23), wherein the first wiring layer has a vertical cross-section of a trapezoid shape in which a top surface is narrower than a bottom surface thereof (see Fig. 23).
Although, Yu teaches the first redistribution substrate comprising a first wiring layer, he does not teach the structural details of the first redistribution layer such that the first wiring layer includes a first titanium seed layer.
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In the same field of endeavor, refer to the modified combined Fig. 1a and Fig. 1b provided above, Yamasaki teaches a first redistribution substrate 40 comprising: a first wiring layer 61/62/63/64; wherein the first wiring layer includes a first titanium seed layer 61, and wherein the first titanium seed layer has a vertical cross-section of a trapezoid shape in which a top surface is narrower than a bottom surface thereof (see Fig.1a/1b above).
In light of such teachings, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate a multi-layered wiring layer, as taught by Yamasaki, to aid in adhesion between different material composition.
Regarding claim 2, refer to the figures provided above, in the combination of Yu and Yamasaki, Yamasaki teaches the first wiring layer 61/62 includes a copper seed layer 62 on and contacting the top surface of the first titanium seed layer 61, and a copper wiring 63/64 on and contacting the first titanium copper seed layer (see Fig. 1a/1b), wherein a width of the copper seed layer (at any point along the slanted vertical the thickness is uniform) in a horizontal direction is uniform (see Fig. 1a/1b), and wherein the first body layer includes a polymer layer 44 (para [0022] and [0035]) is under the first titanium seed layer (see Fig. 1a/1b).
Regarding claim 5, refer to the figures provided above, in the combination of Yu and Yamasaki, Yamasaki teaches a side slope of the trapezoid structure shape is from about 65° to about 90° (see Fig. 1/1b).
Regarding claim 6, refer to the figures provided above, Yu and Yamasaki teach the first redistribution substrate 122 further includes, in the first body layer (124, 128, 132, and 136), a second wiring layer on a layer different (directly below the top layer) from a layer on which the first wiring layer is arranged (see Fig. 23), and wherein the second wiring layer includes a second titanium seed layer (61-Yamasaki), and wherein a vertical cross-section of the second titanium seed layer has a trapezoid shape in which a top surface is narrower than a bottom surface thereof. (see Fig. 1a/1b)
Regarding claim 7, refer to the figures provided above, in the combination of Yu and Yamasaki teach the first redistribution substrate 122 further includes, in the first body layer (124, 128, 132, and 136), a second wiring layer on a layer different (directly below the top layer) from a layer on which the first wiring layer is arranged (see Fig. 23), and wherein Yamasaki teaches the second wiring layer includes a second titanium seed layer 61 having a vertical cross-section of a reverse-trapezoid structure shape (as depicted in original Fig. 1a) and in which a top surface is wide and wider than a bottom surface is narrow thereof (see Fig. 1a).
Regarding claim 8, refer to the figures provided above, in the combination of Yu and Yamasaki teach the first redistribution substrate 122 further includes, in the first body layer (124, 128, 132, and 136), a second wiring layer on a layer different (directly below the top layer) from a layer on which the first wiring layer is arranged (see Fig. 23), and wherein the first wiring layer is adjacent to the second wiring layer and connected to the second wiring layer through via contacts (see figures provided above).
Regarding claim 9, refer to the figures provided above, Yu and Yamasaki teach the second redistribution substrate 106-Yu includes a second body layer 108 and a second wiring layer 106 in the second body layer (see Fig. 23), Yamasaki teaches the wiring layer includes a third titanium seed layer 61 having a vertical cross- section of a trapezoid structure shape (see Fig. 1a/1b) in which a top surface is narrow and narrower than a bottom surface is wide thereof (see Fig. 1a/1b).
Regarding claim 11, refer to the figures provided above, in the combination of Yu and Yamasaki, Yu teaches the semiconductor chip 50 includes an application processor chip (para [0012]), and the semiconductor package further includes an upper package 200 arranged on the second redistribution substrate 106 and connected to the second redistribution substrate through contact terminals 166, the semiconductor package including a memory chip (para [0061]).
Regarding claim 12, refer to the Examiner’s mark-up of Fig. 23 provided above, Yu teaches a semiconductor package comprising:
a first redistribution substrate 122;
semiconductor chips 50 on the first redistribution substrate (see Fig. 23);
through posts 116 on sides of the semiconductor chips (see Fig. 23) and on the first redistribution substrate (see Fig. 23);
a sealing material 120 surrounding it side surface surfaces of the through post posts, and covering and sealing the semiconductor chips (see Fig. 23);
a second redistribution substrate 106 on the sealing material and the through post posts (see Fig. 23); and
an external contact terminal 164 in a fan-out structure on a bottom surface of the first redistribution substrate (see Fig. 23),
wherein the first redistribution substrate and the second redistribution substrate each include a body layer (128,112 respectively) and a wiring layer (126, 110 respectively) in the body layer (see Fig. 23),
Although, Chen teaches the first redistribution substrate comprising a first wiring layer, he does not teach the structural details of the first redistribution layer such that the wiring layer includes a first titanium seed layer having a vertical cross- section of a trapezoid structure shape in which a top surface is narrow and narrower than a bottom surface is wide thereof, a copper seed layer on and contacting the top surface of the first titanium seed layer, and a copper wiring on and contacting a top surface of the copper seed layer, wherein a width of the copper seed layer is uniform, and wherein a side slope of the trapezoid structure first titanium seed laver is from about 65° to about 90°.
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In the same field of endeavor, refer to the modified combined Fig. 1a and Fig. 1b provided above, Yamasaki teaches a first redistribution substrate 40 comprising: a first wiring layer 61/62/63/64; the wiring layer includes a first titanium seed layer 61 having a vertical cross- section of a trapezoid shape (see Fig. 1a/1b) in which a top surface is narrower than a bottom surface is wide thereof (see Fig. 1a/1b), a copper seed layer 62 on and contacting the top surface of the first titanium seed layer (see Fig. 1a/1b), and a copper wiring 63/64 on and contacting a top surface of the copper seed layer (see Fig. 1a/1b), wherein a width of the copper seed layer is uniform, and wherein a side slope of the trapezoid structure first titanium seed laver is from about 65° to about 90° (see Fig. 1a/1b).
In light of such teachings, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate a multi-layered wiring layer, as taught by Yamasaki, to aid in adhesion between different material composition.
Regarding claim 14, refer to the figures provided above, in the combination of Yu and Yamasaki teach at least one of the first redistribution substrate 122 and the second redistribution substrate 106 further includes, in the body layer, an additional wiring layer (metal layer below the top layer) on a layer different from a layer on which the wiring layer is arranged (see figures cited above), and the additional wiring layer includes a second titanium seed layer 61 having a vertical cross-section of a trapezoid shape (see Fig. 1a/1b-Yu) in which a top surface is narrower than a bottom surface thereof (see Fig.1 a/1b) or a third titanium seed layer having a vertical cross-section of a reverse-trapezoid shape in which a top surface is wider than a bottom surface thereof.
Regarding claim 15, refer to the figures provided above, in the combination of Yu and Yamasaki teach the semiconductor chip 50 includes an application processor chip (para [0012]), and the semiconductor package further includes an upper package 200 arranged on the second redistribution substrate 106 and connected to the second redistribution substrate through contact terminals 166, the semiconductor package including a memory chip (para [0061]).
Regarding claim 26, refer to the Examiner’s mark-up of Fig. 23 provided above, Yu teaches a semiconductor package comprising:
a first redistribution substrate 122;
a semiconductor chip 50 on the first redistribution substrate (see Fig. 23);
a through post 116 at a side of the semiconductor chip and on the first redistribution substrate (see Fig. 23); and
a second redistribution substrate 106 on the semiconductor chip and the through post (see Fig. 23), wherein the first redistribution substrate includes a body layer (see Fig. 1a/1b).
Although, Chen teaches the first redistribution substrate comprising a first wiring layer, he does not teach the structural details of the first redistribution layer such that the wiring layer includes a first titanium seed layer having a vertical cross- section of a trapezoid structure shape in which a top surface is narrow and narrower than a bottom surface is wide thereof, a copper seed layer on and contacting the top surface of the first titanium seed layer, and a copper wiring on and contacting a top surface of the copper seed layer, wherein a width of the copper seed layer is uniform, and wherein a side slope of the trapezoid structure first titanium seed laver is from about 65° to about 90°.
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In the same field of endeavor, refer to the modified combined Fig. 1a and Fig. 1b provided above, Yamasaki teaches a first redistribution substrate 40 comprising: a first wiring layer 61/62/63/64; the wiring layer includes a first titanium seed layer 61 having a vertical cross- section of a trapezoid shape (see Fig. 1a/1b) in which a top surface is narrower than a bottom surface is wide thereof (see Fig. 1a/1b), a copper seed layer 62 on and contacting the top surface of the first titanium seed layer (see Fig. 1a/1b), and a copper wiring 63/64 on and contacting a top surface of the copper seed layer (see Fig. 1a/1b), wherein a width of the copper seed layer is uniform, and wherein a side slope of the trapezoid structure first titanium seed laver is from about 65° to about 90° (see Fig. 1a/1b).
In light of such teachings, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate a multi-layered wiring layer, as taught by Yamasaki, to aid in adhesion between different material composition.
Regarding claim 27, refer to the figures provided above, Yu and Yamasaki teach the first redistribution substrate 122 further includes a second wiring layer in the body layer (124, 128, 132, the second wiring layer includes a second titanium seed layer (61-Yamasaki) having a vertical cross-section having a trapezoid shape (see Fig. 1a/1b), a second copper seed layer 62 on and contacting a top surface of the second titanium seed layer 61, and a second copper wiring 63/64 on and contacting a top surface of the second copper seed layer (see Fig. 1a/1b).
Regarding claim 28, refer to the figures provided above, in the combination of Yu and Yamasaki, Yamasaki teaches the top surface of the second titanium seed layer (top of 2) has a third width and a bottom surface of the second titanium seed layer has a fourth width that is greater than the third width (see Fig. 1a/1b).
Regarding claim 29, refer to the figures provided above, in the combination of Yu and Yamasaki, Yamasaki teaches the top surface of the second titanium seed layer (top of 2) has a third width and a bottom surface of the second titanium seed layer has a fourth width that is smaller than the third width (see Fig. 1a-top portion).
2. Claim(s) 10 is rejected under 35 U.S.C. 103 as being unpatentable over Yu and Yamasaki, as applied to claim 1 above, and further in view of Noma et al. (PG Pub 2019/0067164; Noma).
Regarding claim 10, refer to the figures provided above, in the combination of Yu and Yamasaki, Yu teaches the through post 116. He does not teach the through post (aka via) "includes a fourth titanium seed layer having a vertical cross-section of a trapezoid structure in which a top surface is narrow and a bottom surface is wide."
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In the same field of endeavor, refer to Fig. 2a through Fig. 2s (emphasis on Fig. 2s provided above) provided above, Noma teaches a semiconductor device 100 (para [0014-0054]) comprising: a through post 211 (para [0045]); wherein the through post includes a titanium seed layer 212 (para [0046]) having a vertical cross-section of a trapezoid structure in which a top surface is narrow and a bottom surface is wide (see Fig. 2s).
In light of such teachings, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to line the TSV with titanium, as taught by Noma, to prevent undesired diffusion of metal.
Allowable Subject Matter
3. Claims 3-4, 13 and 30 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 3 contains allowable subject matter, because the prior art of record, either singularly or in combination, fails to disclose or suggest, in combination with the other elements in claim 3, an area of the top surface of the first titanium seed layer is smaller than an area of a bottom surface of the copper seed layer and is equal to or greater than 65% of the area of the bottom surface of the copper seed layer.
Claim 4 contains allowable subject matter, because the prior art of record, either singularly or in combination, fails to disclose or suggest, in combination with the other elements in claim 4, the first wiring layer is one of a plurality of the-first wiring layers that extend in a first direction on a certain layer in the first body layer and are spaced apart from one another in a second direction perpendicular to the first direction, and wherein the plurality of first wiring layer having layers each have a first width and being- are disposed at an interval less than or equal to 5 µm in the second direction.
Claim 13 contains allowable subject matter, because the prior art of record, either singularly or in combination, fails to disclose or suggest, in combination with the other elements in claim 13, the wiring layer of each of the first redistribution substrate and the second redistribution substrate is one of a plurality of the wiring layer extend layers extending in a first direction on a certain layer layers in the body layer of each of the first redistribution substrate and the second redistribution substrate, and wherein the plurality of wiring layers are spaced apart from one another in a second direction perpendicular to the first direction, wherein the wiring layer having layers each have a first width and being are at an interval less than or equal to 5 µm in the second direction, and wherein a second width of the bottom surface of the first titanium seed layer in the second direction is smaller than the first width of the-each wiring layer.
Claim 30 contains allowable subject matter, because the prior art of record, either singularly or in combination, fails to disclose or suggest, in combination with the other elements in claim 30, the through post includes a third titanium seed layer having a vertical cross- section having a trapezoid shape, a third copper seed layer on and contacting a top surface of the third titanium seed layer, and a copper post on and contacting a top surface of the third copper seed layer, wherein a top surface of the third titanium seed layer is narrower than a bottom surface thereof, and wherein widths of the third copper seed layer and the copper post are uniform.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Christina A Sylvia whose telephone number is (571)272-7474. The examiner can normally be reached on 8am-4pm (M-F).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Marlon Fletcher can be reached on 571-272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CHRISTINA A SYLVIA/Examiner, Art Unit 2817 /MARLON T FLETCHER/Supervisory Primary Examiner, Art Unit 2817