DETAILED ACTION
This action is responsive to the amendment and RCE received on 06/09/2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination (RCE) under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 06/09/2026 has been entered.
Priority
Acknowledgment is made of applicant's claim for priority under 35 U.S.C. 119(a)-(d) or (f), 365(a) or (b), or 386(a) based upon an application filed in PEOPLE'S REPUBLIC OF CHINA on 02/10/2023.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2022/0285609 A1; Huang et al.; 09/2022; (“Huang”) in view of US 2022/0285608 A1; Komura, Eiji; 09/2022; (“Komura”).
Regarding Claim 1. Huang discloses A magnetic random access memory cell (#100, Figure 6L, unit cell of a memory array #10 which may be a magnetic random access memory array according to [0020]), comprising:
a spin-orbit torque (SOT) layer (#104, Figure 6L, spin orbit torque (SOT) layer), through which a write current flows when performing a write operation on the magnetic random access memory cell ([0026], “a write current WP (i.e., the in-plane charge current as described above) may flow through the write transistor WT, the read transistor RT and the SOT layer 104”);
a magnetic tunnel junction (#102, Figure 6L, magnetic tunnel junction (MTJ)), located on the SOT layer (Figure 6L, #102 is located on #104);
a first bottom plug (#206 far left, Figure 6L, bottom via), located on a bottom of the SOT layer and contacting one end of the SOT layer (Figure 6L, the far left #206 is located on a bottom of and directly contacting a left end of #104);
a second bottom plug (#206 second from left, Figure 6L, bottom via), located on the bottom of the SOT layer and spaced apart from the first bottom plug, the second bottom plug contacting the other end of the SOT layer (Figure 6L, the second from left #206 is located on a bottom of and directly contacting a right end of #104, spaced apart in an x-direction from #206 far left); and
a base (#200, Figure 6L, substrate) located on the bottom of the SOT layer (Figure 6L, #200 is located on the bottom of #104), the base comprising a MOS transistor (#WT, Figure 6, write transistor which is a metal oxide semiconductor transistor including a metal gate #WWL and a gate dielectric #702 on a semiconductor substrate #200) having a gate structure (#WWL, Figure 6L, write word line which functions as a gate according to [0024]) located on the base (Figure 6L, #WWL is located on #200) and a source/drain region (#700 second from left, Figure 6L, source/drain structure) located in the base (Figure 6L, #700 second from left is located in #200), the first bottom plug being electrically connected to the source/drain region of the MOS transistor (Figure 6L, #206 far left is electrically connected to #700 second from left by contact plug #202).
Huang does not appear to disclose an arrangement direction of the second bottom plug and the first bottom plug forming an acute included angle with a magnetic moment direction of the magnetic tunnel junction. However, [0018] of Huang does state that various orientations of elements may be considered accordingly.
Komura teaches A magnetic random access memory cell (#100, Figures 1-3, magnetoresistive effect elements wherein the Figure 15 embodiment is considered, see [0119]-[0123]), comprising:
a spin-orbit torque (SOT) layer (#20/#23, Figures 2 and 15, spin-orbit torque wiring), through which a write current flows when performing a write operation on the magnetic random access memory cell ([0067], “spin-orbit torque wiring 20 is a wiring through which an electrical current flows at the time of writing”);
a magnetic tunnel junction (#10/#11, Figures 4 and 15, laminate body comprising the MTJ structure of a free layer (#2, [0059]), a pinned layer (#1, [0059]), and a tunnel barrier layer (#3, [0064])), located on the SOT layer (Figure 2, #10 is on #20);
a first plug (#31, Figures 2 and 15, first wiring), contacting one end of the SOT layer (Figure 2, #31 connected to one end of #20); and
a second plug (#32, Figures 2 and 15, second wiring), contacting the other end of the SOT layer (Figure 2, #32 is connected to the other end of #20 spaced apart from #31), and
an arrangement direction of the second plug and the first plug forming an acute included angle with a magnetic moment direction of the magnetic tunnel junction (Figure 15, [0120], the arrangement direction of #31 and #32 form an acute angle θ with the magnetic moment long axis of the laminate body MTJ #11); and
a base (#Sub, Figure 2, substrate) located on the bottom of the SOT layer (Figure 2, #Sub is located on the bottom of #20), the base comprising a MOS transistor (#Tr(Sw1), Figure 2, switching element which is a metal oxide semiconductor transistor including a metal gate #G and a gate dielectric #GI on a semiconductor substrate #Sub) having a gate structure (#G, Figure 2, gate electrode) located on the base (Figure 2, #G is located on #Sub) and a source/drain region (#D left, Figure 2, drain) located in the base (Figure 2, #D is located in #Sub), the first bottom plug being electrically connected to the source/drain region of the MOS transistor (Figure 6L, #31 is electrically connected to #D left by via wiring #V).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to consider forming the arrangement direction of the second bottom plug and the first bottom plug as an acute included angle with a magnetic moment direction of the magnetic tunnel junction in Huang based on the teachings of Komura since the tilted relative orientation allows magnetization to be easily reversed (see [0122] of Komura).
Regarding Claim 2. Huang in view of Komura discloses The magnetic random access memory cell according to claim 1, wherein:
the SOT layer is a strip structure extending along a first direction (Huang, Figure 4A, #104 is an elongated strip in the x-direction; Komura, Figure 15, #11 is an elongated oval strip structure extending along a first direction being the angled dot-dash line in Figure 15); and
the magnetic moment direction of the magnetic tunnel junction is parallel to the first direction (Huang, Figure 4A, magnetic moment M of #102 is parallel to the x-direction; Komura, Figure 15, [0120], the elongated long axis of the laminate body MTJ is the magnetic moment which is parallel to the dot-dash line).
Regarding Claim 3. Huang in view of Komura discloses The magnetic random access memory cell according to claim 2, wherein:
the magnetic tunnel junction has a spindle-shaped structure (Huang, Figure 4A, #102 has an elongated oval structure like that of a spindle; Komura, Figure 15, laminate body MTJ #11 has an elongated oval structure like that of a spindle); and
a long axis direction of the spindle-shaped structure is the magnetic moment direction of the magnetic tunnel junction (Huang, Figure 4A, #102 has a long axis of the elongated oval in the same direction as the magnetic moment M; Komura, Figure 15, [0120], the elongated long axis of the laminate body MTJ is the magnetic moment which is parallel to the dot-dash line).
Regarding Claim 4. Huang in view of Komura discloses The magnetic random access memory cell according to claim 1, wherein the magnetic random access memory cell further comprises:
a bottom dielectric layer (Huang, #708, Figure 6L, dielectric layer; Komura, #42 of #In, Figures 2 and 3, insulating layer) located between the base and the SOT layer, the first bottom plug and the second bottom plug being located in the bottom dielectric layer (Huang, Figure 6L, #708 is located between #200 and #104 and #206s are located in #708; Komura, Figures 2 and 3, #42 of #In is located at least partially between #Sub and #20).
Regarding Claim 5. Huang in view of Komura discloses The magnetic random access memory cell according to claim 1, wherein the magnetic random access memory cell further comprises:
a top plug (Huang, #208 left, Figure 6L, top via), located on a top of the magnetic tunnel junction and electrically connected to the magnetic tunnel junction (Huang, Figure 6L, #208 left is located on top of and directly electrically connected to #102).
Regarding Claim 6. Huang in view of Komura discloses The magnetic random access memory cell according to claim 5, wherein the magnetic random access memory cell further comprises:
a top dielectric layer (Huang, #716, Figure 6L, dielectric layer; Komura, #43 of #In, Figures 2 and 3, insulating layer), covering the SOT layer and the magnetic tunnel junction, the top plug being located in the top dielectric layer (Huang, Figure 6L, #716 covers a top of #104 and #102 and #208 left is located in #716; Komura, Figures 2 and 3, #43 covers a top of #20 and #10).
Regarding Claim 7. Huang in view of Komura discloses The magnetic random access memory cell according to claim 1, wherein a material of the SOT layer comprises at least one of tantalum, tungsten, platinum, boron-doped tantalum, platinum-gold alloy, platinum-palladium alloy, bismuth selenide or bismuth antimonide (Huang, [0023], #104 optionally comprises several of the listed materials including tungsten, tantalum, and platinum; Komura, [0073], spin-orbit torque wiring 20 may comprise Pt, W, and Ta; [0076]-[0077], #20 may comprise bismuth-selenide or bismuth antimonide).
Regarding Claim 8. Huang in view of Komura discloses The magnetic random access memory cell according to claim 1, wherein:
a material of the first bottom plug comprises at least one of Cu, W, Al, TiN, TaN or Ti; and a material of the second bottom plug comprises at least one of Cu, W, Al, TiN, TaN or Ti (Huang, [0083], #206s are formed through a damascene process for which copper is the most common metal for the metal structure; Komura, [0092], “first wiring 31 and the second wiring 32 are made of, for example, Al or Cu”, i.e. the first and second wiring being the first and second bottom plugs may comprise Al or Cu).
Regarding Claim 9. Huang in view of Komura discloses The magnetic random access memory cell according to claim 1, wherein the magnetic tunnel junction comprises: a free layer (Huang, #300, Figure 3A, free layer; Komura, #2, Figure 3, second ferromagnetic layer which may be a free layer according to [0059]), a tunneling barrier layer (Huang, #314, Figure 3A, barrier layer which electrons may tunnel through according to [0035]; Komura, #3, Figure 3, non-magnetic layer which is a tunnel barrier layer according to [0064]) located on the free layer (Huang, Figure 3A, #314 is located on #300; Komura, Figure 3, #3 is on #2), and a pinned layer (Huang, #316, Figure 3A, reference layer which is pinned according to [0035]; Komura, #1, Figure 3, first ferromagnetic layer which may be fixed or pinned according to [0059]) located on the tunneling barrier layer (Huang, Figure 3A, #316 is located on #314; Komura, Figure 3, #1 is located on #3).
Regarding Claim 10. Huang discloses A magnetic random access memory (#10, Figure 1A, MRAM memory array), comprising:
a plurality of magnetic random access memory cells (#100, Figures 1A and 6L, unit cell of a memory array #10 which may be a magnetic random access memory array according to [0020]) that are arranged in an array (Figure 1A, #100s are arranged in an array); wherein each magnetic random access memory cell comprises:
a spin-orbit torque (SOT) layer (#104, Figure 6L, spin orbit torque (SOT) layer), through which a write current flows when performing a write operation on the magnetic random access memory cell ([0026], “a write current WP (i.e., the in-plane charge current as described above) may flow through the write transistor WT, the read transistor RT and the SOT layer 104”);
a magnetic tunnel junction (#102, Figure 6L, magnetic tunnel junction (MTJ)), located on the SOT layer (Figure 6L, #102 is located on #104);
a first bottom plug (#206 left of each #100, Figure 6L, bottom via), located on a bottom of the SOT layer and contacting one end of the SOT layer (Figure 6L, the left #206 is located on a bottom of and directly contacting a left end of #104);
a second bottom plug (#206 right of each #100, Figure 6L, bottom via), located on the bottom of the SOT layer and spaced apart from the first bottom plug, the second bottom plug contacting the other end of the SOT layer (Figure 6L, the right #206 is located on a bottom of and directly contacting a right end of #104, spaced apart in an x-direction from #206 left); and
a base (#200, Figure 6L, substrate) located on the bottom of the SOT layer (Figure 6L, #200 is located on the bottom of #104), the base comprising a MOS transistor (#WT, Figure 6, write transistor which is a metal oxide semiconductor transistor including a metal gate #WWL and a gate dielectric #702 on a semiconductor substrate #200) having a gate structure (#WWL, Figure 6L, write word line which functions as a gate according to [0024]) located on the base (Figure 6L, #WWL is located on #200) and a source/drain region (#700 second from left, Figure 6L, source/drain structure) located in the base (Figure 6L, #700 second from left is located in #200), the first bottom plug being electrically connected to the source/drain region of the MOS transistor (Figure 6L, #206 far left is electrically connected to #700 second from left by contact plug #202).
Huang does not appear to disclose an arrangement direction of the second bottom plug and the first bottom plug forming an acute included angle with a magnetic moment direction of the magnetic tunnel junction. However, [0018] of Huang does state that various orientations of elements may be considered accordingly.
Komura teaches A magnetic random access memory cell (#100, Figures 1-3, magnetoresistive effect elements wherein the Figure 15 embodiment is considered, see [0119]-[0123]), comprising:
a spin-orbit torque (SOT) layer (#20/#23, Figures 2 and 15, spin-orbit torque wiring), through which a write current flows when performing a write operation on the magnetic random access memory cell ([0067], “spin-orbit torque wiring 20 is a wiring through which an electrical current flows at the time of writing”);
a magnetic tunnel junction (#10/#11, Figures 4 and 15, laminate body comprising the MTJ structure of a free layer (#2, [0059]), a pinned layer (#1, [0059]), and a tunnel barrier layer (#3, [0064])), located on the SOT layer (Figure 2, #10 is on #20);
a first plug (#31, Figures 2 and 15, first wiring), contacting one end of the SOT layer (Figure 2, #31 connected to one end of #20); and
a second plug (#32, Figures 2 and 15, second wiring), contacting the other end of the SOT layer (Figure 2, #32 is connected to the other end of #20 spaced apart from #31), and
an arrangement direction of the second plug and the first plug forming an acute included angle with a magnetic moment direction of the magnetic tunnel junction (Figure 15, [0120], the arrangement direction of #31 and #32 form an acute angle θ with the magnetic moment long axis of the laminate body MTJ #11); and
a base (#Sub, Figure 2, substrate) located on the bottom of the SOT layer (Figure 2, #Sub is located on the bottom of #20), the base comprising a MOS transistor (#Tr(Sw1), Figure 2, switching element which is a metal oxide semiconductor transistor including a metal gate #G and a gate dielectric #GI on a semiconductor substrate #Sub) having a gate structure (#G, Figure 2, gate electrode) located on the base (Figure 2, #G is located on #Sub) and a source/drain region (#D left, Figure 2, drain) located in the base (Figure 2, #D is located in #Sub), the first bottom plug being electrically connected to the source/drain region of the MOS transistor (Figure 6L, #31 is electrically connected to #D left by via wiring #V).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to consider forming the arrangement direction of the second bottom plug and the first bottom plug as an acute included angle with a magnetic moment direction of the magnetic tunnel junction in Huang based on the teachings of Komura since the tilted relative orientation allows magnetization to be easily reversed (see [0122] of Komura).
Response to Arguments/Amendments
Applicant’s amendments to claims 1 and 10 along with corresponding arguments, see pages 5-6 of the remarks, filed 06/09/2026, with respect to the 35 U.S.C. 102 rejections of claims 1-10 have been fully considered and have been found persuasive. The originally cited prior art does not disclose all of the limitations of amended claims 1 and 10. The 35 U.S.C. 102 rejection of claims 1-10 as anticipated by US 2022/0285608 A1; Komura, Eiji; 09/2022; (“Komura”) have been withdrawn.
However, a new reference has been applied in view of the amendments. Specifically, US 2022/0285609 A1; Huang et al.; 09/2022; (“Huang”) has been found to disclose at least the amended limitations to claims 1 and 10. Huang discloses a base (#200, Figure 6L, substrate) located on the bottom of the SOT layer (Figure 6L, #200 is located on the bottom of #104), the base comprising a MOS transistor (#WT, Figure 6, write transistor which is a metal oxide semiconductor transistor including a metal gate #WWL and a gate dielectric #702 on a semiconductor substrate #200) having a gate structure (#WWL, Figure 6L, write word line which functions as a gate according to [0024]) located on the base (Figure 6L, #WWL is located on #200) and a source/drain region (#700 second from left, Figure 6L, source/drain structure) located in the base (Figure 6L, #700 second from left is located in #200), the first bottom plug being electrically connected to the source/drain region of the MOS transistor (Figure 6L, #206 far left is electrically connected to #700 second from left by contact plug #202). The combination of Huang and Komura are interpreted to render claims 1 and 10 obvious.
Claim(s) 1-10 stand(s) rejected under 35 U.S.C. 103 as being unpatentable over US 2022/0285609 A1; Huang et al.; 09/2022; (“Huang”) in view of US 2022/0285608 A1; Komura, Eiji; 09/2022; (“Komura”).
Conclusion
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/TYLER J WIEGAND/Examiner, Art Unit 2812
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