DETAILED ACTION
Table of Contents
I. Notice of Pre-AIA or AIA Status 3
II. Election/Restrictions 3
III. Claim Rejections - 35 USC § 102 3
A. Claims 1, 3, 4, 8-13, and 16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 6,838,355 (“Stamper”). 4
B. Claims 11-14, 16, and 18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2021/0265348 (“Xie”). 7
C. Claims 11 and 17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2020/0075596 (“Shin”). 9
IV. Claim Rejections - 35 USC § 103 10
A. Claims 2 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Stamper. 11
B. Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Stamper, as applied to claim 14 above, and further in view of US 2019/0181088 (“Lee”). 13
C. Claims 1, 2, 4-8, and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Xie in view of US 2022/0285514 (“Chen”). 14
D. Claims 9, 19, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Xie in view of Chen, as applied to claim 1 above, and further in view of US 2022/0320088 (“Pan”). 19
Conclusion 22
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I. Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
II. Election/Restrictions
Applicant’s election without traverse of species group I in the reply filed on 12/22/2025 is acknowledged. Applicant indicates that claims 1-20 read on the elected species.
III. Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
A. Claims 1, 3, 4, 8-13, and 16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 6,838,355 (“Stamper”).
With regard to claim 1, Stamper discloses, generally in Fig. 2(d),
1. An integrated circuit device, comprising:
[1] a substrate 20 [col. 7, line 1];
[2a] a plurality of wiring structures 23/24 on the substrate 20, the plurality of wiring structures 23/24 extending in a first direction parallel to an upper surface of the substrate 20 and each including:
[2b] a wiring layer 24 [see annotated Fig. 2(d), below] on the substrate 20 and extending in a direction perpendicular to the upper surface of the substrate 20;
[2c] an insulating pattern 23 surrounding a sidewall of the wiring layer 24 and including a first insulating material [col. 7, lines 21-25]; and
[2d] a capping layer 25 on an upper surface of the wiring layer 24 and including a conductive material [col. 7, lines 40-41 referencing materials of capping layer 14 at col. 5, lines 40-48];
[3] a via layer 24 [see annotated Fig. 2(d), below] on the plurality of wiring structures 23/24, the via layer 24 being electrically connected to one wiring structure 24 of the plurality of wiring structures 23/24 [as shown in Fig. 2(d)]; and
[4a] an interlayer insulating layer 26 [col. 7, lines 42-48] covering a sidewall of the insulating pattern 23 between each wiring structure 23/24 of the plurality of wiring structures 23/24,
[4b] the interlayer insulating layer 26 having an upper surface higher than an upper surface of each wiring layer 24 and an upper surface of each insulating pattern 23 [as shown in Fig. 2(d)].
The interconnect 24 includes metal lines, which are the upper portions and the vias, which are the lower portions, as shown in Fig. 2(d), reproduced below and annotated to show the parts. (See col. 5, lines 7-30; Figs. 1(a)-1(d).)
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238
434
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Greyscale
(Stamper: annotated Fig. 2(d))
This is all of the limitations of claim 1.
With regard to claims 3, 4, and 8-10, Stamper further discloses,
3. The integrated circuit device as claimed in claim 1, wherein:
[1] the interlayer insulating layer 26 includes a second insulating material [col. 7, lines 42-48 reference materials at col. 6, lines 6-37], and
[2] the second insulating material [used for interlayer insulating layer 26] includes a material different from the first insulating material [used for insulating pattern 23] [col. 7, lines 47-48: “Again, second dielectric material 26 preferably has a lower dielectric constant than that of first dielectric material 23.”].
4. The integrated circuit device as claimed in claim 1, wherein the upper surface of the insulating pattern 23 is at a vertical level that is lower than an upper surface of the capping layer 25 [as shown in Fig. 2(d)].
8. The integrated circuit device as claimed in claim 1, wherein the first insulating material [used for insulating pattern 23] includes SiO2, Al2O3, or a combination thereof [col. 7, lines 21-23].
9. The integrated circuit device as claimed in claim 1, wherein the conductive material [of the capping layer 25] includes graphene, Ti, Al, Cr, Au, Ni, Pt, or a combination thereof [col. 7, lines 40-41 referencing materials of capping layer 14 at col. 5, lines 40-48].
10. The integrated circuit device as claimed in claim 1, wherein each insulating pattern 23 has a constant thickness along the sidewall of each wiring layer 24 [as shown in the annotated Fig. 2(d), above].
With regard to claims 11-13 and 16, Stamper discloses,
11. An integrated circuit device, comprising:
[1] a substrate 20;
[2] a first wiring structure [right 23/24 in annotated Fig. 2(d)] on the substrate 20, the first wiring structure extending in a first direction parallel to an upper surface of the substrate;
[3] a second wiring structure [left 23/24 in annotated Fig. 2(d)] spaced apart from the first wiring structure [right 23/24] in a second direction perpendicular to the first direction;
[4] a via layer 24 [see annotated Fig. 2(d) on the first wiring structure [right 23/24] and connected to the first wiring structure [right 23/24]; and
[5] an interlayer insulating layer 26 between the first wiring structure [right 23/24] and the second wiring structure [left 23/24],
wherein:
[6a] the first wiring structure [right 23/24] includes:
[6b] a first wiring layer [right 24] on the substrate 20 and extending in a direction perpendicular to the upper surface of the substrate 20, and
[6c] an insulating pattern [right 23] surrounding a sidewall of the first wiring layer [right 24] and including a first insulating material [supra], and
[6d] the interlayer insulating layer 26 covers a sidewall of the insulating pattern [right 23] between the first wiring structure [right 23/24] and the second wiring structure [left 23/24] and
[6e] has an upper surface higher than an upper surface of each of the first wiring layer [right 24] and the insulating pattern [right 23].
12. The integrated circuit device as claimed in claim 11, wherein the interlayer insulating layer 26 is in contact with the sidewall of the insulating pattern [right 23].
13. The integrated circuit device as claimed in claim 11, wherein:
[1] the interlayer insulating layer 26 includes a second insulating material, and
[2] the second insulating material includes SiO2, SiCOH, SiF, SiOC, or a combination thereof [again, col. 7, lines 42-48 referencing materials at, e.g., col. 6, lines 6-37, 60-65, including “silica aerogel”, SiCOH, porous SiCOH].
16. The integrated circuit device as claimed in claim 11, wherein the interlayer insulating layer 26 has a constant width between the first wiring structure [right 24] and the second wiring structure [left 24] [as shown in Fig. 2(d)].
B. Claims 11-14, 16, and 18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2021/0265348 (“Xie”).
With regard to claim 11, Xie discloses, generally in Fig. 9,
11. An integrated circuit device [title], comprising:
[1] a substrate 104 [¶ 32];
[2] a first wiring structure [center of three shown (HKMG gate 602)/(spacer 204) in Fig. 9; ¶¶ 68-74] on the substrate 104, the first wiring structure [center 602/204] extending in a first direction [Y direction in Fig. 1] parallel to an upper surface of the substrate 104;
[3] a second wiring structure [right or left 602/204] spaced apart from the first wiring structure [center 602/204] in a second direction perpendicular to the first direction;
[4] a via layer 906 [¶ 79] on the first wiring structure [center 602/204] and connected to the first wiring structure [center 602/204]; and
[5] an interlayer insulating layer 506 [¶ 65] between the first wiring structure [center 602/204] and the second wiring structure [right or left 602/204],
wherein:
[6a] the first wiring structure [center 602/204] includes:
[6b] a first wiring layer [center 602] on the substrate 104 and extending in a direction perpendicular to the upper surface of the substrate 104 [as shown in Fig. 9], and
[6c] an insulating pattern 204 surrounding a sidewall of the first wiring layer [center 602] and including a first insulating material [¶ 45: “a low-k dielectric, a nitride, silicon nitride, silicon oxide, SiON, SiC, SiOCN, or SiBCN”], and
[6d] the interlayer insulating layer 506 covers a sidewall of the insulating pattern 204 between the first wiring structure [center 602/204] and the second wiring structure [right or left 602/204] and
[6e] has an upper surface higher than an upper surface of each of the first wiring layer [center 602] and the insulating pattern [center 204] [as shown in Fig. 9].
12. The integrated circuit device as claimed in claim 11, wherein the interlayer insulating layer 506 is in contact with the sidewall of the insulating pattern [center 204].
13. The integrated circuit device as claimed in claim 11, wherein:
[1] the interlayer insulating layer 506 includes a second insulating material, and
[2] the second insulating material includes SiO2, SiCOH, SiF, SiOC, or a combination thereof [¶ 65].
14. The integrated circuit device as claimed in claim 11, wherein the second wiring structure [right or left 602/204 in Fig. 9] includes:
[1] a second wiring layer [right or left 602] on the substrate 104 and extending in the direction perpendicular to the upper surface of the substrate 104 [as shown in Fig. 1]; and
[2] a capping layer 604 on the upper surface of the second wiring layer [right or left 602] and including a third insulating material [¶ 74: “The gate hard masks 604 can be made of any suitable material, such as, for example, silicon nitride.”].
16. The integrated circuit device as claimed in claim 11, wherein the interlayer insulating layer 506 has a constant width between the first wiring structure [center 602/204] and the second wiring structure [right or left 602/204].
18. The integrated circuit device as claimed in claim 11, further comprising:
[1] a barrier layer [not shown but is “(e.g., a conformal metal liner (not shown), such as NiPt, Ni, Ti is initially deposited” (¶ 79)] covering side surfaces and lower surfaces of the via layer [i.e. the “bulk metals such as Co, W or Ru) to form … a gate contact 906,” (¶ 79)],
[2] wherein the barrier layer covers the upper surface of the first wiring layer [center 602] and the upper surface of the insulating pattern [center 204] [because the barrier layer is “conformal” over the “gate contact trench 804” (¶ 79)].
C. Claims 11 and 17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2020/0075596 (“Shin”).
With regard to claims 11 and 17, Shin discloses, generally in Figs. 1 and 2,
11. An integrated circuit device, comprising:
[1] a substrate 110 [¶ 24];
[2] a first wiring structure [e.g. center GL/124 along line X2—X2' in Figs. 1 and 2 (¶ 26)] on the substrate 110, the first wiring structure [center GL/124] extending in a first direction [Y direction in Fig. 1] parallel to an upper surface of the substrate 110 [as shown in Fig. 1];
[3] a second wiring structure [left or right GL/124 along line X2—X2' in Figs. 1 and 2] spaced apart from the first wiring structure [center GL/124] in a second direction [X direction in Fig. 1] perpendicular to the first direction [Y direction];
[4] a via layer 152 [¶ 40] on the first wiring structure [center GL/124] and connected to the first wiring structure [center GL/124]; and
[5] an interlayer insulating layer 128 and/or 142 [¶¶ 29, 39] between the first wiring structure [center GL/124] and the second wiring structure [right or left GL/124],
wherein:
[6a] the first wiring structure [center GL/124] includes:
[6b] a first wiring layer [center GL] on the substrate 110 and extending in a direction perpendicular to the upper surface of the substrate 110 [as shown in Fig. 1], and
[6c] an insulating pattern [center 124] surrounding a sidewall of the first wiring layer [center GL] and including a first insulating material [¶ 27], and
[6d] the interlayer insulating layer 128 and/or 142 covers a sidewall of the insulating pattern 124 between the first wiring structure [center GL/124] and the second wiring structure [left or right GL/124] and
[6e] has an upper surface higher than an upper surface of each of the first wiring layer [center GL/124] and the insulating pattern 124.
17. The integrated circuit device as claimed in claim 11, wherein the upper surface of the insulating pattern [center 124] is at substantially a same vertical level as the upper surface of the first wiring layer [center GL].
IV. Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
A. Claims 2 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Stamper.
Claim 14 reads,
14. The integrated circuit device as claimed in claim 11, wherein the second wiring structure includes:
[1] a second wiring layer on the substrate and extending in the direction perpendicular to the upper surface of the substrate; and
[2] a capping layer on the upper surface of the second wiring layer and including a third insulating material.
The prior art of Stamper, as explained above, discloses each of the features of claim 11.
With regard to the capping layer material, Stamper states,
The cap 25 may be formed by the same techniques and of the same materials as described for cap 14.
(Stamper: col. 7, lines 40-41)
The cap 14 also may be formed of any suitable material. For example, cap 14 may be formed of CoNiP or CoWP, by selective electroless plating. Alternatively, cap 14 may be formed of tungsten, by selective CVD metal deposition. In another alternative, cap 14 may be formed of a selectively deposited dielectric. In yet another alternative, cap 14 may be composed of a conductive or dielectric layer which is lithographically patterned and etched.
(Stamper: col. 5, lines 41-48; emphasis added)
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to make the capping layer 25 over the second wiring layer (left 24) in annotated Fig. 2(d)] from a dielectric material because (1) Stamper explicitly suggests dielectric materials as an option (id.) and (2) there is no conductive via connected to it, by contrast to the conductive via 24 shown (annotated Fig. 2(d), above) connected to the first wiring layer (right 24) by the intervening capping layer 25 which must be made of, by contrast, a conductive material.
This is all of the limitations of claim 14.
Claim 2 reads,
2. The integrated circuit device as claimed in claim 1, wherein:
[1] a height of each capping layer in the direction perpendicular to the upper surface of the substrate is less than a height of each wiring layer, and
[2] the height of each capping layer in the direction perpendicular to the upper surface of the substrate is less than a height of the via layer.
The prior art of Stamper, as explained above, teaches each of the features of claim 1.
At the outset, note that Applicant uses the term “height”, denoted in the Instant Figures with reference character, “h1”, “h2”, and “h3”, consistent with “thickness” rather than with “elevation” above a common surface, e.g., the substrate. Stamper is interpreted consistent with the Instant Application.
Stamper does not explicitly provide the relative height of the capping layer 25 and the wiring layers 24 but shows in Fig. 2(d) that the thickness of the capping layer 25 is less than that of each of the wiring layers 24 and the via 24 connected to the wiring layer, as in annotated in Fig. 2(d), above. As also quoted above, the material of the capping layer 25 can be CoNiP or CoWP or tungsten (supra). The preferred material of the interconnect, i.e. metal lines and vias (Stamper: e.g. at col. 5, lines 7-30) is copper (Stamper: sentence bridging col. 4-5).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to make the capping layer 25 thinner than each of the wiring layers 24 and vias 24 because the resistivity of any of CoNiP or CoWP or tungsten is significantly higher than that of copper. Thus, one having ordinary skill in the art would readily understand that the bulk of the wiring layer 24 should have the lowest possible resistivity in order to minimize signal delay and overheating. Moreover, one having ordinary skill in the art would understand to make the relatively higher-resistivity capping layer 25 as thin as possible in order to reduce the contact resistance between the via and the underlying wiring layer 24 to which is connected.
In addition, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to make the via (the 24 in annotated Fig. 24) thicker than the capping layer 25 in order to increase the distance between the wiring lines 24 in the metal levels in order to reduce RC delays in signal transmission as would be immediately appreciated by those having ordinary skill in the art.
This is all of the limitations of claim 2.
B. Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Stamper, as applied to claim 14 above, and further in view of US 2019/0181088 (“Lee”).
Claim 15 reads,
15. The integrated circuit device as claimed in claim 14, wherein the third insulating material includes SiOC, SiCN, SiOCN, Al2O3, AlN, or a combination thereof.
The prior art of Stamper, as explained above, teaches each of the features of claim 14.
Stamper does not teach what the material of the capping layer 25 is when it is a dielectric.
Lee teaches a capping layer 140 over wiring layers, 112 and 113 (Lee: ¶ 25), to which no electrical connection is made can be made from AlN (Lee: ¶ 58).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to make the capping layer 25 over the second wiring layer from AlN because Stamper is silent to the dielectric composition such that one having ordinary skill in the art would use a known capping material such as AlN. As such, the selection of AlN for the capping layer 25 in Stamper amounts to obvious material choice. (See MPEP 2144.07.)
C. Claims 1, 2, 4-8, and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Xie in view of US 2022/0285514 (“Chen”).
Claim 1 reads,
1. An integrated circuit device, comprising:
[1] a substrate;
[2a] a plurality of wiring structures on the substrate, the plurality of wiring structures extending in a first direction parallel to an upper surface of the substrate and each including:
[2b] a wiring layer on the substrate and extending in a direction perpendicular to the upper surface of the substrate;
[2c] an insulating pattern surrounding a sidewall of the wiring layer and including a first insulating material; and
[2d] a capping layer on an upper surface of the wiring layer and including a conductive material;
[3] a via layer on the plurality of wiring structures, the via layer being electrically connected to one wiring structure of the plurality of wiring structures; and
[4a] an interlayer insulating layer covering a sidewall of the insulating pattern between each wiring structure of the plurality of wiring structures,
[4b] the interlayer insulating layer having an upper surface higher than an upper surface of each wiring layer and an upper surface of each insulating pattern.
With regard to claim 1, Xie discloses, generally in Fig. 9,
1. An integrated circuit device, comprising:
[1] a substrate 104;
[2a] a plurality of wiring structures 602/204 on the substrate 104, the plurality of wiring structures 602/204 extending in a first direction [Y direction in Fig. 1] parallel to an upper surface of the substrate 104 and each including:
[2b] a wiring layer 602 on the substrate 104 and extending in a direction perpendicular to the upper surface of the substrate 104 [as shown in Fig. 9];
[2c] an insulating pattern 204 surrounding a sidewall of the wiring layer 602 and including a first insulating material [¶ 45: “a low-k dielectric, a nitride, silicon nitride, silicon oxide, SiON, SiC, SiOCN, or SiBCN”]; and
[2d] … [not taught] …
[3] a via layer 906 on the plurality of wiring structures 602, the via layer 906 being electrically connected to one wiring structure [i.e. the center 602] of the plurality of wiring structures 602; and
[4a] an interlayer insulating layer 506 covering a sidewall of the insulating pattern 204 between each wiring structure 602/204 of the plurality of wiring structures 602/204,
[4b] the interlayer insulating layer 506 having an upper surface higher than an upper surface of each wiring layer 602 and an upper surface of each insulating pattern 204.
With regard to feature [3] of claim 1, the claim feature “a via layer on the plurality of wiring structures” is interpreted consistent with Fig. 2 of the Instant Application shown shows a via layer 430 in contact with only one of the plurality of wiring layers 210a, 210b.
With regard to feature [2d] of claim 1,
[2d] a capping layer on an upper surface of the wiring layer and including a conductive material;
Xie does not teach a conductive capping layer on the upper surface of each wiring layer 602.
Chen, like Xie, teaches a gate-all-around finFET having a plurality of vertically-stacked nanoribbon channels 170 (Chen: ¶¶ 26-27; Fig. 1C). Also like Xie, Chen teaches that there are plural, parallel-extending high-k/gate metal (HKMG) gate structures 140 formed by replacement-gate processing (Chen: ¶¶ 25, 40; Figs. 1A-1B). In addition, Chen teaches that the HKMG gate electrode include a conductive capping layer 300 extending over the top surface (Chen: ¶ 34) that provides the benefit of reducing the gate resistance at the nanochannels 170 (Chen: ¶ 35).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include the gate capping layer 300 of Chen over the gate electrodes 602 of Xie in order to reduce the gate resistance at the nanochannels 108 of Xie, as taught in Chen (Chen: ¶ 35). As such, Chen may be seen as an improvement to Xie in this aspect.
This is all of the features of claim 1.
Claim 2 reads,
2. The integrated circuit device as claimed in claim 1, wherein:
[1] a height of each capping layer in the direction perpendicular to the upper surface of the substrate is less than a height of each wiring layer, and
[2] the height of each capping layer in the direction perpendicular to the upper surface of the substrate is less than a height of the via layer.
Again, Xie does not teach the capping layer but it is obvious in view of Chen (supra).
With regard to claim 2, Chen further teaches,
2. The integrated circuit device as claimed in claim 1, wherein:
[1] a height 520 of each capping layer 300 in the direction perpendicular to the upper surface of the substrate 110 is less than a height of each wiring layer 530 [Chen: Fig. 5; ¶ 49], and
[2] the height of each capping layer 520 [e.g. 20 to 70 nm, e.g. 30 nm to 60 nm (Chen: ¶ 49)] in the direction perpendicular to the upper surface of the substrate 110 …
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, in addition, to make the capping layer 300 of Chen used in Xie to be, e.g. 30 nm to 60 nm, because Chen teaches that this thickness is suitable and is a small fraction of the thickness of the gate electrode.
So modified, the thickness of the via layer 906 in Xie necessarily would be greater than that of the capping layer 300 of Chen used in Xie, as evidenced by Fig. 9 of Xie, which shows that the via layer 906 extends past top surface of the gate electrode 602 to cover a portion of the side surfaces and therefore necessarily includes a thickness greater than any portion that is the capping layer.
With regard to claim 4, Xie modified accord to Chen as explained under claims 1 and 2, further teaches,
4. The integrated circuit device as claimed in claim 1, wherein the upper surface of the insulating pattern 204 is at a vertical level that is lower than an upper surface of the capping layer 300 [of Chen used in Xie] [because the gate trench opening 804 moves the height of the insulating layer pattern 204 to below the top surface of the gate electrode 602, as shown in Figs. 8-9 of Xie].
With regard to claim 5, Xie further discloses,
5. The integrated circuit device as claimed in claim 1, wherein the via layer 906 includes:
[1] a first portion [lower portion] having a width in a second direction [X direction in Fig. 1, which equals width direction in Fig. 9] perpendicular to the first direction [Y direction in Fig. 1, which is equal to into-out of page of Fig. 9] that is less than a width of the one wiring structure 602/204 in the second direction; and
[2] a second portion [upper portion] on the first portion [lower portion], the second portion [upper portion] having a width in the second direction that is greater than the width of the one wiring structure 602/204 in the second direction [as shown in Fig. 9].
With regard to feature [1], because the claimed “via layer” does not include the disclosed and claimed “barrier layer”, i.e. the not-shown conformal metal liner of Xie (¶ 79) that makes up part of the via structure 906 shown in Fig. 9 of Xie, the via layer is narrower than the wiring structure 602/204 by twice the thickness of said conformal metal liner”, as evidenced by Fig. 9 which shows the lower portion of the via structure 906, i.e. the liner plus the bulk fill, to be of equal width. This is exactly identical to that shown in Fig. 2 of the Instant Application, i.e. that w3 is smaller than w1 by an amount that is twice the thickness of the barrier layer 410.
With regard to claims 6-7, Xie modified accord to Chen as explained under claims 1 and 2, further teaches,
6. The integrated circuit device as claimed in claim 1, further comprising
[1] a barrier layer [i.e. the “conformal metal liner” (Xie: ¶ 79)] surrounding side surfaces and lower surfaces of the via layer [bulk metal fill portion of 906 (Xie: ¶ 79)],
[2] wherein the barrier layer is in contact with upper surfaces and side surfaces of the capping layer [300 of Chen used on the top surface of 602 of Xie, as explained above] of the one wiring structure.
7. The integrated circuit device as claimed in claim 6, wherein the barrier layer [i.e. the “conformal metal liner” (Xie: ¶ 79)] includes:
[1] a first portion covering a part of the upper surface of the interlayer insulating layer 506 [of Xie, as evidenced by Fig. 9];
[2] a second portion covering the upper surface of the capping layer [300 of Chen used on the top surface of 602 of Xie, as explained above] of the one wiring structure [center 602/204 in Fig. 9 of Xie] at a vertical level lower than the upper surface of the interlayer insulating layer 506; and
[3] a third portion covering the upper surface of the insulating pattern [center 204 in Fig. 9 of Xie] of the one wiring structure [center 602/204 of Xie] and protruding toward the substrate [as shown in Fig. 9 of Xie].
With regard to claims 8 and 10, Xie further discloses,
8. The integrated circuit device as claimed in claim 1, wherein the first insulating material [of the insulating pattern 204] includes SiO2, Al2O3, or a combination thereof [Xie: ¶ 45].
10. The integrated circuit device as claimed in claim 1, wherein each insulating pattern 204 has a constant thickness along the sidewall of each wiring layer 602 [as shown in Fig. 9 of Xie].
D. Claims 9, 19, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Xie in view of Chen, as applied to claim 1 above, and further in view of US 2022/0320088 (“Pan”).
Claim 9 reads,
9. The integrated circuit device as claimed in claim 1, wherein the conductive material [used for the capping layer] includes graphene, Ti, Al, Cr, Au, Ni, Pt, or a combination thereof.
The prior art of Xie in view of Chen, as explained above, teaches each of the features of claim 1.
Chen does not teach that the capping layer is any of the materials in claim 9, but Chen does not limit the material of the capping layer:
In other embodiments, the selective growth process 550 may be configured to grow another tungsten-containing material or another suitable material as the conductive capping layer 300. Regardless of the specific type of material grown as the conductive capping layer 300, it is understood that the conductive capping layer 300 has a lower resistivity than the metal gate electrode of the HKMG structure 140, for example, a lower resistivity than each of the layers 400, 410, 420, 430, and 440.
(Chen: ¶ 51; emphasis added)
Pan, like Chen, teaches a gate-all-around finFET having a plurality of vertically-stacked nanoribbon channels 220 (Pan: ¶ 17; Fig. 2-13) having a metal capping layer 380 on the gate electrode 374 (Pan: ¶¶ 53, 58; Fig. 1C). In addition to tungsten, Pan teaches that the capping layer 380 can be any of Ti, Al, Ni, and Pt (¶ 58). At least aluminum has a greater conductivity than tungsten and would therefore meet the requirement in Chen (id.).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to make the capping layer 300 of Chen, used in Xie, from aluminum because it would be the substitution of one known low-resistivity metal for another suitable for the same purpose of forming a low-resistivity capping metal for the gate electrode of the same kind of nano-channel finFET. As such the selection of aluminum amounts to obvious material choice. (See MPEP 2144.07.)
This is all of the limitations of claim 9.
Claim 19 reads,
19. An integrated circuit device, comprising:
[1] a substrate;
[2a] a plurality of wiring structures on the substrate, the plurality of wiring structures extending in a first direction parallel to an upper surface of the substrate and each including:
[2b] a wiring layer on the substrate and extending in a direction perpendicular to the upper surface of the substrate,
[2c] an insulating pattern surrounding a sidewall of the wiring layer and including a first insulating material, and
[2d] a capping layer on an upper surface of the wiring layer and including a conductive material,
[3] a via layer on the plurality of wiring structures, the via layer being connected to one wiring structure of the plurality of wiring structures; and
[4a] an interlayer insulating layer covering a sidewall of the insulating pattern between each wiring structure of the plurality of wiring structures,
[4b] the interlayer insulating layer having an upper surface higher than an upper surface of each wiring layer and higher than an upper surface of insulating pattern,
wherein:
[5] the capping layer has a height in a direction perpendicular to the upper surface of the substrate that is less than a height of the wiring layer and is less than a height of the via layer,
[6] the upper surface of each insulating pattern is at a vertical level lower than an upper surface of each capping layer,
[7] each insulating pattern has a constant thickness along the sidewall of each wiring layer,
[8a] the via layer includes:
[8b] a first portion having a width in a second direction perpendicular to the first direction that is less than a width of the one wiring structure, and
[8c] a second portion on the first portion, the second portion having a width in the second direction that is greater than the width of the one wiring structure in the second direction,
[9] the first insulating material includes SiO2, Al2O3, or a combination thereof, and
[10] the conductive material includes graphene, Ti, Al, Cr, Au, Ni, Pt, or a combination thereof.
Each of features [1]-[4b] of claim 19 are the same as recited in claim 1.
Feature [5] of claim 19 is essentially the same as claim 2.
Feature [6] of claim 19 is the same as claim 4.
Feature [7] of claim 19 is the same as claim 10.
Features [8a]-[8c] of claim 19 are the same as those recited in claim 5.
Feature [9] of claim 19 is the same as claim 8.
Feature [10] of claim 19 is essentially the same as claim 9.
Thus, each of the features of claim 19, other than feature [10], has been addressed above under the rejection over Xie in view of Chen, and feature [10] of claim 19 is addressed under claim 9, above.
Claim 20 reads,
20. The integrated circuit device as claimed in claim 19, further comprising
[1] a barrier layer surrounding side surfaces and lower surfaces of the via layer,
wherein:
[2] the barrier layer is in contact with upper surfaces and side surfaces of the capping layer of the one wiring structure, and
[3a] the barrier layer includes:
[3b] a first portion covering a part of an upper surface of the interlayer insulating layer;
[3c] a second portion covering the upper surface of the capping layer of the one wiring structure at a vertical level lower than the upper surface of the interlayer insulating layer; and
[3d] a third portion covering an upper surface of the insulating pattern of the one wiring structure and protruding toward the substrate.
Claim 20 is the same as claims 6 and 7, which have been addressed above under the rejection over Xie in view of Chen.
Conclusion
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Signed,
/ERIK KIELIN/
Primary Examiner, Art Unit 2814