DETAILED ACTION
This office action is in response to applicant’s Restriction/Election filed on 12/10/2025.
Currently claims 1-51 are pending in the application.
Election/Restrictions
Applicant's election of Species B, Claims 21-33 with traverse, in the reply filed on 12/10/2025 is acknowledged. The applicant did not provide any specific reason for traversal. The examiner explained the reason for restriction in the office action of 10/23/2025. The structures and the circuit connections of various Species are different. Therefore, they are considered separate inventions. Furthermore, the examiner is required to find the various circuits claimed in the claim-set. As a result, the examiner needs to make a rigorous search strategy and implementation of that search strategy in several different platforms available to the examination system. Thus, the restriction requirement is FINAL.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 01/16/2024 and 07/07/2023 were filed before the mailing date of the office action. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements were considered by the examiner.
Claim Rejections - 35 USC § 112 (b)
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 22-26 are rejected under 35 U.S.C. 112 (b), as being indefinite for failing to particularly pointing out and distinctly claim the subject matter which the inventor or a joint inventor, regard as their invention.
Regarding claim 22, the instant claim recites limitation in view of claim 21, where claim 22 recites “a first drain/source terminal of the first select transistor” and “a second drain/source terminal of the first select transistor” and “a first drain/source terminal of the second select transistor” (claim 22, lines 1-4). There is insufficient antecedent basis for this limitation in the claim. It is unclear whether the “first drain/source terminal” and the “second drain/source terminal” of the first transistor which is same as the first select transistor and the “first drain/source terminal” of the second transistor which is same as the second select transistor (claim 21, lines 24-29) are being recalled or a new “a first drain/source terminal of the first select transistor” and “a second drain/source terminal of the first select transistor” and “a first drain/source terminal of the second select transistor” (claim 22, lines 1-4) are being introduced, rendering the claim indefinite. Clarification and/or correction are/is required.
Claims 23-26 are also rejected due to their dependence on a rejected base claim.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over US 2023/0064751 A1 (Chang) and further in view of US 2017/0053925 A1 (Wong).
Regarding claim 21, Chang discloses, an antifuse-type one time programming (OTP) memory cell for a physically unclonable function technology,
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the antifuse-type OTP memory cell (500; memory device; Fig. 5B; [0068] – [0076]) comprising:
a first nanowire (as annotated on Fig. 5B; [0069]);
a first gate structure (as annotated on Fig. 5B; [0069]) comprising a first spacer, a second spacer, a first gate dielectric layer and a first gate layer (as annotated on Fig. 5B; [0069]), wherein a central region of the first nanowire is surrounded by the first gate dielectric layer, the first gate dielectric layer is surrounded by the first gate layer (as annotated on Fig. 5B; [0069]), a first side region (right side) of the first nanowire is surrounded by the first spacer, and a second side region (left side) of the first nanowire is surrounded by the second spacer (as annotated on Fig. 5B; [0069]);
a first drain/source structure (558; epitaxial structure; Fig. 5B; [0074]) electrically contacted with a first terminal (right terminal) of the first nanowire (as annotated on Fig. 5B; [0069]);
a second nanowire (as annotated on Fig. 5B; [0069]);
a second gate structure (as annotated on Fig. 5B; [0069]) comprising a third spacer, a fourth spacer, a second gate dielectric layer and a second gate layer (as annotated on Fig. 5B; [0069]), wherein a central region of the second nanowire is surrounded by the second gate dielectric layer, the second gate dielectric layer is surrounded by the second gate layer (as annotated on Fig. 5B; [0069]), a first side region (right side) of the second nanowire is surrounded by the third spacer, and a second side region (left side) of the second nanowire is surrounded by the fourth spacer (as annotated on Fig. 5B; [0069]);
a second drain/source structure (556; epitaxial structure; Fig. 5B; [0074]) electrically contacted with a second terminal (left terminal) of the first nanowire and a first terminal (right terminal) of the second nanowire;
a third drain/source structure (554; epitaxial structure; Fig. 5B; [0074]) electrically contacted with a second terminal (left terminal) of the second nanowire;
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a first transistor (126; transistor; Fig. 5B; [0057]) comprising a first drain/source terminal (as annotated on Fig. 5B; [0057]), a gate terminal (as annotated on Fig. 5B; [0057]) and a second drain/source terminal (as annotated on Fig. 5B; [0057]), wherein the second drain/source terminal of the first transistor is connected with the first drain/source structure (558); and
a second transistor (120; transistor; Fig. 5B; [0057]) comprising a first drain/source terminal (as annotated on Fig. 5B; [0057]), a gate terminal (as annotated on Fig. 5B; [0057]) and a second drain/source terminal (as annotated on Fig. 5B; [0057]), wherein the first drain/source terminal of the second transistor is connected with the third drain/source structure (554).
But Chang fails to teach explicitly, the first gate layer is connected with an antifuse control line and the second gate layer is connected with the antifuse control line;
However, in analogous art, Wong discloses, the first gate layer is connected with an antifuse control line (AF1) and the second gate layer is connected with the antifuse control line (AF2) (Fig. 4B; [0049] – [0050]);
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Chang and Wong before him/her, to modify the teachings of an antifuse-type one time programming (OTP) memory cell as taught by Chang and to include the teaching of gate layers being connected to antifuse control lines as taught by Wong since the connection would facilitate smooth programming of antifuse memory structure. Absent this important teaching in Chang, a person with ordinary skill in the art would be motivated to reach out to Wong while forming an antifuse-type one time programming (OTP) memory cell of Chang.
Allowable Subject Matter
Claims 22-33 are objected to as being dependent upon rejected base claims, but would be allowable if rewritten in independent forms including all of the limitations of the base claims and any intervening claims.
Regarding claim 22, the closest prior art, US 2023/0064751 A1 (Chang), in combination with US 2017/0053925 A1 (Wong), fails to disclose, “the antifuse-type OTP memory cell as claimed in claim 21, wherein the first transistor is a first select transistor, and the second transistor is a second select transistor, wherein a first drain/source terminal of the first select transistor is connected with a first bit line, a gate terminal of the first select transistor is connected with a word line, a second drain/source terminal of the first select transistor is connected with the first drain/source structure, a first drain/source terminal of the second select transistor is connected with the third drain/source structure, a gate terminal of the second select transistor is connected with the word line, and a second drain/source terminal of the second select transistor is connected with a second bit line”, in combination with the additionally claimed features, as are claimed by the Applicant.
Regarding claim 27, the closest prior art, US 2023/0064751 A1 (Chang), in combination with US 2017/0053925 A1 (Wong), fails to disclose, “the antifuse-type OTP memory cell as claimed in claim 21, further comprising a first select transistor and a second select transistor, wherein the first transistor is a first following transistor, and the second transistor is a second following transistor, wherein a first drain/source terminal of the first select transistor is connected with a first bit line, a gate terminal of the first select transistor is connected with a word line, a first drain/source terminal of the first following transistor is connected with a second drain/source terminal of the first select transistor, a gate terminal of the first following transistor is connected with a following control line, a second drain/source terminal of the first following transistor is connected with the first drain/source structure, a first drain/source terminal of the second following transistor is connected with the third drain/source structure, a gate terminal of the second following transistor is connected with the following control line, a first drain/source terminal of the second select transistor is connected with a second drain/source terminal of the second following transistor, a gate terminal of the second select transistor is connected with the word line, and a second drain/source terminal of the second select transistor is connected with a second 16 bit line”, in combination with the additionally claimed features, as are claimed by the Applicant.
Claims 23-26 and 28-33 are also objected to due to their dependence on an objected base claim.
Note: The objected claims which are also subjected to 112 (b) rejections are shown as rejected claims in PTO-326 form.
Examiner’s Note (Additional Prior Arts)
The examiner included a few prior arts which were not used in the rejection but are relevant to the disclosure.
US 2021/0249423 A1 (Chang) - A semiconductor device is disclosed. The semiconductor device includes a fin-based structure formed on a substrate. The semiconductor device includes a plurality of first nanosheets, vertically spaced apart from one another, that are formed on the substrate. The semiconductor device includes a first source/drain (S/D) region electrically coupled to a first end of the fin-based structure. The semiconductor device includes a second S/D region electrically coupled to both of a second end of the fin-based structure and a first end of the plurality of first nanosheets. The semiconductor device includes a third S/D region electrically coupled to a second end of the plurality of first nanosheets. The fin-based structure has a first crystal lattice direction and the plurality of first nano sheets have a second crystal lattice direction, which is different from the first crystal lattice direction.
US 2022/0359545 A1 (Chang) - A semiconductor device is disclosed including a plurality of first nanostructures extending along a first lateral direction. The semiconductor device includes a plurality of second nanostructures extending along the first lateral direction. The semiconductor device includes a dielectric fin structure disposed immediately next to a first sidewall of each of the plurality of first nanostructures along a second lateral direction perpendicular to the first lateral direction. The semiconductor device includes a first gate structure wrapping around each of the plurality of first nanostructures except for the first sidewalls. The semiconductor device includes a second gate structure straddling the plurality of second nanostructures.
US 2019/0164981 A1 (Chen) - A multi-cell per bit nonvolatile memory (NVM) unit is disclosed including a select transistor disposed on a first oxide define (OD) region, a word line transistor disposed on the first OD region, and serially connected floating gate transistors disposed between the select transistor and the word line transistor. A first floating gate extension continuously extends toward a second OD region and adjacent to an erase gate region. A second floating gate extension continuously extends toward a third OD region and is capacitively coupled to a control gate region. A channel length of each of the floating gate transistors is shorter than that of the select transistor or the word line transistor.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to S M SOHEL IMTIAZ whose telephone number is (408) 918-7566. The examiner can normally be reached on 8AM-5PM, M-F, PST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine S. Kim can be reached at 571-272-8458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/S M SOHEL IMTIAZ/Primary Patent Examiner
Art Unit 2812
02/03/2026