DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-15 and 21-23 have been considered but are moot on grounds of new rejection.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “adjacent to a circuit layer comprising at least one transistor and the second surface of the first semiconductor chip is an inactive surface of the first semiconductor chip, the third surface of the second semiconductor chip is an active surface of the second semiconductor chip adjacent to a circuit layer comprising at least one transistor and the fourth surface of the second semiconductor chip is an inactive surface of the second semiconductor chip, the first chip stack includes third semiconductor chips stacked on the first surface of the first semiconductor chip, each of the third semiconductor chips is disposed such that an active surface thereof faces the first semiconductor chip, and an inactive surface thereof faces away from the first semiconductor chip, each active surface being adjacent to a circuit layer comprising at least one transistor”, “a circuit layer of the first semiconductor chip that comprises a transistor”, “a circuit layer of the second semiconductor chip that comprises a transistor” and “a circuit layer of the respective third semiconductor chip that comprises a transistor” must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 3, 4, 6, 10-12, 21 and 22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (Chen) (US 2022/0093564 A1) in view of Song et al. (Song) (US 2022/0200735 A1 now US 11,444,068 B2) as evidenced or in view of Haba et al. (Haba) (US 2020/0227367 A1).
In regard to claim 1, Chen (Figs. 1, 3L, 6, 7, 8, 10 and associated text and items) discloses a semiconductor package (Figs. 1, 3L, 6, 7, 8, 10), comprising: an interconnect structure [power delivery network] (item 100); a first semiconductor chip (item 120) disposed on a top surface of the interconnect structure [power delivery network] (item 100), the first semiconductor chip (item 120) having a first surface (top surface of item 120) and a second surface (bottom surface of item 120) that are opposite to each other; a second semiconductor chip (item 110) disposed on the top surface of the power delivery network (item 100) and horizontally spaced apart from the first semiconductor chip (item 120), the second semiconductor chip (item 110) having a third surface (top surface of item 110) and a fourth surface (bottom surface of item 110) that are opposite to each other; a first chip stack (item 150) disposed on the first surface of the first semiconductor chip stack (item 120); and a second chip stack (item 140 or 144a-144d) disposed on the third surface (top surface of item 110) of the second semiconductor chip (item 110), wherein: the first surface (top surface of item 120) of the first semiconductor chip (item 120) is an active surface of the first semiconductor chip (item 120), the third surface (top surface of item 110) of the second semiconductor chip (item 110) is an active surface of the second semiconductor chip (item 110), the first chip stack (item 150) includes third semiconductor chips (items 152a-152d) stacked on the first surface of the first semiconductor chip (item 120), each of the third semiconductor chips (items 152a-152d) is disposed such that an active surface thereof faces the first semiconductor chip (item 120), and the first chip stack (item 150) and the second semiconductor chip (item 110) are electrically connected to each other through the interconnect structure [power delivery network] (item 100), but does not specifically disclose a power delivery network.
Song (Fig. 8 and associated text) discloses a power delivery network (item 450).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Song for the purpose of providing/delivering power.
Chen as modified by Song does not specifically disclose the first surface of the first semiconductor chip is an active surface of the first semiconductor chip adjacent to a circuit layer comprising at least one transistor and the second surface of the first semiconductor chip is an inactive surface of the first semiconductor chip, the third surface of the second semiconductor chip is an active surface of the second semiconductor chip adjacent to a circuit layer comprising at least one transistor and the fourth surface of the second semiconductor chip is an inactive surface of the second semiconductor chip, the first chip stack includes third semiconductor chips stacked on the first surface of the first semiconductor chip, each of the third semiconductor chips is disposed such that an active surface thereof faces the first semiconductor chip, and an inactive surface thereof faces away from the first semiconductor chip, each active surface being adjacent to a circuit layer comprising at least one transistor.
Haba (Figs. 9A-9D, 10A-10D and associated text) discloses front-to-front, front-to-back and back-to-back bonding/stacking.
Therefore it would have been obvious to one ordinary skill in the art before the effective filing date to incorporate the teachings of Haba for the purpose of an electrical connection.
Chen as modified by Song and Haba discloses the Applicant’s claimed invention.
In regard to claim 3, Chen (Figs. 1, 3L, 6, 7, 8, 10 and associated text and items) as modified by Song (Fig. 8 and associated text) discloses wherein the top surface of the power delivery network is (item 100, Chen, item 450, Song) in direct contact with the second surface (bottom surface of item 120) of the first semiconductor chip (item 120) and the fourth surface (bottom surface of item 110) of the second semiconductor chip (item 110).
In regard to claim 4, Chen (Figs. 1, 3L, 6, 7, 8, 10 and associated text and items) as modified by Song (Fig. 8 and associated text) discloses wherein: the first semiconductor chip (item 120) includes a first chip pad (items P1, P2 or top portions of V1, Figs. 4, 5) adjacent to the first surface, each of the third semiconductor chips (items 152a-152d) includes a second chip pad (item P) adjacent to a bottom surface of each of the third semiconductor chips (items 152a-152d), and the first chip pad (item P1, P2 or top portion of V1) of the first semiconductor chip and the second chip pad (item P) of a lowermost one of the third semiconductor chips (items 152a-152d) are bonded to each other. Examiner has not given a special definition to the term “bonded”, therefore certain features can be “directly” or “indirectly” bonded.
In regard to claim 6, Chen (Figs. 1, 3L, 6, 7, 8, 10 and associated text and items) as modified by Song (Fig. 8 and associated text) discloses wherein adjacent ones of the third semiconductor chips (items 152a-152d) are in direct contact with each other.
In regard to claim 10, Chen (Figs. 1, 3L, 6, 7, 8, 10 and associated text and items) as modified by Song (Fig. 8 and associated text) discloses wherein the power delivery network (item 450) includes conductive interconnection lines (items 104a, 104b, 108, Chen, shown but not labeled, Song) and an interconnection insulating layer (item 102, Chen, shown but not labeled, Song).
In regard to claim 11, Chen (Figs. 1, 3L, 6, 7, 8, 10 and associated text and items) as modified by Song (Fig. 8 and associated text) discloses wherein the conductive interconnection lines (items 104a, 104b, 108, Chen, shown but not labeled, Song) include a metallic material (paragraphs 25, 26, copper or other suitable metal, Chen) , and the interconnection insulating layer (item 102) includes at least one of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or low-k dielectric layers (paragraph 25, Chen).
In regard to claim 12, Chen (Figs. 1, 3L, 6, 7, 8, 10 and associated text and items) as modified by Song (Fig. 8 and associated text) discloses wherein the power delivery network (item 100, Chen, item 450, Song) further includes outer terminals (item 188, Chen, items 492, 490) on a bottom surface of the power delivery network (item 100, Chen, item 450, Song).
In regard to claim 21, Chen (Figs. 1, 3L, 6, 7, 8, 10 and associated text and items) discloses wherein the second chip stack (item 140) includes at least one dummy chip (items 144a-144d).
In regard to claim 22, Chen (Figs. 1, 3L, 6, 7, 8, 10 and associated text and items) as modified by Song (Fig. 8 and associated text) discloses wherein the first chip stack (item 150) and the second semiconductor chip (item 110) are electrically connected to each other through the interconnect structure [power delivery network] (item 100)through an electrical routing path including a second via penetrating the second semiconductor chip (item 110) to directly contact the interconnect structure [power delivery network] (item 100), and a first via penetrating the first semiconductor chip (item 120) to directly contact the interconnect structure [power delivery network] (item 100).
Claim(s) 2, 4, 5, 7-9, 13-15 and 23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (Chen) (US 2022/0093564 A1) in view of Song et al. (Song) (US 2022/0200735 A1 now US 11,444,068 B2) as evidenced or in view of Haba et al. (Haba) (US 2020/0227367 A1) as applied to claims 1, 3, 6, 10-12, 21 and 22 above, and further in view of Hu et al. (Hu) (US 2020/0343218 A1).
In regard to claim 2, Chen (Figs. 1, 3L, 6, 7, 8, 10 and associated text and items) as modified by Song (Fig. 8 and associated text) does not specifically disclose further comprising an upper silicon substrate on the first chip stack and the second chip stack.
Hu (Figs. 1, 3, 4, 5, 10, 11, 12 and associated text) discloses further comprising an upper silicon substrate (item S, 400, paragraphs 13, 88) on the first chip stack and the second chip stack.
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Hu for the purpose of protection/device free cover member or device containing cover member.
In regard to claim 4, Chen (Figs. 1, 3L, 6, 7, 8, 10 and associated text and items) as modified by Song (Fig. 8 and associated text) discloses wherein: the first semiconductor chip (item 120) includes a first chip pad (items P1, P2 or top portions of V1, Figs. 4, 5) adjacent to the first surface, each of the third semiconductor chips (items 152a-152d) includes a second chip pad (item P) adjacent to a bottom surface of each of the third semiconductor chips (items 152a-152d), and the first chip pad (item P1, P2 or top portion of V1) of the first semiconductor chip and the second chip pad (item P) of a lowermost one of the third semiconductor chips (items 152a-152d) are bonded to each other.
Hu ((Figs. 1, 3, 4, 5, 10, 11, 12 and associated text) discloses wherein: the first semiconductor chip (lowermost items C1, C2 or C3) includes a first chip pad (items BP11, BP12, BP21, BP22, BP31 of lowermost C1, C2 or C3) adjacent to the first surface (top surface of lowermost items C1, C2 or C3), each of the third semiconductor chips (middle to top items C1, C2 or C3) includes a second chip pad (items BP11, BP12, BP21, BP22, BP31) adjacent to a bottom surface of each of the third semiconductor chips (middle to top items C1, C2 or C3), and the first chip pad (items BP11, BP12, BP21, BP22, BP31 of lowermost C1, C2 or C3) of the first semiconductor chip (lowermost items C1, C2 or C3) and the second chip pad (items BP11, BP12, BP21, BP22, BP31) of a lowermost one of the third semiconductor chips (middle items C1, C2 or C3) are directly bonded to each other.
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Hu for the purpose of an electrical connection.
In regard to claim 5, Chen (Figs. 1, 3L, 6, 7, 8, 10 and associated text and items) as modified by Song (Fig. 8 and associated text), Haba and Hu ((Figs. 1, 3, 4, 5, 10, 11, 12 and associated text) discloses wherein the first chip pad (items P1, P2 or top portions of V1, Figs. 4, 5, Chen, items BP11, BP12, BP21, BP22, BP31 of lowermost C1, C2 or C3) and the second chip pad (item P, Chen, items BP11, BP12, BP21, BP22, BP31 of middle item C1, C2, or C3) form a single object that is formed of the same metallic material.
In regard to claim 7, Chen (Figs. 1, 3L, 6, 7, 8, 10 and associated text and items) as modified by Song (Fig. 8 and associated text) discloses wherein: the first semiconductor chip (item 120) includes a first via (item V1) penetrating a portion of the first semiconductor chip (item 120), each of the third semiconductor chips (items 152a-152d) includes a third via (item V2, Fig. 3G) penetrating a portion of each of the third semiconductor chips (items 152a-152d), but does not specifically disclose the second semiconductor chip includes a second via penetrating a portion of the second semiconductor chip.
Hu (Figs. 1, 3, 4, 5, 10, 11, 12 and associated text) discloses the second semiconductor chip includes a second via (items TSV1, TSV2, BV11, BV21 or BV31) penetrating a portion of the second semiconductor chip (lowermost items C1, C2 or C3).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Hu for the purpose of an electrical connection.
Chen as modified by Song, Haba and Hu does not specifically disclose a diameter of the third via is larger than each of a diameter of the first via and a diameter of the second via.
It would have been obvious to modify the invention to include a diameter of the third via being larger than each of a diameter of the first via and a diameter of the second via, since such a modification would have involved a mere change in the size/shape of a component. A change in size/shape is generally recognized as being within the level of ordinary skill in the art (In re Rose, 105 USPQ 237 (CCPA 1955)).
It would have also been obvious to one having ordinary skill in the art at the time of the invention to modify the invention to include a diameter of the third via being larger than each of a diameter of the first via and a diameter of the second via, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art (In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980)).
In regards to claim 8, Chen as modified by Song, Haba and Hu does not specifically disclose The semiconductor package as claimed in claim 7, wherein a length of the third via is larger than a length of the first via and a length of the second via.
It would have been obvious to modify the invention to include a length of the third via being larger than a length of the first via and a length of the second via, since such a modification would have involved a mere change in the size/shape of a component. A change in size/shape is generally recognized as being within the level of ordinary skill in the art (In re Rose, 105 USPQ 237 (CCPA 1955)).
It would have also been obvious to one having ordinary skill in the art at the time of the invention to modify the invention to include a length of the third via being larger than a length of the first via and a length of the second via, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art (In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980)).
In regard to claim 9, Chen (Figs. 1, 3L, 6, 7, 8, 10 and associated text and items) as modified by Song (Fig. 8 and associated text) and Hu (Figs. 1, 3, 4, 5, 10, 11, 12 and associated text) discloses wherein the power delivery network (item 100, Chen, item 450, Song) includes conductive interconnection lines (items 104a, 104b, 108, Chen, shown but not labeled, Song) and an interconnection insulating layer (item 102, Chen, shown but not labeled, Song, item BDLi), and each of the first and second vias (items TSV1, TSV2, BV11, BV21 or BV31, Hu) is in direct contact with a corresponding one of the conductive interconnection lines (items 104a, 104b, 108, Chen, shown but not labeled, Song, items BVia, BVib, BVic, BPia, BPib, Bpic, Hu).
In regards to claim 13, Chen (Figs. 1, 3L, 6, 7, 8, 10 and associated text and items) discloses a semiconductor package (Figs. 1, 3L, 6, 7, 8, 10), comprising: a first semiconductor chip (item 120) having a first surface (top surface of item 120) and a second surface (bottom surface of item 120), which are opposite to each other, the first surface (top surface of item 120) being an active surface of the first semiconductor chip (item 120); a second semiconductor chip (item 110) horizontally spaced apart from the first semiconductor chip (item 120), the second semiconductor chip (item 110) having a third surface (top surface of item 110) and a fourth surface (bottom surface of item 110), which are opposite to each other, the third surface (top surface of item 110) being an active surface of the second semiconductor chip (item 110); an interconnect structure [a power delivery network] (item 100) in direct contact with the second surface (bottom surface of item 120) of the first semiconductor chip (item 120) and the fourth surface (bottom surface of item 110) of the second semiconductor chip (item 110); third semiconductor chips (items 152a-152d) vertically stacked on the first surface (top surface of item 120) of the first semiconductor chip (item 120); dummy chips (items 140 or 144a-144d) disposed on the third surface (top surface of item 110) of the second semiconductor chip (item 110); the first semiconductor chip (item 120) includes a first via (item V1) penetrating a portion of the first semiconductor chip (item 120), the interconnect structure [a power delivery network] (item 100) includes conductive interconnection lines (items 104a, 104b, 108) and an interconnection insulating layer (item 102), each of the third semiconductor chips (items 152a-152d) is disposed such that an active surface of each of the third semiconductor chips (items 152a-152d) faces the first semiconductor chip (item 120), and the third semiconductor chips (items 152a-152d) are electrically connected to the second semiconductor chip (item 110) through the interconnect structure [a power delivery network] (item 100), but does not specifically disclose a power delivery network.
Song (Fig. 8 and associated text) discloses a power delivery network (item 450).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Song for the purpose of providing/delivering power.
Chen as modified by Song does not specifically disclose the active surface being adjacent to a circuit layer of the first semiconductor chip that comprises at least one transistor; a second semiconductor chip horizontally spaced apart from the first semiconductor chip, the second semiconductor chip having a third surface and a fourth surface, which are opposite to each other, the third surface being an active surface and the fourth surface being an inactive surface of the second semiconductor chip, the active surface being adjacent to a circuit layer of the second semiconductor chip that comprises at least one transistor; a power delivery network in direct contact with the second surface of the first semiconductor chip and the fourth surface of the second semiconductor chip; third semiconductor chips vertically stacked on the first surface of the first semiconductor chip; dummy chips disposed on the third surface of the second semiconductor chip; and a silicon substrate disposed on the third semiconductor chips and the dummy chips, wherein: the first semiconductor chip includes a first via penetrating a portion of the first semiconductor chip, the second semiconductor chip includes a second via penetrating a portion of the second semiconductor chip, the power delivery network includes conductive interconnection lines and an interconnection insulating layer, each of the first and second vias is in direct contact with a corresponding one of the conductive interconnection lines, each of the third semiconductor chips is disposed such that an active surface of each of the third semiconductor chips faces the first semiconductor chip, each active surface adjacent to a circuit layer of the respective third semiconductor chip that comprises at least one transistor.
Haba (Figs. 9A-9D, 10A-10D and associated text) discloses front-to-front, front-to-back and back-to-back bonding/stacking.
Therefore it would have been obvious to one ordinary skill in the art before the effective filing date to incorporate the teachings of Haba for the purpose of an electrical connection.
Chen as modified by Song and Haba does not specifically disclose and a silicon substrate disposed on the third semiconductor chips and the dummy chips,…the second semiconductor chip includes a second via penetrating a portion of the second semiconductor chip…each of the first and second vias is in direct contact with a corresponding one of the conductive interconnection lines.
Hu (Figs. 1, 3, 4, 5, 10, 11, 12 and associated text) discloses further comprising an upper silicon substrate (item S, 400, paragraphs 13, 88) on the first chip stack and the second chip stack… the second semiconductor chip (lowermost items C1, C2 or C3) includes a second via (items TSV1, TSV2, BV11, BV21 or BV31) penetrating a portion of the second semiconductor chip (lowermost items C1, C2 or C3) …each of the first and second vias (items TSV1, TSV2, BV11, BV21 or BV31) is in direct contact with a corresponding one of the conductive interconnection lines (MP1, MP2, BPia, BPib, Bpic).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Hu for the purpose of protection/device free cover member or device containing cover member and an electrical connection.
In regard to claim 14, Chen (Figs. 1, 3L, 6, 7, 8, 10 and associated text and items) as modified by Song (Fig. 8 and associated text) and Hu (Figs. 1, 3, 4, 5, 10, 11, 12 and associated text) discloses wherein each of the third semiconductor chips (items 152a-152d, Chen) includes a third via (item V2, Fig. 3G, Chen) penetrating a portion of each of the third semiconductor chips (items 152a-152d, Chen), but does not specifically disclose a diameter of the third via is larger than a diameter of the first via and a diameter of the second via.
It would have been obvious to modify the invention to include a diameter of the third via being larger than each of a diameter of the first via and a diameter of the second via, since such a modification would have involved a mere change in the size/shape of a component. A change in size/shape is generally recognized as being within the level of ordinary skill in the art (In re Rose, 105 USPQ 237 (CCPA 1955)).
It would have also been obvious to one having ordinary skill in the art at the time of the invention to modify the invention to include a diameter of the third via being larger than each of a diameter of the first via and a diameter of the second via, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art (In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980)).
In regards to claim 15, Chen (Figs. 1, 3L, 6, 7, 8, 10 and associated text and items) discloses wherein each of the third semiconductor chips (items 152a-152d) is in direct contact with others of the third semiconductor chips (items 152a-152d) adjacent thereto.
In regard to claim 23, Chen (Figs. 1, 3L, 6, 7, 8, 10 and associated text and items) as modified by Song, Haba, and Hu (Figs. 1, 3, 4, 5, 10, 11, 12 and associated text) discloses wherein the upper silicon substrate (item S, 400, paragraphs 13, 88) is a dummy silicon substrate.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TELLY D GREEN whose telephone number is (571)270-3204. The examiner can normally be reached M-F 8am-5pm.
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TELLY D. GREEN
Examiner
Art Unit 2898
/TELLY D GREEN/Primary Examiner, Art Unit 2898 June 24, 2026
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