DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement(s) (IDS) submitted on 07/07/2023 is/are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement(s) is/are being considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-7, 10-14, and 17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kang (U.S. PG Pub No US2018/0358328A1).
Regarding claim 1, Kang teaches a semiconductor package (P100) fig. 1 [0014] comprising:
a first redistribution structure (lower 110s with lower 120s) fig. 1 [0014-0015] comprising a first redistribution pattern (lower 120 conductive layers) [0014] and a first redistribution insulating layer (lower 110 insulating layer) [0014], wherein the first redistribution pattern (lower 120) comprises a first redistribution via (V1 of lower 120) fig. 1 [0014] extending in a vertical direction within the first redistribution insulating layer (lower 110);
a second redistribution structure (upper 110 with upper 120s) fig. 1 [0014] on the first redistribution structure (lower 110 with lower 120s) and comprising a second redistribution pattern (upper 120s) fig. 1 [0014-0015] and a second redistribution insulating layer (upper 110) fig. 1 [0014-0015], wherein the second redistribution pattern (upper 120s) comprises a lower redistribution pad (upper 120 conductive pattern “LP” with surface for electrical connections) (see annotated fig. 1 below) at a lower surface of the second redistribution insulating layer (upper 110);
a first semiconductor chip (310) fig. 1 [0019] on the second redistribution structure (upper 120); and
a second semiconductor chip (320) fig. 1 [0030, 0032] on (supported by) the first semiconductor chip (310),
wherein an upper surface of the first redistribution insulating layer (lower 110) is in (direct) contact with the lower surface of the second redistribution insulating layer (upper 110) (see annotated fig. 1 below), and
wherein the first redistribution via (V1) of the first redistribution structure (lower 120s) is in (direct) contact with the lower redistribution pad (LP) of the second redistribution structure (upper 120).
[AltContent: rect][AltContent: arrow][AltContent: textbox (Diagonal-line)][AltContent: connector][AltContent: arrow][AltContent: textbox (Conductive post )][AltContent: rect][AltContent: textbox (Conductive pillar )][AltContent: arrow][AltContent: rect][AltContent: arrow][AltContent: textbox (3rd redistribution layer )][AltContent: arrow][AltContent: textbox (LP)][AltContent: arrow][AltContent: textbox (V1)][AltContent: rect][AltContent: arrow][AltContent: textbox (2nd redistribution layer )][AltContent: textbox (1st redistribution layer )][AltContent: arrow][AltContent: rect]
PNG
media_image1.png
493
1253
media_image1.png
Greyscale
Annotated fig. 1 of Kang
Regarding claim 2, Kang teaches the semiconductor package (P100) fig. 1 [0014] of claim 1. Kang also teaches further comprising:
a third redistribution structure (upper 410, 420) fig. 1 [0022] that is (vertically) between the first semiconductor chip (310) fig. 1 [0022] and the second semiconductor chip (320) fig. 1 [0030, 0032] and comprises a third redistribution pattern (upper 420s) fig. 1 [0022] and a third redistribution insulating layer (upper 410) fig. 1 [0022]; and
a conductive post (right 221 with right 222) fig. 1 [0018] extending (vertically) between the second redistribution structure (upper 110) and the third redistribution structure (comprising upper 410) and electrically connecting [0018] the second redistribution pattern (upper 120s) to the third redistribution pattern (comprising upper 420s) [0018].
Regarding claim 3, Kang teaches the semiconductor package (P100) fig. 1 [0014] of claim 2. Kang also teaches further comprising:
a first connection bump (311) fig. 1 [0020] between the first semiconductor chip (310) fig. 1 [0019] and the second redistribution structure (upper 110 with upper 120s) fig. 1 [0014];
a conductive pillar (left 221 with left 223) fig. 1 [0018] (diagonally) between the first semiconductor chip (310) and the third redistribution structure (upper 410, 420) fig. 1 [0022]; and
a second connection bump (321) fig. 1 [0032] (vertically) between the second semiconductor chip (320) fig. 1 [0024, 0032] and the third redistribution structure (upper 410, 420).
Regarding claim 4, Kang teaches the semiconductor package (P100) fig. 1 [0014] of claim 3. Kang also teaches further comprising a first molding layer (210(s)) fig. 1 [0017-0018] between the second redistribution structure (upper 110 with upper 120s) fig. 1 [0014] and the third redistribution structure (upper 410, 420) fig. 1 [0022],
wherein the first molding layer (210) at least partially (laterally) surrounds the first semiconductor chip (310) fig. 1 [0019], the first connection bump (311) fig. 1 [0020], and the conductive pillar (left 221 with left 223) fig. 1 [0018],
wherein the conductive post (right 221 with right 222) fig. 1 [0018] vertically penetrates the first molding layer (210).
Regarding claim 5, Kang teaches the semiconductor package (P100) fig. 1 [0014] of claim 4. Kang also teaches wherein an upper surface (200b) fig. 1 [0017] of the first molding layer (210) fig. 1 [0017] is coplanar with an upper surface of the conductive pillar (left 221 with left 223 comprising uppermost surface of 223) fig. 1 [0018].
Regarding claim 6, Kang teaches the semiconductor package (P100) fig. 1 [0014] of claim 4. Kang also teaches further comprising a second molding layer (510) fig. 1 [0028] at least partially surrounding the second semiconductor chip (320) fig. 1 [0030, 0032] on the third redistribution structure (upper 410, 420) fig. 1 [0022].
Regarding claim 7, Kang teaches the semiconductor package (P100) fig. 1 [0014] of claim 6. Kang also teaches wherein an upper surface of the second molding layer (500b) fig. 1 [0034] is coplanar with an upper surface of the second semiconductor chip (uppermost surface of 320) fig. 1 [0030].
Regarding claim 10, Kang teaches the semiconductor package (P100) fig. 1 [0014] of claim 1. Kang also teaches further comprising:
a frame substrate (210(s) and 510(s)) fig. 1 [0017-0018, 0028] on an outer portion (top) of the first redistribution structure (lower 110s with lower 120s) fig. 1 [0014-0015] and comprising a frame body (210 and 510) and a vertical connection conductor (521) fig. 1 [0018] in the frame body (210 and 510), wherein the frame body (210 and 510) (partially) has a through hole (gap in 210, 510 and intervening layers) fig. 1 [0017-0018] that accommodates the first semiconductor chip (310) fig. 1 [0019] and the second semiconductor chip (320) fig. 1 [0030, 0032]; and
a third molding layer (530) fig. 1 [0033] on (supported by) the first semiconductor chip (310) and the second semiconductor chip (320) within the through hole of the frame substrate (210(s) and 510s) fig. 1 [0017-0018, 0028].
Regarding claim 11, Kang teaches the semiconductor package (P100) fig. 1 [0014] of claim 10. Kang also teaches further comprising a fourth redistribution structure (upper 410, 420) fig. 1 [0022] on the third molding layer (530) fig. 1 [0033] and comprising a fourth redistribution pattern (upper 420) fig. 1 [0022] electrically connected to the vertical connection conductor (521) fig. 1 [0018].
Regarding claim 12, Kang teaches the semiconductor package (P100) fig. 1 [0014] of claim 11. Kang also teaches further comprising a third semiconductor chip (320 may host additional chips of a plurality) fig. 1 [0032] on the fourth redistribution structure (upper 410, 420) fig. 1 [0022].
Regarding claim 13, Kang teaches the semiconductor package (P100) fig. 1 [0014] of claim 1. Kang also teaches further comprising:
a third molding layer (lower 410) fig. 1 [0022] on (supported by) the (top of) first semiconductor chip (310) fig. 1 [0019] and the (bottom of) second semiconductor chip (upper 320) fig. 1 [0030];
a vertical connection conductor (425) fig. 1 [0022] penetrating the third molding layer (lower 410) fig. 1 [0022]; and
a fourth redistribution pattern (lower 420s) fig. 1 [0022] lower extending on (in) the third molding layer (lower 410) fig. 1 [0022] and electrically connected to the vertical connection conductor (425) [0023].
Regarding claim 14, Kang teaches a semiconductor package (P100) fig. 1 [0014] comprising:
a first redistribution structure (lower 110s with lower 120s) fig. 1 [0014-0015] comprising a first redistribution pattern (lower 120 conductive layers) [0014] and a first redistribution insulating layer (lower 110 insulating layer) [0014], wherein the first redistribution pattern (lower 120s) comprises a first redistribution via (V1) (see annotated fig. 1 below) extending in a vertical direction (downward) from an upper surface of the first redistribution insulating layer (lower 110);
a sub package (SP) (see annotated fig. 1 below) on a central portion of the first redistribution structure (lower 110);
a frame substrate (lower 210) fig. 1 [0017-0018] on (supported by) an outer portion (bottom) of the first redistribution structure (lower 110 with lower 120s) and comprising a frame body (lower 210) having a through hole (hole in lower 210 hosting 230, 310) fig. 1 [0020] (partially) accommodating the sub package (SP), and the frame substrate (lower 210) further comprising a vertical connection conductor (lower 221) fig. 1 [0018] extending in the vertical direction within the frame body (lower 210); and
a package molding layer (230 with lower 410) fig. 1 [0021-0022] on (in) the sub package (SP) within the through hole (hole in lower 210 hosting 230, 310) fig. 1 [0020] defined by outer sidewalls of the frame substrate (lower 210), wherein the sub package (SP) comprises:
a second redistribution structure (upper 110 with upper 120s) fig. 1 [0014] comprising a second redistribution pattern (upper 120s) fig. 1 [0014-0015] and a second redistribution insulating layer (upper 110) fig. 1 [0014-0015], wherein the second redistribution pattern (upper 120s) comprises a lower redistribution pad (upper 120 conductive pattern “LP” with surface for electrical connections) (see annotated fig. 1 below) at a lower surface of the second redistribution insulating layer (upper 110);
a first semiconductor chip (310) fig. 1 [0019] on the second redistribution structure (upper 110 with upper 120s);
a first molding layer (upper 210) fig. 1 [0017] at least partially (laterally) surrounding the first semiconductor chip (310) on (supported by) the second redistribution structure (upper 110 with upper 120s);
a third redistribution structure (upper 410, upper 420s) fig. 1 [0022] on (supported by) the first semiconductor chip (310) and the first molding layer (upper 210) and comprising a third redistribution pattern (upper 420s) fig. 1 [0022] and a third redistribution insulating layer (upper 410) fig. 1 [0022];
a conductive post (upper, right 221 with right 222) fig. 1 [0018] (see annotated fig. 1 below) extending (vertically) between the second redistribution structure (upper 110) and the third redistribution structure (comprising upper 410 and upper 420) and electrically connecting [0018] the second redistribution pattern (upper 120s) to the third redistribution pattern (comprising upper 420s) [0018]; and
a second semiconductor chip (320) fig. 1 [0030] on the third redistribution structure (comprising upper 410 and upper 420),
wherein the upper surface of the first redistribution insulating layer (lower 110) is in direct contact with the lower surface of the second redistribution insulating layer (upper 110) (see annotated fig. 1 below), and
wherein the first redistribution via (V1) of the first redistribution structure (lower 110 with lower 120s) is in direct contact with the lower redistribution pad (LP) of the second redistribution structure (upper 110 with upper 120s) (see annotated fig. 1 below).
[AltContent: rect][AltContent: textbox (SP)][AltContent: arrow][AltContent: rect][AltContent: rect][AltContent: arrow][AltContent: textbox (Diagonal-line)][AltContent: connector][AltContent: arrow][AltContent: textbox (Conductive post )][AltContent: rect][AltContent: textbox (Conductive pillar )][AltContent: arrow][AltContent: rect][AltContent: arrow][AltContent: textbox (3rd redistribution layer )][AltContent: arrow][AltContent: textbox (LP)][AltContent: arrow][AltContent: textbox (V1)][AltContent: rect][AltContent: arrow][AltContent: textbox (2nd redistribution layer )][AltContent: textbox (1st redistribution layer )][AltContent: arrow]
PNG
media_image1.png
493
1253
media_image1.png
Greyscale
Annotated fig. 1 of Kang
Regarding claim 17, Kang teaches the semiconductor package (P100) fig. 1 [0014] of claim 16. Kang also teaches wherein the first molding layer (upper 210) fig. 1 [0017] at least partially (laterally) surrounds the first semiconductor chip (310) fig. 1 [0019], the first connection bump (311) fig. 1 [0020] (311 laterally surrounded in top-view), and the conductive pillar (left 221 with left 223) fig. 1 [0018] (see annotated fig. 1 above), an upper surface of the first molding layer (upper 210) fig. 1 [0017] is coplanar with an upper surface of the conductive pillar (left 221 with left 223) fig. 1 [0018] (see annotated fig. 1 above).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over Kang (U.S. PG Pub No US2018/0358328A1), as applied in claim 1 above, in view of Yang (U.S. PG Pub No US2015/0061120A1).
Regarding claim 8, Kang teaches the semiconductor package (P100) fig. 1 [0014] of claim 1. Kang wherein the first semiconductor chip (310) fig. 1 [0019] comprises:
a first semiconductor substrate (310).
However, Kang does not explicitly disclose comprising a first active surface and a first inactive surface that are opposite to each other, wherein the first active surface faces towards the second semiconductor chip (320) fig. 1 [0030, 0032];
a first through electrode penetrating the first semiconductor substrate (310);
a first front-side interconnect structure on the first active surface of the first semiconductor substrate (310) and comprising a first interconnect pattern electrically connected to the first through electrode;
and a first backside interconnect structure between the first inactive surface of the first semiconductor substrate (310) and the second redistribution structure and comprising a first backside interconnect pattern, the first backside interconnect structure electrically connected to the first through electrode.
Yang teaches a semiconductor package (10) fig. 1 [0024] comprising a first semiconductor substrate (110 with 130) fig. 1 [0027-0028] comprising a first active surface (top of 110) [0028] and a first inactive surface (bottom of 130) that are opposite to each other, wherein the first active surface (top of 110) faces towards the second semiconductor chip (210) fig. 1 [0037];
a first through electrode (lower 170) fig. 1 [0025] penetrating the first semiconductor substrate (110);
a first front-side interconnect structure (180) fig. 1 [0035] on the first active surface (top of 110) of the first semiconductor substrate (110) and comprising a first interconnect pattern (181) [0035] electrically connected to the first through electrode (lower 170);
and a first backside interconnect structure (133) fig. 1 [0029] (partially) between the first inactive surface (bottom 130) of the first semiconductor substrate (110) and the second redistribution structure (530) fig. 1 [0049] and comprising a first backside interconnect pattern (133), the first backside interconnect structure (133) electrically connected to the first through electrode (lower 170).
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the semiconductor package of Kang to include the additional circuitry penetrating through and connected to the active chips [0025-0031] in order to increase the number of electrical connections and contact area [0019] of the chip [0024] as well as aid in heat radiation management [0048-0050], as taught by Yang.
Regarding claim 9, Kang teaches the semiconductor package (P100) fig. 1 [0014] of claim 8. Kang wherein the second semiconductor chip (320) fig. 1 [0030] comprises:
a second semiconductor substrate (320).
However, Kang does not explicitly disclose wherein the second semiconductor chip comprises (320):
a second semiconductor substrate (320) comprising a second active surface and a second inactive surface that are opposite to each other, wherein the second active surface faces towards the first semiconductor chip (310) fig. 1 [0017-0019]; and
a second interconnect structure between the second active surface of the second semiconductor substrate (320) and the first semiconductor chip (310) and comprising a second interconnect pattern.
Yang teaches a semiconductor package (10) fig. 1 [0024] wherein the second semiconductor chip comprises (210 with 520) fig. 1 [0037, 0046]:
a second semiconductor substrate (210 with 520) fig. 1 [0037, 0046] comprising a second active surface (bottom of 210) [0037] and a second inactive surface (top of 520) that are opposite to each other, wherein the second active surface (bottom of 210) faces towards the first semiconductor chip (310) fig. 1 [0017-0019]; and
a second interconnect structure (290) fig. 1 [0039] between the second active surface (bottom of 210) of the second semiconductor substrate (210) and the first semiconductor chip (110) fig. 1 [0025] and comprising a second interconnect pattern (290) [0039].
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the semiconductor package of Kang to include the additional circuitry penetrating through and connected to the active chips [0025-0031] in order to increase the number of electrical connections and contact area [0019] of the chip [0024] as well as aid in heat radiation management [0048-0050], as taught by Yang.
11. Claim(s) 15-16 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Kang (U.S. PG Pub No US2018/0358328A1), as applied in claim 14 above, in view of Jang (U.S. PG Pub No US2021/0111140A1).
Regarding claim 15, Kang teaches the semiconductor package (P100) fig. 1 [0014] of claim 14. Kang also teaches wherein a (outer) sidewall of the second redistribution structure (upper 110 with upper 120s) fig. 1 [0014], a (outer) sidewall of the first molding layer (upper 210) fig. 1 [0017], and a (outer) sidewall of the third redistribution structure (upper 410, 420) fig. 1 [0022] are aligned with each other in the vertical direction.
However, Kang does not explicitly disclose wherein the package molding layer (230 with lower 410) fig. 1 [0021-0022] extends along the sidewall of the second redistribution structure, the sidewall of the first molding layer, and the sidewall of the third redistribution structure.
Jang teaches a semiconductor package [see fig. 22, 0122-0123] wherein the package molding layer (600) fig. 22 [0123] extends along the (outer) sidewall of the second redistribution structure (130) fig. 22 [0100], the sidewall of the first molding layer (110) fig. 22 [0100], and the sidewall of the third redistribution structure (120) fig. 22 [0100].
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the package of Kang such that the molding materials(s) of the package are formed as a single, continuous molding layer covering outer sidewalls of the redistribution layers, internal molding layers, and chips [0054, 0060-0062, 0100] in order to protect the package from the formation of cracks [0066, 0116], as taught by Jang.
Regarding claim 16, Kang teaches the semiconductor package (P100) fig. 1 [0014] of claim 15. Kang also teaches further comprising:
a first connection bump (311) fig. 1 [0020] between the first semiconductor chip (310) fig. 1 [0020] and the second redistribution structure (upper 110 with upper 120s) fig. 1 [0014-0015] and electrically connecting the first semiconductor chip (310) to the second redistribution pattern (upper 120);
a conductive pillar (left 221 with left 223) fig. 1 [0018] (diagonally) (see annotated fig. 1 above) between the first semiconductor chip (310) and the third redistribution structure (upper 410 with upper 420s) and electrically connecting the first semiconductor chip (310) and the third redistribution pattern (upper 420s) (commonly connected through interconnect substrates [0019]);
a second connection bump (321) fig. 1 [0032] between the second semiconductor chip (320) fig. 1 [0030] and the third redistribution structure (upper 410, 420) fig. 1 [0022] and electrically connecting the second semiconductor chip (320) to the third redistribution pattern (upper 420s); and
a second molding layer (510) fig. 1 [0028] at least partially surrounding the second semiconductor chip (320) on the third redistribution structure (upper 410 with upper 420s), wherein a sidewall of the second molding layer (510) is aligned with a sidewall of the third redistribution structure (upper 410) in the vertical direction.
However, Kang does not explicitly disclose wherein the package molding layer (230 with lower 410) fig. 1 [0021-0022] extends along the sidewall of the second molding layer (510).
Jang teaches a semiconductor package [see fig. 22, 0122-0123] wherein the package molding layer (600) fig. 22 [0123] extends along the (outer) sidewall of the second molding layer (140) fig. 22 [0055].
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the package of Kang such that the molding materials(s) of the package are formed as a single, continuous molding layer covering outer sidewalls of the redistribution layers, internal molding layers, and chips [0054, 0060-0062, 0100] in order to protect the package from the formation of cracks [0066, 0116], as taught by Jang.
Regarding claim 18, Kang teaches the semiconductor package (P100) fig. 1 [0014] of claim 15. However, Kang does not explicitly disclose wherein the package molding layer (230 with lower 410) fig. 1 [0021-0022] directly contacts a sidewall of the second semiconductor chip (320) fig. 1 [0030] and extends along the sidewall of the second semiconductor chip (320).
Jang teaches a semiconductor package [see fig. 22, 0122-0123] wherein the package molding layer (600) fig. 22 [0123] directly contacts a sidewall of the second semiconductor chip (310) fig. 22 [0071] and extends along the sidewall of the second semiconductor chip (310).
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the package of Kang such that the molding materials(s) of the package are formed as a single, continuous molding layer covering outer sidewalls of the redistribution layers, internal molding layers, and chips [0054, 0060-0062, 0100] in order to protect the package from the formation of cracks [0066, 0116], as taught by Jang.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Kang (U.S. PG Pub No US2018/0358328A1) in view of Choi (U.S. PG Pub No US2020/0273771A1).
Regarding claim 19, Kang teaches a semiconductor package (P100) fig. 1 [0014] comprising:
a first redistribution structure (lower 110s with lower 120s) fig. 1 [0014-0015] comprising a first redistribution pattern (lower 120 conductive layers) [0014] and a first redistribution insulating layer (lower 110 insulating layer) [0014], wherein the first redistribution pattern (lower 120 conductive layers) comprises a first redistribution via (V1) (see annotated fig. 1 below) extending in a vertical direction (downward) from an upper surface of the first redistribution insulating layer (lower 110);
a sub package (SP) (see annotated fig. 1 below) on (supported by) a central portion of the first redistribution structure (lower 110 with lower 120s);
a frame substrate (lower 210) fig. 1 [0017-0018] on (supported by) an outer portion (top) of the first redistribution structure (lower 110, 120) and comprising a frame body (210) having a through hole (hole in lower 210 hosting 230, 310) fig. 1 [0020] (partially) accommodating the sub package (SP), and the frame substrate (lower 210) further comprising a vertical connection conductor (lower 221) fig. 1 [0018] extending in the vertical direction within the frame body (lower 210); and
a package molding layer (230 with lower 410) fig. 1 [0021-0022] on (in) the sub package (SP) (partially) within the through hole (hole in lower 210) of the frame substrate (lower 210), wherein the sub package (SP) comprises:
a second redistribution structure (upper 110 with upper 120s) fig. 1 [0014] comprising a second redistribution pattern (upper 120s) fig. 1 [0014-0015] and a second redistribution insulating layer (upper 110) fig. 1 [0014-0015],
wherein the second redistribution pattern (upper 110, upper 120s) comprises a lower redistribution pad (LP) (see annotated fig. 1 below) at a lower surface of the second redistribution insulating layer (upper 110) and a second redistribution via (V2 of upper 120s) (see annotated fig. 1 below) extending in the vertical direction within the second redistribution insulating layer (upper 110);
a first semiconductor chip (310) fig. 1 [0019] on the second redistribution structure (upper 110, 120s);
a first connection bump (311) fig. 1 [0020] electrically connecting the second redistribution pattern (comprising upper 120s) to the first semiconductor chip (310) between (vertically-between) the second redistribution structure (upper 110, upper 120s) and the first semiconductor chip (310);
a first molding layer (upper 210) fig. 1 [0017] at least partially (laterally) surrounding the first semiconductor chip (310) on the second redistribution structure (upper 110, upper 120s);
a third redistribution structure (upper 410, upper 420s) fig. 1 [0022] on (supported by) the first semiconductor chip (310) and the first molding layer (upper 210) and comprising a third redistribution pattern (upper 420s) fig. 1 [0022] and a third redistribution insulating layer (upper 410) fig. 1 [0022];
a conductive post (upper, right 221 with right 222) fig. 1 [0018] (see annotated fig. 1 below) extending (vertically) between the second redistribution structure (upper 110) and the third redistribution structure (comprising upper 410 and upper 420) and electrically connecting [0018] the second redistribution pattern (upper 120s) to the third redistribution pattern (comprising upper 420s) [0018]; and
a second semiconductor chip (320) fig. 1 [0030] on the third redistribution structure (comprising upper 410 and upper 420),
a second connection bump (321) fig. 1 [0032] electrically connecting the third redistribution pattern (upper 420s) to the second semiconductor chip (330) between (vertically-between) the third redistribution structure (upper 410, upper 420s) and the second semiconductor chip (320); and
a second molding layer (510) fig. 1 [0028] at least partially surrounding the second semiconductor chip (320) on the third redistribution structure (upper 410, upper 420),
wherein the upper surface of the first redistribution insulating layer (lower 110) is in direct contact with the lower surface of the second redistribution insulating layer (upper 110) (see annotated fig. 1 below), and
wherein the first redistribution via (V1) of the first redistribution structure (lower 110 with lower 120s) is in direct contact with the lower redistribution pad (LP) of the second redistribution structure (upper 110 with upper 120s) (see annotated fig. 1 below),
and wherein the lower redistribution pad (LP) has a rectangular cross-sectional shape.
[AltContent: arrow][AltContent: textbox (V2)][AltContent: rect][AltContent: textbox (SP)][AltContent: arrow][AltContent: rect][AltContent: rect][AltContent: arrow][AltContent: textbox (Diagonal-line)][AltContent: connector][AltContent: arrow][AltContent: textbox (Conductive post )][AltContent: rect][AltContent: textbox (Conductive pillar )][AltContent: arrow][AltContent: rect][AltContent: arrow][AltContent: textbox (3rd redistribution layer )][AltContent: arrow][AltContent: textbox (LP)][AltContent: arrow][AltContent: textbox (V1)][AltContent: rect][AltContent: arrow][AltContent: textbox (2nd redistribution layer )][AltContent: textbox (1st redistribution layer )][AltContent: arrow]
PNG
media_image1.png
493
1253
media_image1.png
Greyscale
Annotated fig. 1 of Kang
However, Kang does not explicitly disclose wherein the first redistribution via (V1) has a tapered shape in which a width thereof decreases towards the upper surface of the first redistribution insulating layer (lower 110).
Choi teaches a semiconductor package (100) fig. 9 [0060] wherein the first redistribution via (113b) fig. 9 [0063] has a tapered shape in which a width thereof decreases towards the upper surface of the first redistribution insulating layer (top of 111b) fig. 9 [0070].
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the vias of the package of Kang to have tapered shapes [0074, 0083-0084] in order to modify the relative contact areas of the vias interfacing with other conductive structures [0074, 0083-0084] and increase the number of conductive patterns which may be incorporated into the package [0116], as taught by Kang.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Kang (U.S. PG Pub No US2018/0358328A1) modified by Choi (U.S. PG Pub No US2020/0273771A1), as applied in claim 19 above, and further in view of Kim (U.S. PG Pub No US2020/0043840A1).
Regarding claim 20, Kang in view of Choi teaches the semiconductor package (P100) fig. 1 [0014] of claim 19. However, Kang does not explicitly disclose wherein the first redistribution structure (113b) fig. 9 [0063] further comprises a first seed metal layer extending along a surface of the first redistribution via (V1),
wherein the second redistribution structure (upper 110s with upper 120s) fig. 1 [0014-0015] further comprises a second seed metal layer extending along a lower surface of the lower redistribution pad (LP),
wherein the first seed metal layer and the second seed metal layer are in contact with each other.
Kim teaches a semiconductor package (1) fig. 1A [0019] wherein the first redistribution structure (124) fig. 1A [0022] further comprises a first seed metal layer (122) fig. 1A [0022] extending along a surface of the first redistribution via (VO1) fig. 1A [0030-0032],
wherein the second redistribution structure (134) fig. 1A [0033] further comprises a second seed metal layer (132) fig. 1A [0033] extending along a lower surface of the lower redistribution pad (surface of 134 for connections),
wherein the first seed metal layer (122) and the second seed metal layer (132) are in (electrical) contact with each other.
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the redistribution structures of Kang to comprise the metal seed layers of Kim in order to provide additional, highly conductive material [0022-0024] between the redistribution layers so as to enhance their electrical connections [0022-0024] and improve overall redistribution structure reliability [0005, 0121], as taught by Kim.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Remaining references made available on the PTO-892 form are considered relevant to the present disclosure because they all feature multiple redistribution structures connected to multiple chips.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SEAN AYERS WINTERS whose telephone number is (571)270-3308. The examiner can normally be reached Monday - Friday 10:30 am - 7:00 pm (EST).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, N. Drew Richards can be reached at (571) 272-1736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/SEAN AYERS WINTERS/Examiner, Art Unit 2892 01/31/2026
/NORMAN D RICHARDS/Supervisory Patent Examiner, Art Unit 2892