DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Note by the Examiner
2. For clarity, the reference to specific claim numbers are presented in bold. Cited claim limitations are presented in bold the first time they are associated with a particular prior art disclosing the cited limitations, and subsequent reference to the already disclosed claim limitations are presented un-bolded. Certain elements from prior art which are not required by the claims are also presented un-bolded if they are particularly pertinent to understanding how the references are being combined. Item-to-item matching and Examiner explanations for 102 &/or 103 rejections have been provided in parenthesis.
Response to Amendment
3. Applicant’s amendment to the claims, filed on August 22, 2021, is acknowledged. Entry of amendment is accepted and made of record.
Response to Arguments/Remarks
4. Applicant’s arguments/remarks, see pgs. 7-9, with respect to the immediate allowance of the current application have been fully considered but are not persuasive.
The Examiner notes that upon further consideration a second non-final rejection is presented herein in a new grounds of rejection, as the prior arts of record are found to disclose some claim limitations previously indicated as allowable subject matter.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
5. Claims 1-5, 7, 9, 21-27, and 29 are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 2005/0280061 A1), hereinafter as L1, in view of Kim et al. (US 2022/0102334 A1), hereinafter as K1
6. Regarding Claim 1, L1 discloses a memory device (see in particular Figs. 1, 8-9 and [0054] “memory devices 656”), comprising:
a memory array structure (each of the capacitor portions of the DRAM cells 656, see Fig. 9 and [0078] “The capacitor may be MIM (Metal-Insulator-Metal), PIP (Poly-Insulator-Poly), MIP (Metal-Insulator-Poly)”) comprising:
a vertical transistor (MOSFET of element 101 having gate element 123 and active layer element 124, see in particular Fig. 8 and [0078]) having a first terminal (bottom n+ terminal of element 124, see [0077-0078] “SOI pillar 124”) and a second terminal (top n+ terminal of element 124);
a storage unit (see in particular Fig. 9 element Capacitor) having a first end (first top end) coupled to the first terminal of the vertical transistor (see in particular Fig. 9); and
a bit line (see in particular Figs. 8-9 element 122, see Fig. 8 element 122 (BL), bit line) coupled to the second terminal of the vertical transistor (see Figs. 8-9);
a first peripheral circuit (peripheral circuit of element 114, see [0058] “logic circuit 114”) coupled to a first surface (first bottom surface) of the memory array structure (see Fig. 9 in particular); and
wherein the vertical transistor comprises a semiconductor body (p-type portion of element 124, see [0077-0078] “SOI pillar 124”) extending in a first direction (vertical direction in the cross sectional view), and a gate structure (element 123, see Figs. 1, 8-9 element 123 (WL) with gate insulator element 183, see [0071] “gate insulator 183”) coupled to at least one side of the semiconductor body (see Figs. 1, 8-9); and wherein the bit line is in contact with the first peripheral circuit through a second contact structure (see Fig. 9 element 122 in contact with the first peripheral circuit element 114 through wiring electrically connected to element 131).
L1 does not explicitly disclose a second peripheral circuit coupled to a second surface of the memory array structure opposite to the first surface; and the gate structure is in contact with the first peripheral circuit through a third contact structure
K1 discloses (see Fig. 5B) a second peripheral circuit (peripheral circuit element PE2, see [0057] “second peripheral circuit region PE2”) coupled to a second surface (top surface) of the memory array (element CELL) structure opposite to the first surface (bottom surface) (see Fig. 5B); and the gate structure (word lines of elements GS, see [0073] “The plurality of gate lines 130 may include the plurality of word lines WL”) is in contact with the first peripheral circuit (element PE1, see [0097] “The others of the plurality of gate lines 130 may be connected to at least one or exactly one selected from a plurality of lower circuits CT1, which are included in a first peripheral circuit region PE1, through the conductive pad region 112 and the second contact structure CTS2”) through a third contact structure (see Fig. 5B element CML and CTS2 connects to element PE1)(see [0104-0105] The row decoder element 32 in Fig. 1 can be separated into both element PE1 and PE2 regions but are in electrical communication, see Fig. 5B illustrates at least one element TR1 and one element TR2 connected).
The second peripheral circuit and connections with the gate structure as taught by K1 is incorporated as a second peripheral circuit and connections with the gate structure of L1.
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of K1 with L1 because the combination allows for separation of high voltage and low voltage transistors (see K1 [0045]); and the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known number of peripheral circuitry and connections for another in a similar memory device to obtain predictable results (see K1 Fig. 5B).
7. Regarding Claim 2, L1, K1 disclose the memory device of claim 1, further comprising :
a first contact structure (see K1 Fig. 5B vertical contact structure between element TR2 and TR1 including element 164) extending through the memory array structure and in contact with the first peripheral circuit and the second peripheral circuit (see K1 Fig. 5B).
8. Regarding Claim 3, L1, K1 disclose the memory device of claim 2, further comprising:
a first bonding interface disposed between the memory array structure and the first peripheral circuit (see L1 Fig. 9 dotted line bonding interface – note, the manner in which the claim is currently recited does not require a particular material for the bonding interface); and
a second bonding interface disposed between the memory array structure and the second peripheral circuit (see L1 Fig. 9 dotted line bonding interface and K1 boundary between element PE2 and CELL – note, the manner in which the claim is currently recited does not require a particular material for the bonding interface).
9. Regarding Claim 4, L1, K1 disclose the memory device of claim 3, wherein (see K1 Fig. 5B) the second peripheral circuit comprises a first surface (first lower surface) in contact with the memory array structure through the second bonding interface (see Fig. 5B), and a second surface (second upper surface) comprising a pad structure (element 296, see [0107] “I/O pad 296 … may include a metal”).
10. Regarding Claim 5, L1, K1 disclose the memory device of claim 4, wherein (see L1) the first bonding interface is disposed between the first peripheral circuit and the storage unit (see in particular Fig. 9), and the bit line is disposed between the second bonding interface and the vertical transistor (see Figs. 8-9 the second bonding interface is at a topmost layer of the memory cell, and the bit line element 122 is between the top and the vertical transistor of element 111).
11. Regarding Claim 7, L1, K1 disclose the memory device of claim 1, wherein the second contact structure extends in the first direction longer than the vertical transistor (see L1 Fig. 9 electrical wiring connecting element 122 with the first peripheral circuit element 114 through wiring electrically connected to element 131; K1 the second contact conductive structure connecting between element TR2 and TR1, and see L1 Fig. 1 the combined second contact extends from element 114 to above element 101 longer than the vertical transistor of element 101), and the third contact structure extends in the first direction longer than the storage unit (see K1 the third contact structure at least elements CML and CTS2 extends a length above and below the memory elements MCA, and see L1 Fig. 1 the combined third contact structure extends above and below element 101 longer than the vertical transistor of element 101).
12. Regarding Claim 9, L1, K1 disclose the memory device of claim 4, wherein the first bonding interface is disposed between the first peripheral circuit and the bit line (see L1 in particular Figs. 8-9 and the second bonding interface is disposed between the second peripheral circuit and the storage unit (see L1 in particular Figs. 8-9 and K1 Fig. 5B).
13. Regarding Claim 21, L1 discloses a memory device (see in particular Figs. 1, 8-9 and [0054] “memory devices 656”), comprising:
a memory array structure (each of the capacitor portions of the DRAM cells 656, see Fig. 9 and [0078] “The capacitor may be MIM (Metal-Insulator-Metal), PIP (Poly-Insulator-Poly), MIP (Metal-Insulator-Poly)”) comprising:
a vertical transistor (MOSFET of element 101 having gate element 123 and active layer element 124, see in particular Fig. 8 and [0078]) having a first terminal (bottom n+ terminal of element 124, see [0077-0078] “SOI pillar 124”) and a second terminal (top n+ terminal of element 124);
a storage unit (see in particular Fig. 9 element Capacitor) having a first end (first top end) coupled to the first terminal of the vertical transistor (see in particular Fig. 9); and
a bit line (see in particular Figs. 8-9 element 122, see Fig. 8 element 122 (BL), bit line) coupled to the second terminal of the vertical transistor (see Figs. 8-9);
a first peripheral circuit (peripheral circuit of element 114, see [0058] “logic circuit 114”) coupled to a first surface (first bottom surface) of the memory array structure (see Fig. 9 in particular); and
wherein the vertical transistor comprises a semiconductor body (p-type portion of element 124, see [0077-0078] “SOI pillar 124”) extending in a first direction (vertical direction in the cross sectional view), and a gate structure (element 123, see Figs. 1, 8-9 element 123 (WL) with gate insulator element 183, see [0071] “gate insulator 183”) coupled to at least one side of the semiconductor body (see Figs. 1, 8-9); and
wherein a second end of the storage unit is in contact with the first peripheral circuit through a first contact structure (top end of the element Capacitor in contact with the first peripheral circuit of element 114 through the conductive contact structure connecting through element 131), and the first contact structure extends in the first direction longer than the vertical transistor (see Fig. 9)
L1 does not explicitly disclose a second peripheral circuit coupled to a second surface of the memory array structure opposite to the first surface.
K1 discloses (see Fig. 5B) a second peripheral circuit (peripheral circuit element PE2, see [0057] “second peripheral circuit region PE2”) coupled to a second surface (top surface) of the memory array (element CELL) structure opposite to the first surface (bottom surface) (see Fig. 5B); and the gate structure (word lines of elements GS, see [0073] “The plurality of gate lines 130 may include the plurality of word lines WL”) is in contact with the first peripheral circuit (element PE1, see [0097] “The others of the plurality of gate lines 130 may be connected to at least one or exactly one selected from a plurality of lower circuits CT1, which are included in a first peripheral circuit region PE1, through the conductive pad region 112 and the second contact structure CTS2”) through a third contact structure (see for example Fig. 5B element CML and CTS2 connects to element PE1)(see [0104-0105] The row decoder element 32 in Fig. 1 can be separated into both element PE1 and PE2 regions but are in electrical communication, see Fig. 5B illustrates at least one element TR1 and one element TR2 connected).
The second peripheral circuit and connections with the gate structure as taught by K1 is incorporated as a second peripheral circuit and connections with the gate structure of L1.
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of K1 with L1 because the combination allows for separation of high voltage and low voltage transistors (see K1 [0045]); and the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known number of peripheral circuitry and connections for another in a similar memory device to obtain predictable results (see K1 Fig. 5B).
14. Regarding Claim 22, L1, K1 disclose the memory device of claim 21, further comprising:
a second contact structure (see K1 Fig. 5B vertical contact structure between element TR2 and TR1 including element 164) extending through the memory array structure and in contact with the first peripheral circuit and the second peripheral circuit (see K1 Fig. 5B the memory array structure is corresponded with the entire height of element MCA across the substrate).
15. Regarding Claim 23, L1, K1 disclose the memory device of claim 22, further comprising:
a first bonding interface disposed between the memory array structure and the first peripheral circuit (see L1 Fig. 9 dotted line bonding interface – note, the manner in which the claim is currently recited does not require a particular material for the bonding interface); and
a second bonding interface disposed between the memory array structure and the second peripheral circuit (see L1 Fig. 9 dotted line bonding interface and K1 boundary between element PE2 and CELL – note, the manner in which the claim is currently recited does not require a particular material for the bonding interface).
16. Regarding Claim 24, L1, K1 disclose the memory device of claim 23, wherein (see K1 Fig. 5B) the second peripheral circuit comprises a first surface (first lower surface) in contact with the memory array structure through the second bonding interface (see Fig. 5B), and a second surface (second upper surface) comprising a pad structure (element 296, see [0107] “I/O pad 296 … may include a metal”).
17. Regarding Claim 25, L1, K1 disclose the memory device of claim 24, wherein (see L1) the first bonding interface is disposed between the first peripheral circuit and the storage unit (see in particular Fig. 9), and the bit line is disposed between the second bonding interface and the vertical transistor (see Figs. 8-9 the second bonding interface is at a topmost layer of the memory cell, and the bit line element 122 is between the top and the vertical transistor of element 111).
18. Regarding Claim 26, L1, K1 disclose the memory device of claim 24, wherein the bit line is in contact with the first peripheral circuit through the first contact structure (see L1 Fig. 9), and the gate structure is in contact with the first peripheral circuit through a third contact structure (see K1 Fig. 5B element CML and CTS2 connects to element PE1).
19. Regarding Claim 27, L1, K1 disclose the memory device of claim 24, wherein the third contact structure extends in the first direction longer than the storage unit (see K1 Fig. 5 element CML and CTS2 connects to element PE1 extends above and below the memory cell and is combined n the same manner with L1).
20. Regarding Claim 29, L1, K1 disclose the memory device of claim 23, wherein the first bonding interface is disposed between the first peripheral circuit and the bit line (see L1 in particular Figs. 8-9), and the second bonding interface is disposed between the second peripheral circuit and the storage unit (see L1 in particular Figs. 8-9 and K1 Fig. 5B).
Allowable Subject Matter
21. Claims 30-31 are allowed.
Claims 8, 10, 28 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reason for indicating allowable subject matter:
The prior art made of record, either singularly or in combination, does not disclose or suggest at least the claim limitations of:
22. Claim 8, “the first contact structure is longer than the second contact structure in the first direction, and the second contact structure is longer than the third contact structure in the first direction” – as instantly claimed and in combination with the additionally claimed limitations.
23. Claim 10, “a second end of the storage unit is in contact with the first peripheral circuit through a fourth contact structure, and the fourth contact structure extends in the first direction longer than the vertical transistor” – as instantly claimed and in combination with the additionally claimed limitations.
24. Claim 28, “the second contact structure is longer than the first contact structure in the first direction, and the first contact structure is longer than the third contact structure in the first direction” – as instantly claimed and in combination with the additionally claimed limitations.
25. Claim 30, “wherein the bit line is in contact with the first peripheral circuit through a second contact structure, the gate structure is in contact with the first peripheral circuit through a third contact structure, the first contact structure is longer than the second contact structure in the first direction, and the second contact structure is longer than the third contact structure in the first direction” – as instantly claimed and in combination with the additionally claimed limitations.
All claims depending on the current claim incorporate the same allowable subject matter.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SAMUEL PARK whose telephone number is (303)297-4277. The examiner can normally be reached Normal Schedule: M-F Sometime between 6:30 a.m. - 7:00 p.m..
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/SAMUEL PARK/Examiner, Art Unit 2818