DETAILED ACTION
Claims 14-38 are pending.
Claims 29-33, 35, and 38 are withdrawn.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Applicant’s claim for the benefit of a prior-filed application (16/396,680) under 35 U.S.C. 119(e) or under 35 U.S.C. 120, 121, 365(c), or 386(c) is acknowledged.
Per MPEP 609.02(I) and (II)(A)(2), the examiner of a continuing application will consider information which has been considered by the Office in the parent application. Therefore, information considered in parent application 16/396,680 has been considered during examination of the instant application. However, if applicant wants said considered information to be printed on any patent resulting from the instant application, applicant must ensure that said information appears on either an IDS or an 892 in the instant application.
Election/Restrictions
Applicant’s election without traverse of Group I in the reply filed on December 14, 2025, is acknowledged.
Specification
The title of the invention is not sufficiently descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
The disclosure is objected to because of the following informalities:
In paragraph 1, please insert any patent numbers for related applications that have been issued.
In paragraph 9, line 2, delete the space after the hyphen.
Appropriate correction is required.
Claim Objections/Recommendations
Claim 25 includes some redundancy that can be eliminated. The examiner recommends rewording to --The computing machine of claim 21, wherein the first instruction is a 16-bit payload instruction, a 32-bit payload instruction, a 48-bit payload instruction, or a 64-bit payload instruction.--.
Claim 28 is objected to because of the following informalities:
Replace “of” with either --comprising-- or --having--.
Remove the hyphen after “13”.
Claim 34 is objected to because of the following informalities:
In line 3, replace “wherein” with --and--.
In line 3, insert a comma before “or”.
In claim 5, replace “wherein” with --and--.
Claim 36 is objected to because of the following informalities:
Replace “of” with either --comprising-- or --having--.
Remove the hyphen after “29”.
Claim 37 is objected to because of the following informalities:
Replace “of” with either --comprising-- or --having--.
Remove the hyphen after “61”.
Appropriate correction is required.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
Such claim limitations are:
In claim 14, “a shift controller that receives the first immediate operand at a first input” and controls “a shifter circuit”, and “presents a shift control value at a second input to the shifter circuit”. Applicant has only generically shown shift control 1303 in FIG.13. The examiner could not find specific structure in the specification that performs the claimed functions of the shift controller. As such, broadest reasonable interpretation (BRI) is taken and 112(a)/(b) rejections are set forth below. The examiner recommends claiming a shift controller circuit to avoid 112(f) invocation.
In claim 21, “a shift controller that presents a shift control value…”. For similar reasoning, BRI is taken and 112(a)/(b) rejections are set forth below.
In claim 22, “the shift controller generates the shift control value…”. For similar reasoning, BRI is taken and 112(a)/(b) rejections are set forth below.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 14-19 and 21-26 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding claims 14 and 21-22, as described above in the “Claim Interpretation” section, the disclosure does not provide adequate structure for the shift controller to perform the claimed functions. The specification does not demonstrate that applicant has made an invention that achieves the claimed functions because the invention is not described with sufficient detail such that one of ordinary skill in the art can reasonably conclude that the inventor had possession of the claimed invention.
Regarding claim 18, the examiner has been unable to find original support in the parent application for combining first and second immediate operands to generate a first resultant immediate for use by a subsequent instruction (claim 14) and then combining the first resultant immediate with a third immediate of a third instruction. From FIG.11, it appears there is support for combining more than two immediate operands together (the loop formed by steps 1102, 1104, 1106 and 1110). However, the subsequent instruction in applicant’s claim actually executes on the combined first and second immediates, which means the loop goes to step 1108, at which point, the immediate operand register is cleared. Thus, it seems there is no support for a third instruction to then further combine a third immediate with the first and second immediates because the first and second immediates have been used and cleared. If applicant believes that claim 18 is supported, please point the examiner to clear support and provide any necessary explanation. Otherwise, the examiner recommends deleting claim 18.
Claims 15-19 and 22-26 are rejected due to their dependence on a claim lacking adequate written description.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 14-19 and 21-26 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claims 14 and 21-22, the shift controller + function limitations invoke 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. However, as described above, the written description fails to disclose the corresponding structure(s), material(s), or act(s) for performing the entire claimed function(s) and to clearly link the structure(s), material(s), or act(s) to the function(s). Therefore, the claim(s) are indefinite and are rejected under 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph.
Applicant may:
(a) Amend the claim(s) so that the claim limitation(s) will no longer be interpreted as a limitation(s) under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g. claiming this controller as a circuit);
(b) Amend the written description of the specification such that it expressly recites what structure(s), material(s), or act(s) perform the entire claimed function(s), without introducing any new matter (35 U.S.C. 132(a)); or
(c) Amend the written description of the specification such that it clearly links the structure(s), material(s), or act(s) disclosed therein to the function(s) recited in the claim(s), without introducing any new matter (35 U.S.C. 132(a)).
If applicant is of the opinion that the written description of the specification already implicitly or inherently discloses the corresponding structure(s), material(s), or act(s) and clearly links them to the function(s) so that one of ordinary skill in the art would recognize what structure(s), material(s), or act(s) perform the claimed function(s), applicant should clarify the record by either:
(a) Amending the written description of the specification such that it expressly recites the corresponding structure(s), material(s), or act(s) for performing the claimed function(s) and clearly links or associates the structure(s), material(s), or act(s) to the claimed function(s), without introducing any new matter (35 U.S.C. 132(a)); or
(b) Stating on the record what the corresponding structure(s), material(s), or act(s), which are implicitly or inherently set forth in the written description of the specification, perform the claimed function(s). For more information, see 37 CFR 1.75(d) and MPEP §§ 608.01(o) and 2181.
Claim 24 is indefinite because it is unclear what applicant is trying to claim. Specifically, what is meant by “by the instruction decoder” in this context? Applicant appears to be claiming that the decoder operates on the resultant operand. However, it is the examiner’s understanding that some execution circuitry (not the decoder) would operate on the operand, as is known in the art. Please clarify.
Claims 15-19 and 22-26 are rejected due to their dependence on an indefinite claim.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 14-19, 27-28, 34, and 36-37 are rejected under 35 U.S.C. 101 because the claimed invention is directed to non-statutory subject matter. The claims do not fall within at least one of the four categories of patent eligible subject matter because they include no explicit recitation of any hardware component, nor do the claims include any component which must be interpreted solely as hardware. Applicant appears to be defining a machine as a software machine including at least one instruction in claims 14 and 27. While claim 14 recites hardware, this hardware is only passively claimed and is not claimed as part of the machine. Instead, applicant is claiming software and how that software would interact with hardware when ultimately executed, but is not positively claiming the hardware. A claimed machine must include a concrete thing, not software per se (see MPEP 2106.03). As such, applicant’s claims encompass software per se, which does not fall into one of the four statutory categories of invention. The examiner recommends claiming at least one hardware component as part of the machine.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 14-16, 19-20, 27, and 34 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Baum (US 5,095,526).
Referring to claim 14, Baum has taught a computing machine comprising:
a first instruction (column 4, line 65, to column 5, line 21, “second prefix instruction”) comprising at least one first opcode (all instructions include an opcode to indicate an operation to perform) and a first immediate operand presented to a shifter circuit controlled by a shift controller that receives the first immediate operand at a first input (column 4, line 65, to column 5, line 21. The immediate operand of the prefix instruction is sent to a shifting prefix register (which is controlled to shift by some controlling logic (shift controller)),
wherein the shift controller presents a shift control value at a second input to the shifter circuit in response to a subsequent instruction comprising at least one second opcode and a second immediate operand, wherein the shifter circuit generates a shifted value from the first immediate operand in response to the shift control value (column 4, line 65, to column 5, line 21. In response to a subsequent instruction other than a prefix instruction (“an instruction with a prefixable immediate”, which has an opcode and its own immediate), a shift control value would be sent to the shifter to output the prefix register contents. The outputted contents represent a shifted value that includes the first immediate operand and a shifted prior immediate operand (from a first prefix instruction)); and
a first resultant immediate operand is generated by combining the shifted value with the second immediate operand (column 5, lines 15-20), and
wherein, the subsequent instruction is configured to execute upon the first resultant immediate operand (one of ordinary skill in the art understands that the instruction that forms the final immediate executes on that immediate. That is, the prefix instructions merely assist in combining the immediate portions, but the final instruction with a prefixable immediate will form the final immediate and then operate on it in the manner indicated by the opcode).
Referring to claim 15, Baum has taught the computing machine of claim 14, where in the shifted value from the first immediate operand is combined with the second immediate operand using a concatenation operation (column 5, lines 15-20).
Referring to claim 16, Baum has taught the computing machine of claim 14, wherein the subsequent instruction is decoded independent of the first instruction (in the cited portion of Baum, the prefix instructions cause their own actions to occur and are separate instructions from the instruction with a prefixable immediate. Because they are separate instructions, they are decoded independently. All processors include a decoder to decode instructions to determine what to perform).
Referring to claim 19, Baum has taught the computing machine of claim 14, wherein the first instruction is a payload immediate instruction (the second prefix instruction carries an immediate value to be combined with another instruction, i.e., the second prefix’s immediate is a payload).
Referring to claim 20, Baum has taught a computing machine comprising:
at least one instruction decoder that decodes a first instruction comprising at least one first opcode and a first immediate operand, wherein the first instruction is an immediate operand instruction of the computing machine (column 4, line 65, to column 5, line 21. A first or second prefix instruction includes a first immediate operand. Every instruction, including a prefix instruction, must include an opcode to distinguish it from every other instruction and dictate its unique operation to be performed. All processors also include a decoder to decode instructions to determine what operations to perform); and
further, the at least one instruction decoder decodes a subsequent instruction comprising at least one second opcode and a second immediate operand, and wherein the at least one instruction decoder configures the subsequent instruction comprising the at least one second opcode to operate upon a combination of the first immediate operand and the second immediate operand (column 5, lines 15-20. The instruction with a prefixable immediate, when decoded, will combine its second immediate operand with the first immediate operand such that an operation is performed on the combination).
Referring to claim 27, Baum has taught a computing machine comprising:
a first instruction comprising at least one first opcode and a first immediate operand, wherein the first instruction is a payload immediate instruction (column 4, line 65, to column 5, line 21. A prefix instruction is a first payload immediate instruction that carries a first immediate operand. Each instruction includes an opcode to distinguish it from every other instruction and dictate its unique operation to be performed); and
a subsequent second instruction comprising at least one second opcode wherein the second instruction is configured with the at least one second opcode to operate upon the first immediate operand (column 5, lines 15-20. The instruction with a prefixable immediate will combine its second immediate operand with the first immediate operand such that an operation is performed on the combination. Again, an opcode is required to carry out this second instruction’s operation).
Referring to claim 34, Baum has taught the computing machine of claim 27, wherein the payload immediate instruction is decoded along with the second instruction (all instructions are decoded in a processor) wherein the second instruction is a 16-bit instruction (from column 4, line 57, all instructions are 16-bit instructions) (struck through limitations are optional and are not required to be addressed).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 17 and 36-37 are rejected under 35 U.S.C. 103 as being unpatentable over Baum in view of the examiner’s taking of Official Notice.
Referring to claim 17, Baum has taught the computing machine of claim 14, but has not taught wherein the first resultant immediate operand is used in an arithmetic operation or logical operation or a vector operation or a matrix operation. However, Official Notice is taken that at least arithmetic and logical operations that operate on immediate values was well known in the art before applicant’s invention (e.g. add-immediate, or-immediate, etc.). Such allows arithmetic and logic operations to be performed on data encoded directly into the instruction to realize elementary and fundamental mathematical and Boolean operations in a processor without consuming extra register space. As a result, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Baum such that the first resultant immediate operand is used in an arithmetic operation or logical operation or a vector operation or a matrix operation.
Referring to claim 36, Baum has taught the computing machine of claim 27, but has not taught wherein the payload immediate instruction is a 32-bit instruction with the first immediate operand of fewer than 29-bits. Instead, Baum has taught that all instructions are 16-bit instructions (column 4, line 57). However, Official Notice is taken that 32-bit instructions were well known in the art before applicant’s invention. Increasing the size of an instruction allows for one or more of: (1) more instructions in the instruction set (opcode size can be increased), (2) more registers to be addressed (register ID fields can be increased), (3) larger immediate data on which to operate (immediate field size can be increased), etc. As a result, it would have first been obvious to one of ordinary skill in the art before applicant’s invention to modify Baum such that the instructions are 32-bit instructions. While a 32-bit prefix instruction would include an opcode of some size, this size is not disclosed. However, changing the sizes of fields of an instruction amounts to a routine expedient, not a patentable distinction, particularly absent a demonstration by applicant of the criticality of the claimed size. See MPEP 2144.04, including section IV(A). Here, the larger the opcode field, the more instructions that can be part of the instruction set. The larger the immediate field, the larger a combined immediate value could be. As such, as more overall instructions are desired in the instruction set, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Baum such that the opcode of the 32-bit prefix instruction is at least 4 bits, meaning the immediate would be fewer than 29 bits.
Referring to claim 37, Baum has taught the computing machine of claim 27, but has not taught wherein the payload immediate instruction is a 64-bit instruction with the first immediate operand of fewer than 61-bits. Instead, Baum has taught that all instructions are 16-bit instructions (column 4, line 57). However, Official Notice is taken that 64-bit instructions were well known in the art before applicant’s invention. Increasing the size of an instruction allows for one or more of: (1) more instructions in the instruction set (opcode size can be increased), (2) more registers to be addressed (register ID fields can be increased), (3) larger immediate data on which to operate (immediate field size can be increased), etc. As a result, it would have first been obvious to one of ordinary skill in the art before applicant’s invention to modify Baum such that the instructions are 64-bit instructions. While a 64-bit prefix instruction would include an opcode of some size, this size is not disclosed. However, changing the sizes of fields of an instruction amounts to a routine expedient, not a patentable distinction, particularly absent a demonstration by applicant of the criticality of the claimed size. See MPEP 2144.04, including section IV(A). Here, the larger the opcode field, the more instructions that can be part of the instruction set. The larger the immediate field, the larger a combined immediate value could be. As such, as more overall instructions are desired in the instruction set, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Baum such that the opcode of the 64-bit prefix instruction is at least 4 bits, meaning the immediate would be fewer than 61 bits.
Claim 28 is rejected under 35 U.S.C. 103 as being unpatentable over Baum.
Referring to claim 28, Baum has taught the computing machine of claim 27, wherein the payload immediate instruction is a 16-bit instruction (column 4, line 57), but has not taught that the first immediate operand includes fewer than 13-bits. While a prefix instruction would include an opcode of some size, this size and the size of the first immediate is not disclosed. However, changing the sizes of fields of an instruction amounts to a routine expedient, not a patentable distinction, particularly absent a demonstration by applicant of the criticality of the claimed size. See MPEP 2144.04, including section IV(A). Here, the larger the opcode field, the more instructions that can be part of the instruction set. The larger the immediate field, the larger a combined immediate value could be. As such, as more overall instructions are desired in the instruction set, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Baum such that the opcode of the prefix instruction is at least 4 bits, meaning the immediate would be fewer than 13 bits.
Allowable Subject Matter
Claims 18 and 21-26 are objected to as being dependent upon a rejected base claim, but would be allowable over the prior art if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Amending these claims to address other issues may affect allowability.
Conclusion
The following prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
KR20080101104 has taught a first instruction that moves part of an immediate to a concatenation register, and then a second instruction that instructs the system to concatenate the data in the concatenation register with a second part of an immediate and then perform an instruction on the combined result.
Iwasa (US 5,177,701) has taught concatenating immediate portions of two different instructions, and a prior art method of storing an immediate portion in a register, shifting the portion in the register, ORing the shifted result with another immediate portion, and then calculating a result using the OR’s result.
Kwon (US 2017/0315811) has taught performing an operation on concatenated immediate portions in different instructions.
Brown (US 2014/0149722) has taught fusing instructions, which includes combining immediates.
Sheaffer (US 6,732,257) has taught splitting and recombining immediates.
Wishneusky (US 2003/009753) has taught extending an immediate operand field.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to David J. Huisman whose telephone number is 571-272-4168. The examiner can normally be reached on Monday-Friday, 9:00 am-5:30 pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta, can be reached at 571-270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/David J. Huisman/Primary Examiner, Art Unit 2183