DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Applicant’s arguments, see Remarks, filed 12/10/2025, with respect to Drawing objections and the rejection(s) of the claims under 35 USC 112(b), 102(a), and 103 have been fully considered and are persuasive, the amendments made overcome the rejections and objection. Therefore, the rejections and objection has been withdrawn. However, upon further consideration, a new ground(s) of rejection under 35 USC 103 is made incorporating US 10388732 B1 Frougier et al.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 9 and 18 are rejected under 35 U.S.C. 103 as being obvious over US 11107736 B1 Cheng hereafter “Cheng” in view of US 10388732 B1 Frougier et al here after “Frougier”
Claim 9 Cheng teaches a semiconductor structure (figs. 1A-1Q) comprising: a semiconductor substrate (106 fig. 1A, fig. 1B, fig. 1C);
a first field effect transistor (FET) (102N1-4 fig. 1A and 1B) formed on the substrate, the first field effect transistor being an n-type field effect transistor (nFET) [Sufficiently disclosed column 7 line 39 “NFETS”], wherein the nFET has a first threshold voltage (Vt0) (TN1-4 fig. 1L) and a gate of the nFET (112N1-4 fig. 1B) comprises a first work function metal (WFM) (130 within 112N3 fig. 1B) layered with a first interfacial layer (IL) (127 within 112N3 fig. 1B), a first high-k dielectric (HK) (128N3 fig. 1B), and a first dipole material (129N1-4); and
a second field effect transistor (FET) (102P1-4 fig. 1A and 1C) formed on the substrate, the second field effect transistor being a p-type FET (pFET), wherein the pFET has a second threshold voltage (Vt1) (TP1-4 fig. 1M) and a gate of the pFET (112P1-4 fig. 1C) comprises a first work function metal (WFM) (130 within 112P1-4 fig. 1C) layered with a second interfacial layer (127 within 112P1-4 fig. 1B), a second high-k dielectric (128P1-4 fig. 1B), and a second dipole material (129P1-4 fig. 1B);
Cheng does not teach a bottom dielectric isolator, wherein the bottom dielectric isolator separates the substrate from:
the first dipole material of the first FET; and
the second dipole material of the second FET.
Frougier teaches a similar semiconductor structure comprising gates (36 and 38 fig. 11) of a layer stack (comprising at least 36, 38, 44, 24, 30 and 52 fig. 11) wherein a bottom dielectric isolator (18 fig. 11) separates the gate structures from a substrate (14 fig. 11)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the device of Cheng with the device of Frougier such that “a bottom dielectric isolator, wherein the bottom dielectric isolator separates the substrate from: the first dipole material of the first FET; and the second dipole material of the second FET” to electrically isolate the gates (layer stack) from the substrate [Column 3 lines 15-20 Frougier].
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Annotated fig. 1E: highlighting a first dipole material and a second dipole material in the gate structures of Cheng
Claim 18 The semiconductor structure of claim 9, wherein the second dipole material includes titanium [“TiO2” [titanium] is sufficiently disclosed Column 13 lines 27-53 wherein the second dipole material is a doped portion of the HK dielectric layer, illustrated fig. 1E.
Claim 17 is rejected under 35 U.S.C. 103 as being obvious over Cheng and Frougier as shown in claim 9, and in further view of US 20090302370 A1 Guha hereafter “Guha”
Claim 17 Cheng in view of Frougier teaches as shown above the semiconductor structure of claim 9,
Cheng in view of Frougier does not teach wherein the second dipole material includes manganese.
Guha teaches a gate structure fig. 1 and/or fig. 2 that includes a dipole material (106 fig. 1 and/or 206 fig. 2) that includes manganese (Paragraph 0030 MnO2 Table 1), Aluminum ( Paragraph 0030 Table 1 Al2O3 or AlN), or titanium (Paragraph 0030 TiO2 or TiN).
It would have been obvious to one of ordinary skill in the art before the effective filing date to take the second dipole material that Cheng in view of More and Frougier teaches as select manganese as Guha teaches such that “the second dipole material includes manganese” as selection of a known material for its known material properties is prima facie type obviousness [See MPEP 2144.06] In this case it is the Electronegativity and/or Flatband shift of the material [Table 1 and paragraph 0030 Guha].
Claims 1-8, 10-11, and 13-16 are rejected under 35 U.S.C. 103 as being unpatentable over Cheng in view of Frougier, and further in view of US 20220216327 A1 More et al hereafter “More”.
Claim 1 Cheng teaches a semiconductor structure comprising: a semiconductor substrate (106 fig. 1C);
a first p-type field effect transistor (FET) (102P3 fig. 1C) formed on the substrate [sufficiently illustrated fig. 1C], wherein the first pFET has a first threshold voltage (Vt0) (TP3 Fig. 1M) and a gate of the first pFET (112P3 fig. 1C) comprises a first work function metal (WFM) (130 fig. 1C) layered with a first interfacial layer (IL) (127 fig. 1C) and a first high-k dielectric (HK) (128P3 fig. 1) [Note; general composition of the gate to channel structure is further graphed fig. 1E];
a second pFET (102P1 fig. 1C) formed on the substrate, wherein the second pFET has a second threshold voltage (Vt1) (TP1 fig. 1M) and a gate of the second pFET (112P1 fig. 1C) comprises the first WFM [met under broadest reasonable interpretation wherein “the first WFM” interpreted as a collective noun, illustrated fig. 1C] layered with a second IL (127 fig. 1C within 112P1), a second HK (128P1 fig. 1C), and a first dipole material [a first portion of 129P1-129P3 fig. 1C, the Rare-earth metal based dipole layer in the interfacial oxide region, sufficiently disclosed fig. 1E, See annotation below]; and
a third pFET (102P2 fig. 1C) formed on the substrate, wherein the third pFET has a third threshold voltage (Vt2) (TP2 Fig. 1M) and a gate of the third pFET (112P2 fig. 1C) comprises the first WFM layered [met under broadest reasonable interpretation wherein “the first WFM” interpreted as a collective, illustrated fig. 1C] with a third IL (127 within 11P2 fig. 1C), a third HK (128P2 fig. 1C), the first dipole material [sufficiently illustrated fig. 1C and 1E] , and a second dipole material [a second portion of 129P1-129P3 fig. 1C, the Rare-earth metal based dipole layer in the High-K dielectric region, sufficiently disclosed fig. 1E, See annotation below];
|Vt0|<|Vt2|<|Vt1| [Sufficiently illustrated fig. 1M, |TP3|<|TP2|<|TP1|].
Cheng does not teach the first pFET does not include the first dipole material and does not include the second dipole material, and the second pFET does not include the second dipole material nor a bottom dielectric isolator, wherein the bottom dielectric isolator separates the substrate from:
the first HK of the first pFET;
the first dipole material of the second pFET; and
the second dipole material of the third pFET,
More teaches a dipole gate structure (Fig. 12A) comprising a WFM layer (1131A fig. 12A), an interfacial layer (307 fig. 12A), a HK layer (309 fig. 12A), a first dipole material (“doped top portion” [of the interfacial layer] 307B fig. 12A, Sufficiently disclosed Paragraph 0015 “A dopant source layer can be formed on the diffusion barrier layer to dope a portion of the high-k dielectric layer and the interfacial layer, form various intermixed layers, and form dopant dipoles at the interface of the high-k dielectric layer and the interfacial layer”), a second dipole material (“doped bottom portion” [of the high-k dielectric layer] 309A fig. 12A, Similarly disclosed in paragraph 0015); A threshold voltage (Vt Paragraph 0056) is a result effected variable of a thickness of the first dipole material (307Bt fig. 12A), and a thickness of the second dipole material (309At fig. 12A) [Sufficiently disclosed Paragraph 0056]; Dipole material maybe omitted [Sufficiently disclosed paragraph 0055 “High-k dielectric layer 309 may not include portions doped with the dopant and may not include an intermixing layer”].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modified the device Cheng teaches in view of the first dipole material and second dipole material More teaches such that “the first nFET does not include the first dipole material and does not include the second dipole material, and the second nFET does not include the second dipole material” as part of routine optimization of threshold voltage of the first nFet and the second nFet [by reducing the thickness to zero such that the element is omitted, See MPEP 2144.05 II. A] and/or Omission of an element and its function is obvious if the function of the element is not desired, in this case, the function is shifting the threshold voltage as evidenced by both Cheng [Fig. 1E-1Q] and More [Paragraph 0055-0057] [See MPEP 2144.04 II. A]
Frougier teaches a similar semiconductor structure comprising gates (36 and 38 fig. 11) of a layer stack (comprising at least 36, 38, 44, 24, 30 and 52 fig. 11) wherein a bottom dielectric isolator (18 fig. 11) separates the gate structures from a substrate (14 fig. 11)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the device of Cheng in view of More with the device of Frougier such that “a bottom dielectric isolator, wherein the bottom dielectric isolator separates the substrate from: the first dipole material of the first FET; and the second dipole material of the second FET” to electrically isolate the gates (layer stack) from the substrate [Column 3 lines 15-20 Frougier]
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Annotated fig. 1E: highlighting a first dipole material and a second dipole material in the gate structures of Cheng
Claim 2 Cheng in view of More Frougier teaches as shown above the semiconductor structure of claim 1, further comprising:
a fourth pFET (102P4 fig. 1C) formed on the substrate, wherein the fourth pFET has a threshold voltage Vt3 (TP4 fig. 1M) and a gate of the fourth pFET (112P4 fig. 1C) comprises the first WFM layered with a fourth IL (127 within 112P4 fig. 1C) and a fourth HK (128P4 fig. 1C), wherein |Vt3|<|Vt0| (sufficiently illustrated fig. 1M).
Cheng does not teach the fourth pFET has only the second dipole material between the fourth IL and the fourth HK and inside the fourth IL and the fourth HK.
As shown for claim 1 it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Cheng in view of More by omitting the first dipole material within the fourth pFET such that “the fourth pFET has only the second dipole material between the fourth IL and the fourth HK and inside the fourth IL and the fourth HK” as part of routine optimization of threshold voltage of the fourth pFET [by reducing the thickness to zero such that the element is omitted, See MPEP 2144.05 II. A] and/or Omission of an element and its function is obvious if the function of the element is not desired, in this case, the function is shifting the threshold voltage as evidenced by both Cheng [Fig. 1E-1Q] and More [Paragraph 0055-0057] [See MPEP 2144.04 II. A].
Claim 3 Cheng in view of More and Frougier teaches as shown above the semiconductor structure of claim 1, wherein:
the first dipole material is present in the second IL and the second HK on the second pFET and in the third IL and the third HR on the third pFET [Sufficiently illustrated between fig. 1C and fig. 1E of Cheng].
Claim 4 Cheng in view of More and Frougier teaches as shown above the semiconductor structure of claim 3, wherein:
the second dipole material is present in the third IL and the third HK on the third pFET [Sufficiently illustrated between fig. 1C and fig. 1E of Cheng].
Claim 5 Cheng in view of More and Frougier teaches as shown above the semiconductor structure of claim 1, wherein the first dipole material shifts threshold voltage toward a conduction band of a semiconductor [This functional limitation is met under MPEP 2112.01 as the structure and/or composition is the same as claimed and/or disclosed].
Claim 6 Cheng in view of More and Frougier teaches as shown above the semiconductor structure of claim 5, wherein the first dipole material comprises a material selected from a list consisting of: lanthanum, yttrium, magnesium, gadolinium. [embodiments of “Lanthanum”, “Gadolinium”, “yttrium”, and/or “magnesium” is sufficiently disclosed column line 49-67 wherein the first dipole material is a doped portion of the interfacial layer, illustrated fig. 1E]
Claim 7 Cheng in view of More and Frougier teaches as shown above the semiconductor structure of claim 1, wherein the second dipole material shifts threshold voltage toward a valence band of a semiconductor [This functional limitation is met under MPEP 2112.01 as the structure and/or composition is the same as claimed and/or disclosed].
Claim 8 Cheng in view of More and Frougier teaches as shown above the semiconductor structure of claim 7, wherein the second dipole material comprises a material selected from a list consisting of: aluminum, manganese, titanium [embodiments of “Al” [aluminum], and/or “TiO2” [titanium] is sufficiently disclosed Column 13 lines 27-53 wherein the second dipole material is a doped portion of the HK dielectric layer, illustrated fig. 1E].
Claim 10 Cheng in view of More and Frougier teaches as shown above the semiconductor structure of claim 1, wherein the bottom dielectric isolator further
separates the substrate from a source and drain of the first pFET, the second pFET, and the third pFET [met in view of the modification made in view of Frougier as made above, Frougier Fig. 11 illustrates the bottom dielectric isolator (18) further separating the source/drain regions (52) from the substrate (14) ].
Claim 11 Cheng in view of More and Frougier teaches as shown above the semiconductor structure of claim 1, wherein the second dipole of the third pFET is located between the bottom dielectric isolator and the first dipole of the third pFET [this limitation is met under broadest reasonable interpretation, illustrated in Cheng fig 1C each portion of the gates between adjacent channel layers is radial symmetric further annotated fig. 1E (Cheng) shown above illustrates this structure relative to the channel In view of the modification of Frougier the resulting structure forms a stack in the relative order of 1. Substrate, 2. Bottom dielectric isolator, 3. Channel 4. first dipole material 5. Second dipole material 6. Gate electrode/work function (gate center). 7. Second dipole material 8. First dipole material 9. Channel. As shown in this order 1. Substrate… 7. Second dipole material 8. First dipole material, the limitation is met when considering the gate structure above gate radial center and below the channel. The examiner further notes that a similar type of radial symmetry is illustrated in fig. 2 of the instant application, however reversed, positioned below gate radial center above a channel. If this limitation were amended to clarify the difference between the structural position and the materials between the first dipole material and the second dipole material within the third PFET (perhaps relative to the WFM and IL) along with a persuasive argument regarding why this particular arrangement is critical may overcome prior art of record].
Claim 13 Cheng in view of More and Frougier the semiconductor structure of claim 1, wherein the second dipole material includes titanium [embodiments “TiO2” [titanium] is sufficiently disclosed Column 13 lines 27-53 wherein the second dipole material is a doped portion of the HK dielectric layer, illustrated fig. 1E]).
Claim 14 Cheng in view of More and Frougier teaches as shown above the semiconductor structure of claim 1, further comprising an oxide layer (comprising 114 and 340 illustrated fig. 1C, 340 is labeled fig. 3B, an embodiment of silicon oxide is disclosed in Column 10 lines 42-55 ), wherein the oxide layer caps fins of the first pFET, the second pFET, and the third pFET [sufficiently illustrated fig. 1E], the oxide layer located adjacent to:
the HK of the first pFET [sufficiently illustrated fig. 1E];
the first dipole material of the second pFET [sufficiently illustrated fig. 1E]; and
the second dipole material of the third pFET [sufficiently illustrated fig. 1E].
Claim 15 Cheng in view of More and Frougier teaches as shown above the semiconductor structure of claim 2, wherein the bottom dielectric isolator separates the substrate from the second dipole material of the fourth pFET [met in view of the modification of Frougier and/or for the same reasons to electrically isolate the substrate from the layered structure].
Claim 16 Cheng in view of More and Frougier teaches as shown above the semiconductor structure of claim 2, further comprising an oxide layer (114 and 340 illustrated fig. 1C, 340 is labeled fig. 3B, an embodiment of silicon oxide is disclosed in Column 10 lines 42-55 ), wherein the oxide layer caps fins of the first pFET, the second pFET, the third pFET, and the fourth pFET [illustrated fig. 1C], the oxide layer located adjacent to:
the HK of the first pFET [illustrated fig. 1C];
the first dipole material of the second pFET [illustrated fig. 1C];
the second dipole material of the third pFET [illustrated fig. 1C]; and
the second dipole material of the fourth pFET [illustrated fig. 1C].
Claims 12 is rejected under 35 U.S.C. 103 as being unpatentable over Cheng in view of Frougier and More as shown in the claims above and in further view of Guha.
Claim 12 Cheng in view of More and Frougier The semiconductor structure of claim 1,
the second dipole material includes Titanium or Aluminum [sufficiently disclosed Column 13 lines 27- 53]
Does not teach wherein the second dipole material includes manganese.
Guha teaches a gate structure fig. 1 and/or fig. 2 that includes a dipole material (106 fig. 1 and/or 206 fig. 2) that includes manganese (Paragraph 0030 MnO2 Table 1), Aluminum ( Paragraph 0030 Table 1 Al2O3 or AlN), or titanium (Paragraph 0030 TiO2 or TiN).
It would have been obvious to one of ordinary skill in the art before the effective filing date to take the second dipole material that Cheng in view of More and Frougier teaches as select manganese as Guha teaches such that “the second dipole material includes manganese” as selection of a known material for its known material properties is prima facie type obviousness [See MPEP 2144.06] In this case it is the Electronegativity and/or Flatband shift of the material [Table 1 and paragraph 0030 Guha].
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/WCT/Examiner, Art Unit 2893
/Britt Hanley/Supervisory Patent Examiner, Art Unit 2893