Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election of claims 1 – 16 without traverse, in the reply filed on 2/17/2026 is acknowledged.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 – 9, 14 – 16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yeh (Pat. No. 9412752 B1), hereinafter Yeh.
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Regarding Independent Claim 1, Yeh teaches a semiconductor device comprising:
a cell region including:
a channel structure ( Yeh, FIG. 1, 80a, 80b; FIG. 10, 1140; column 3, line 25, vertical channel films 80a/80b; column 8, line 34, thin layer 1140 contacts tunneling layer 1132 at least in the regions in which memory cells are being formed ) penetrating through word lines ( Yeh, FIG. 3, 58, 59; FIG. 15, WL; column 4, line 7, word lines 58 and 59; column 7, line 20, conductive strips (WLs) ), and
memory cells ( Yeh, FIG. 3, 70, 71; column 4, line 36, memory cells 70, 71 ) connected to the word lines ( Yeh, FIG. 3, 58, 59; FIG. 15, WL ) and arranged in three dimensions;
a cell contact region in which a cell contact plug ( Yeh, column 17, line 43, the same or additional patterned conductor layers can include conductors coupled to the SSL strips, to the GSL strips and to the word line pads ) connected to a word line ( Yeh, FIG. 3, 58, 59; FIG. 15, WL ) of the cell region is disposed;
a common source line contact region in which a common source line contact plug ( Yeh, FIG. 14, 2020, 2024; column 10, line 6, FIG. 14 illustrates the structure of a following stage after formation of an array of interlayer connectors (2020, 2021, 2022, 2023, 2024, 2025, 2026, 2027) through an interlayer dielectric (not shown), landing on corresponding portions of the thin film semiconductor layer; column 10, line 19, Interlayer connectors 2020 and 2024 provide for electrical connection to portions 2070 and 2071 which are continuous with thin-channel films on the GSL sides of the active pillars; column 4, line 65, ground select line (GSL); column 10, line 30, Reference line 2034 makes electrical contact with interlayer connector 2024 … is connected to the vertical channel films on the GSL sides of NAND strings. As such, reference line 2034 acts as a local common source line and provides connection to a global common source line ) is disposed;
an input and output contact region in which an input and output contact plug ( Yeh, FIG. 14, 2025, 2026; column 10, line 22, Interlayer connectors 2021, 2022, 2023, 2025, 2026, and 2027 provide for electrical connection to portions 2073, 2074, 2075, 2077, 2078, and 2079, respectively, which are portions on the SSL side of the active pillars; column 10, line 43, The inter-level connectors are connected to the vertical channel films on the SSL sides of NAND strings and provide independent connection to the bit lines ) connected to a circuit of the semiconductor device is disposed;
a word line cut region ( Yeh, FIG. 12, 2000, 2001, 2002; column 9, line 11, FIG. 12 illustrates a stage in the process after applying a pillar cut etch which includes etching holes between the stacks through the thin film semiconductor layers to form a plurality of insulating structures (2000, 2001, 2002, 2003, 2004, 2005) ) separating the word lines of the cell region from word lines of a neighboring cell region;
a common source line layer ( Yeh, FIG. 15, 2030, 2034; column 3, line 27, reference lines 2030, 2034 ) connecting the channel structure ( Yeh, FIG. 1, 80a, 80b; FIG. 10, 1140 ) of the cell region and the common source line contact plug ( Yeh, FIG. 14, 2020, 2024 ); and
an input and output pad ( Yeh, FIG. 15, 2031, 2032, 2035, 2036; column 5, line 4, inter-level connector (e.g. 2035, 2036); column 10, line 28, inter-level connectors (e.g. 2031, 2032, 2033, 2035, 2036, and 2037) ) as an external pad of the semiconductor device connected to the input and output contact plug ( Yeh, FIG. 14, FIG. 15, 2025, 2026 ),
wherein the common source line layer ( Yeh, FIG. 15, reference lines 2030, 2034 ) and the input and output pad ( Yeh, FIG. 15, inter-level connector 2031, 2032, 2035, 2036 ) are disposed at the same vertical level ( Yeh, column 2, line 6, The reference line and the inter-level connector are in the first level of patterned conductors ), and
wherein each of the common source line layer ( Yeh, FIG. 15, reference lines 2030, 2034 ) and the input and output pad ( Yeh, FIG. 15, inter-level connector 2031, 2032, 2035, 2036 ) includes the same material ( Yeh, column 10, line 47, The reference lines and the inter-level connectors can comprise tungsten or other conductive materials such as copper, cobalt silicide, tungsten silicide, other metal materials or combinations thereof, and are formed in the same level ).
Regarding Claim 2, Yeh teaches the semiconductor device as claimed in claim 1, on which this claim is dependent, Yeh further teaches: further comprising:
an isolated pad ( Yeh, FIG. 15, 2031, 2032, 2033, 2035, 2036, 2037; column 10, line 28, inter-level connectors (e.g. 2031, 2032, 2033, 2035, 2036, and 2037) ) disposed in the cell contact region and connected to the cell contact plug ( Yeh, column 17, line 43, the same or additional patterned conductor layers can include conductors coupled to the SSL strips, to the GSL strips and to the word line pads ),
wherein the isolated pad ( Yeh, FIG. 15, 2031, 2032, 2033, 2035, 2036, 2037 ) is disposed at the same vertical level ( Yeh, column 2, line 6, The reference line and the inter-level connector are in the first level of patterned conductors ) as the common source line layer ( Yeh, FIG. 15, reference lines 2030, 2034 ), and
wherein each of the isolated pad ( Yeh, FIG. 15, 2031, 2032, 2033, 2035, 2036, 2037 ) and the common source line layer ( Yeh, FIG. 15, reference lines 2030, 2034 ) includes the same material ( Yeh, column 10, line 47, The reference lines and the inter-level connectors can comprise tungsten or other conductive materials ).
Regarding Claim 3, Yeh teaches the semiconductor device as claimed in claim 2, on which this claim is dependent, Yeh further teaches:
wherein the common source line layer ( Yeh, FIG. 15, reference lines 2030, 2034 ) includes a metal ( Yeh, column 10, line 47, The reference lines and the inter-level connectors can comprise tungsten or other conductive materials ) as a major component.
Regarding Claim 4, Yeh teaches the semiconductor device as claimed in claim 2, on which this claim is dependent, Yeh further teaches:
wherein the common source line layer ( Yeh, FIG. 15, reference lines 2030, 2034 ) is disposed across the cell region, the common source line contact region ( Yeh, FIG. 14, 2020, 2024 ), and the word line cut region ( Yeh, FIG. 12, 2000, 2001, 2002 ), and is integrally formed ( Yeh, FIG. 17A, 2024, 2300; FIG. 17B, 2024, 2034 ).
Regarding Claim 5, Yeh teaches the semiconductor device as claimed in claim 4, on which this claim is dependent, Yeh further teaches:
wherein the isolated pad ( Yeh, FIG. 15, 2031, 2032, 2033, 2035, 2036, 2037 ) is surrounded by the common source line layer ( Yeh, FIG. 15, reference lines 2030, 2034 ).
Regarding Claim 6, Yeh teaches the semiconductor device as claimed in claim 2, on which this claim is dependent, Yeh further teaches:
wherein the common source line layer ( Yeh, FIG. 15, reference lines 2030, 2034; FIG. 17A, 2300; FIG. 17B, 2034 ), the input and output pad, and the isolated pad ( Yeh, FIG. 15, 2031, 2032, 2033, 2035, 2036, 2037 ) are embedded in an insulation layer ( Yeh, column 11, line 43, The process can include formation of a layer of interlayer dielectric such as silicon oxide or silicon nitride (not shown) on top of the interlayer connectors, followed by formation of the trenches, corresponding to rectangular regions 2300; column 10, line 6, after formation of an array of interlayer connectors (2020, 2021, 2022, 2023, 2024, 2025, 2026, 2027) through an interlayer dielectric (not shown) … The process can include formation of a layer of interlayer dielectric such as silicon oxide ).
Regarding Claim 7, Yeh teaches the semiconductor device as claimed in claim 6, on which this claim is dependent, Yeh further teaches:
wherein the insulation layer ( Yeh, column 11, line 43, The process can include formation of a layer of interlayer dielectric such as silicon oxide or silicon nitride (not shown) on top of the interlayer connectors, followed by formation of the trenches, corresponding to rectangular regions 2300 ) includes an upper layer ( Yeh, FIG. 18B, second insulating film 2112 ) and a lower layer ( Yeh, FIG. 18B, first insulting film 2111 ) formed of the same material as or a different ( Yeh, column 12, line 41, For example, first insulting film 2111 comprises silicon oxide, and second insulting film 2112 comprises silicon nitride ) material from the upper layer.
Regarding Claim 8, Yeh teaches the semiconductor device as claimed in claim 7, on which this claim is dependent, Yeh further teaches:
wherein the lower layer ( Yeh, FIG. 18B, first insulting film 2111 ) of the insulation layer is made of a silicon oxide ( Yeh, column 12, line 41, For example, first insulting film 2111 comprises silicon oxide ).
Regarding Claim 9, Yeh teaches the semiconductor device as claimed in claim 7, on which this claim is dependent, Yeh further teaches:
wherein the upper layer ( Yeh, FIG. 18B, second insulating film 2112 ) and the lower layer ( Yeh, FIG. 18B, first insulting film 2111 ) of the insulation layer have different cross-sectional shapes ( Yeh, FIG. 23A, FIG. 23B, 2111, 2112; column 14, line 1, In yet another example, where the opening regions (e.g. 2410 shown in FIG. 18A) in the mask used to pattern the second insulting film 2112 have a square shape, the extension can have two straight sides aligned with the bit line and two straight sides aligned with the second insulating film ).
Regarding Claim 14, Yeh teaches the semiconductor device as claimed in claim 1, on which this claim is dependent, Yeh further teaches:
wherein the common source line layer ( Yeh, FIG. 15, reference lines 2030, 2034 ) includes a metal ( Yeh, column 10, line 47, The reference lines and the inter-level connectors can comprise tungsten or other conductive materials ) as a major component.
Regarding Claim 15, Yeh teaches the semiconductor device as claimed in claim 1, on which this claim is dependent, Yeh further teaches:
wherein the common source line layer ( Yeh, FIG. 15, reference lines 2030, 2034 ) is disposed across the cell region, the common source line contact region ( Yeh, FIG. 14, 2020, 2024 ), and the word line cut region ( Yeh, FIG. 12, 2000, 2001, 2002 ), and is integrally formed ( Yeh, FIG. 17A, 2024, 2300; FIG. 17B, 2024, 2034 ).
Regarding Claim 16, Yeh teaches the semiconductor device as claimed in claim 1, on which this claim is dependent, Yeh further teaches: wherein:
the common source line layer ( Yeh, FIG. 15, reference lines 2030, 2034; FIG. 17A, 2300; FIG. 17B, 2034 ) and the input and output pad ( Yeh, FIG. 15, 2031, 2032, 2033, 2035, 2036, 2037 ) are embedded in an insulation layer ( Yeh, column 11, line 43, The process can include formation of a layer of interlayer dielectric such as silicon oxide or silicon nitride (not shown) on top of the interlayer connectors, followed by formation of the trenches, corresponding to rectangular regions 2300; column 10, line 6, after formation of an array of interlayer connectors (2020, 2021, 2022, 2023, 2024, 2025, 2026, 2027) through an interlayer dielectric (not shown) … The process can include formation of a layer of interlayer dielectric such as silicon oxide ), and
the insulation layer ( Yeh, column 11, line 43, The process can include formation of a layer of interlayer dielectric such as silicon oxide or silicon nitride (not shown) on top of the interlayer connectors, followed by formation of the trenches, corresponding to rectangular regions 2300 ) includes an upper layer ( Yeh, FIG. 18B, second insulating film 2112 ) and a lower layer ( Yeh, FIG. 18B, first insulting film 2111 ) formed of the same material as or a different ( Yeh, column 12, line 41, For example, first insulting film 2111 comprises silicon oxide, and second insulting film 2112 comprises silicon nitride ) material from the upper layer.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 10 – 13 are rejected under 35 U.S.C. 103 as being unpatentable over Yeh, in view of Stephens (Pub. No. 20190214298 A1), hereinafter Stephens.
Regarding Claim 10, Yeh teaches the semiconductor device as claimed in claim 9, on which this claim is dependent, Yeh further teaches: wherein:
each of the common source line layer ( Yeh, FIG. 15, reference lines 2030, 2034 ), the isolated pad ( Yeh, FIG. 15, 2031, 2032, 2033, 2035, 2036, 2037 ), and the input and output pad ( Yeh, FIG. 15, inter-level connector 2031, 2032, 2035, 2036 ) includes a first portion ( Yeh, FIG. 15, interlayer connectors 2020/2024 ) contacting the channel structure ( Yeh, FIG. 1, 80a, 80b; FIG. 10, 1140 ), the common source line contact plug ( Yeh, FIG. 14, reference lines 2020, 2024 ), the cell contact plug, and the input and output contact plug ( Yeh, FIG. 14, 2025, 2026 ), and a second portion ( Yeh, FIG. 15, Reference line 2030/2034 ) disposed on the first portion ( Yeh, FIG. 15, interlayer connectors 2020/2024 ),
the first portion ( Yeh, FIG. 15, interlayer connectors 2020/2024 ) has a horizontal cross-sectional area where it abuts the channel structure, the common source line contact plug, the cell contact plug, and the input and output contact plug, and as it approaches the second portion ( Yeh, FIG. 15, Reference line 2030/2034 ), and
the second portion ( Yeh, FIG. 15, Reference line 2030/2034 ) has a horizontal cross-sectional area where it abuts the first portion ( Yeh, FIG. 15, interlayer connectors 2020/2024 ) and as it goes away from the first portion ( Yeh, FIG. 15, interlayer connectors 2020/2024 ).
Yeh fails to disclose:
the first portion has a horizontal cross-sectional area that is widest at bottom, and that narrows on top,
the second portion has a horizontal cross-sectional area that is widest at bottom, and that narrows on top.
However, Stephens teaches:
the first portion ( Stephens, FIG. 5, contacts 34, 36; [0036], As shown in FIG, 5, the contacts 34, 36 will have re-entrant profiles, e.g., reverse tapered profiles, with the larger dimension in direct contact with the respective gate structures 12a and the source/drain contacts 14a … In addition, the contacts 34, 36 will have a smaller profile at a top portion ) has a horizontal cross-sectional area that is widest at bottom, and that narrows on top,
the second portion ( Stephens, FIG. 5, contacts 34, 36; [0036], As shown in FIG, 5, the contacts 34, 36 will have re-entrant profiles, e.g., reverse tapered profiles, with the larger dimension in direct contact with the respective gate structures 12a and the source/drain contacts 14a … In addition, the contacts 34, 36 will have a smaller profile at a top portion ) has a horizontal cross-sectional area that is widest at bottom, and that narrows on top.
Yeh and Stephens are both considered to be analogous to the claimed invention because they are forming metallization and pattern contact in semiconductor. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Yeh ( FIG. 15, Reference line 2030/2034, interlayer connectors 2020/2024; column 2, line 21, the first level of patterned conductors comprising a reference line, acting as a common line source, over the even stack, and inter-level connectors over the odd stack ), to incorporate the teachings of Stephens ( FIG. 5, contacts 34, 36; [0036], As shown in FIG, 5, the contacts 34, 36 will have re-entrant profiles, e.g., reverse tapered profiles, with the larger dimension in direct contact with the respective gate structures 12a and the source/drain contacts 14a … In addition, the contacts 34, 36 will have a smaller profile at a top portion thereof, which allows for improved scaling of the circuit ), to implement the first portion and the second portion. Doing so would provide extra margin for overlay errors / misalignment, and therefore scaling of the circuit can be improved.
Regarding Claim 11, Yeh teaches the semiconductor device as claimed in claim 9, on which this claim is dependent, Yeh further teaches: wherein:
each of the common source line layer ( Yeh, FIG. 15, reference lines 2030, 2034 ), the isolated pad ( Yeh, FIG. 15, 2031, 2032, 2033, 2035, 2036, 2037 ), and the input and output pad ( Yeh, FIG. 15, inter-level connector 2031, 2032, 2035, 2036 ) includes a first portion ( Yeh, FIG. 15, interlayer connectors 2020/2024 ) contacting the channel structure ( Yeh, FIG. 1, 80a, 80b; FIG. 10, 1140 ), the common source line contact plug ( Yeh, FIG. 14, reference lines 2020, 2024 ), the cell contact plug, and the input and output contact plug ( Yeh, FIG. 14, 2025, 2026 ), and a second portion ( Yeh, FIG. 15, Reference line 2030/2034 ) disposed on the first portion ( Yeh, FIG. 15, interlayer connectors 2020/2024 ),
the first portion ( Yeh, FIG. 15, interlayer connectors 2020/2024 ) has a horizontal cross-sectional area where it abuts the channel structure, the common source line contact plug, the cell contact plug, and the input and output contact plug, and as it approaches the second portion ( Yeh, FIG. 15, Reference line 2030/2034 ), and
the second portion ( Yeh, FIG. 15, Reference line 2030/2034 ) has a horizontal cross-sectional area where it abuts the first portion ( Yeh, FIG. 15, interlayer connectors 2020/2024 ) and as it goes away from the first portion ( Yeh, FIG. 15, interlayer connectors 2020/2024 ).
Yeh fails to disclose:
the first portion has a horizontal cross-sectional area that is widest at bottom, and that narrows on top,
the second portion has a horizontal cross-sectional area that is narrowest at bottom, and that widens on top.
However, Stephens teaches:
the first portion ( Stephens, FIG. 5, contacts 34, 36; [0036], As shown in FIG, 5, the contacts 34, 36 will have re-entrant profiles, e.g., reverse tapered profiles, with the larger dimension in direct contact with the respective gate structures 12a and the source/drain contacts 14a … In addition, the contacts 34, 36 will have a smaller profile at a top portion ) has a horizontal cross-sectional area that is widest at bottom, and that narrows on top,
the second portion ( Stephens, FIG. 9, 46, 48; [0042], The via interconnect structure 46 and upper metal wiring structure 48 can be fabricated using well known processes for those skilled in the art, e.g., dual damascene processes ) has a horizontal cross-sectional area that is narrowest at bottom, and that widens on top.
Yeh and Stephens are both considered to be analogous to the claimed invention because they are forming metallization and pattern contact in semiconductor. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Yeh ( FIG. 15, Reference line 2030/2034, interlayer connectors 2020/2024; column 2, line 21, the first level of patterned conductors comprising a reference line, acting as a common line source, over the even stack, and inter-level connectors over the odd stack ), to incorporate the teachings of Stephens ( FIG. 5, contacts 34, 36; [0036], As shown in FIG, 5, the contacts 34, 36 will have re-entrant profiles, e.g., reverse tapered profiles, with the larger dimension in direct contact with the respective gate structures 12a and the source/drain contacts 14a … In addition, the contacts 34, 36 will have a smaller profile at a top portion thereof, which allows for improved scaling of the circuit ) to implement the first portion, and the teachings of Stephens ( FIG. 9, 46, 48; [0042], The via interconnect structure 46 and upper metal wiring structure 48 can be fabricated using well known processes for those skilled in the art, e.g., dual damascene processes ) to implement the second portion. Doing so would provide extra margin for overlay errors / misalignment, and therefore scaling of the circuit can be improved.
Regarding Claim 12, Yeh teaches the semiconductor device as claimed in claim 2, on which this claim is dependent, Yeh further teaches: wherein:
each of the common source line layer ( Yeh, FIG. 15, reference lines 2030, 2034 ), the isolated pad ( Yeh, FIG. 15, 2031, 2032, 2033, 2035, 2036, 2037 ), and the input and output pad ( Yeh, FIG. 15, inter-level connector 2031, 2032, 2035, 2036 ) includes a first portion ( Yeh, FIG. 15, interlayer connectors 2020/2024 ) contacting the channel structure ( Yeh, FIG. 1, 80a, 80b; FIG. 10, 1140 ), the common source line contact plug ( Yeh, FIG. 14, reference lines 2020, 2024 ), the cell contact plug, and the input and output contact plug ( Yeh, FIG. 14, 2025, 2026 ), and a second portion ( Yeh, FIG. 15, Reference line 2030/2034 ) disposed on the first portion ( Yeh, FIG. 15, interlayer connectors 2020/2024 ),
the first portion ( Yeh, FIG. 15, interlayer connectors 2020/2024 ) has a horizontal cross-sectional area where it abuts the channel structure, the common source line contact plug, the cell contact plug, and the input and output contact plug, and as it approaches the second portion ( Yeh, FIG. 15, Reference line 2030/2034 ), and
the second portion ( Yeh, FIG. 15, Reference line 2030/2034 ) has a horizontal cross-sectional area where it abuts the first portion ( Yeh, FIG. 15, interlayer connectors 2020/2024 ) and as it goes away from the first portion ( Yeh, FIG. 15, interlayer connectors 2020/2024 ).
Yeh fails to disclose:
the first portion has a horizontal cross-sectional area that is widest at bottom, and that narrows on top,
the second portion has a horizontal cross-sectional area that is widest at bottom, and that narrows on top.
However, Stephens teaches:
the first portion ( Stephens, FIG. 5, contacts 34, 36; [0036], As shown in FIG, 5, the contacts 34, 36 will have re-entrant profiles, e.g., reverse tapered profiles, with the larger dimension in direct contact with the respective gate structures 12a and the source/drain contacts 14a … In addition, the contacts 34, 36 will have a smaller profile at a top portion ) has a horizontal cross-sectional area that is widest at bottom, and that narrows on top,
the second portion ( Stephens, FIG. 5, contacts 34, 36; [0036], As shown in FIG, 5, the contacts 34, 36 will have re-entrant profiles, e.g., reverse tapered profiles, with the larger dimension in direct contact with the respective gate structures 12a and the source/drain contacts 14a … In addition, the contacts 34, 36 will have a smaller profile at a top portion ) has a horizontal cross-sectional area that is widest at bottom, and that narrows on top.
Yeh and Stephens are both considered to be analogous to the claimed invention because they are forming metallization and pattern contact in semiconductor. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Yeh ( FIG. 15, Reference line 2030/2034, interlayer connectors 2020/2024; column 2, line 21, the first level of patterned conductors comprising a reference line, acting as a common line source, over the even stack, and inter-level connectors over the odd stack ), to incorporate the teachings of Stephens ( FIG. 5, contacts 34, 36; [0036], As shown in FIG, 5, the contacts 34, 36 will have re-entrant profiles, e.g., reverse tapered profiles, with the larger dimension in direct contact with the respective gate structures 12a and the source/drain contacts 14a … In addition, the contacts 34, 36 will have a smaller profile at a top portion thereof, which allows for improved scaling of the circuit ), to implement the first portion and the second portion. Doing so would provide extra margin for overlay errors / misalignment, and therefore scaling of the circuit can be improved.
Regarding Claim 13, Yeh teaches the semiconductor device as claimed in claim 2, on which this claim is dependent, Yeh further teaches: wherein:
each of the common source line layer ( Yeh, FIG. 15, reference lines 2030, 2034 ), the isolated pad ( Yeh, FIG. 15, 2031, 2032, 2033, 2035, 2036, 2037 ), and the input and output pad ( Yeh, FIG. 15, inter-level connector 2031, 2032, 2035, 2036 ) includes a first portion ( Yeh, FIG. 15, interlayer connectors 2020/2024 ) contacting the channel structure ( Yeh, FIG. 1, 80a, 80b; FIG. 10, 1140 ), the common source line contact plug ( Yeh, FIG. 14, reference lines 2020, 2024 ), the cell contact plug, and the input and output contact plug ( Yeh, FIG. 14, 2025, 2026 ), and a second portion ( Yeh, FIG. 15, Reference line 2030/2034 ) disposed on the first portion ( Yeh, FIG. 15, interlayer connectors 2020/2024 ),
the first portion ( Yeh, FIG. 15, interlayer connectors 2020/2024 ) has a horizontal cross-sectional area where it abuts the channel structure, the common source line contact plug, the cell contact plug, and the input and output contact plug, and as it approaches the second portion ( Yeh, FIG. 15, Reference line 2030/2034 ), and
the second portion ( Yeh, FIG. 15, Reference line 2030/2034 ) has a horizontal cross-sectional area where it abuts the first portion ( Yeh, FIG. 15, interlayer connectors 2020/2024 ) and as it goes away from the first portion ( Yeh, FIG. 15, interlayer connectors 2020/2024 ).
Yeh fails to disclose:
the first portion has a horizontal cross-sectional area that is widest at bottom, and that narrows on top,
the second portion has a horizontal cross-sectional area that is narrowest at bottom, and that widens on top.
However, Stephens teaches:
the first portion ( Stephens, FIG. 5, contacts 34, 36; [0036], As shown in FIG, 5, the contacts 34, 36 will have re-entrant profiles, e.g., reverse tapered profiles, with the larger dimension in direct contact with the respective gate structures 12a and the source/drain contacts 14a … In addition, the contacts 34, 36 will have a smaller profile at a top portion ) has a horizontal cross-sectional area that is widest at bottom, and that narrows on top,
the second portion ( Stephens, FIG. 9, 46, 48; [0042], The via interconnect structure 46 and upper metal wiring structure 48 can be fabricated using well known processes for those skilled in the art, e.g., dual damascene processes ) has a horizontal cross-sectional area that is narrowest at bottom, and that widens on top.
Yeh and Stephens are both considered to be analogous to the claimed invention because they are forming metallization and pattern contact in semiconductor. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Yeh ( FIG. 15, Reference line 2030/2034, interlayer connectors 2020/2024; column 2, line 21, the first level of patterned conductors comprising a reference line, acting as a common line source, over the even stack, and inter-level connectors over the odd stack ), to incorporate the teachings of Stephens ( FIG. 5, contacts 34, 36; [0036], As shown in FIG, 5, the contacts 34, 36 will have re-entrant profiles, e.g., reverse tapered profiles, with the larger dimension in direct contact with the respective gate structures 12a and the source/drain contacts 14a … In addition, the contacts 34, 36 will have a smaller profile at a top portion thereof, which allows for improved scaling of the circuit ) to implement the first portion, and the teachings of Stephens ( FIG. 9, 46, 48; [0042], The via interconnect structure 46 and upper metal wiring structure 48 can be fabricated using well known processes for those skilled in the art, e.g., dual damascene processes ) to implement the second portion. Doing so would provide extra margin for overlay errors / misalignment, and therefore scaling of the circuit can be improved.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Da-Wei Lee whose telephone number is (703)756-1792. The examiner can normally be reached M -̶ F 8:00 am -̶ 6:00 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Marlon Fletcher can be reached at 571-272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DA-WEI LEE/Examiner, Art Unit 2817
/MARLON T FLETCHER/Supervisory Primary Examiner, Art Unit 2817
Prosecution Insights