DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application is being examined under the pre-AIA first to invent provisions.
This is a response to the amendment filed 11/3/2025. Claims 2-4 are pending and are under examination.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of pre-AIA 35 U.S.C. 103(a) which forms the basis for all obviousness rejections set forth in this Office action:
(a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-4 is/are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Lee et al. (US2003/0189542) in view of Umezaki et al. (US 2008/0079685) and Liu et al. (US 2009/0051639).
Regarding claim 2, Lee et al.’s figure 2 shows a pixel area comprising a first pixel (connected to OUT2), a second pixel (connected to OUT1), and a third pixel (connected to OUT3); and a driver circuit comprising a first circuit (SRC2), a second circuit (SRC1), and a third circuit (SRC3), wherein the first circuit (figure 3) comprises a first transistor (NT1); a second transistor (NT2); a third transistor (NT6); a fourth transistor (NT3); a fifth transistor (NT12); a sixth transistor (NT10); a seventh transistor (NT14); and an eighth transistor (NT13), wherein the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor have the same conductivity type (N type), wherein one of a source and a drain of the first transistor (NT1) is electrically connected to a first line (CKT) and the other of the source and the drain of the first transistor is electrically connected to a second line (OUT), wherein one of a source and a drain of the second transistor (NT2) is electrically connected to the second line (OUT) and the other of the source and the drain of the second transistor (NT2) is electrically connected to one of a source and a drain of the eighth transistor (NT13), wherein one of a source and a drain of the third transistor (NT6) is electrically connected to a gate of the first transistor (NT1), the other of the source and the drain of the third transistor (NT6) is electrically connected to the third line (VSST), and a gate of the third transistor is electrically connected to a gate of the second transistor (NT2), wherein one of a source and a drain of the fourth transistor (NT3) is electrically connected to the gate of the first transistor (NT1), the other of the source and the drain of the fourth transistor (NT3) is electrically connected to a fourth line (VDDT), and a gate of the fourth transistor (NT3) is electrically connected to a fifth line (IN), wherein one of a source and a drain of the fifth transistor (NT12) is electrically connected to the gate of the first transistor (NT1), the other of the source and the drain of the fifth transistor (NT12) is electrically connected to the third line (VSST), and a gate of the fifth transistor (NT12) is electrically connected to a sixth line (CT), wherein one of a source and a drain of the sixth transistor (NT10) is electrically connected to the gate of the second transistor (NT2), the other of the source and the drain of the sixth transistor (NT10) is electrically connected to the third line (VSST), and a gate of the sixth transistor (NT10) is electrically connected to the gate of the first transistor (NT1), wherein one of a source and a drain of the seventh transistor (NT14) is electrically connected to the first line (CKT), the other of the source and the drain of the seventh transistor (NT14) is electrically connected to a seventh line (CR), and a gate of the seventh transistor (NT14) is electrically connected to the gate of the first transistor (NT1), wherein the other of the source and the drain of the eighth transistor (NT13) is electrically connected to the second line (OUT) and a gate of the eighth transistor (NT13) is electrically connected to the sixth line (CT), the other of the source and the drain of the second transistor ((NT2) and the one of the source and the drain of the eighth transistor (NT13) are configured to be supplied with power supply voltage (claim 3, VSST); wherein the first circuit is configured to output a signal to the first pixel through the second line, and wherein the third circuit is configured to output a signal to the third pixel through the sixth line.
Lee et al.’s does not disclose (1) wherein a ratio of the channel width to the channel length of the fifth transistor is smaller than a ratio of the channel width to the channel length of the fourth transistor; (2) wherein the second circuit is configured to output a signal to the second pixel through the fourth line as called for in claims 2-4.
Regarding the difference noted in item (1), it is a commonly known knowledge in the field of shift register circuit that a transistor with large width to length ratio usually has high current drivability. Thus, it is desirable to have a width to length ratio of one transistor larger than the other transistor in a shift register circuit to ensure a sufficient driving current is obtained. Particularly, one skilled in the art would have been recognized that the current at the node N1 needed to be high enough so that the output transistor (NT1) is properly turned on and the output signal (OUT) is at a desired level in order to prevent erroneous operation (see Umezaki et al. (US 2008/0079685, paragraphs 0199 and 0203; suggests W/L of transistor 105 is ½ of W/L of the transistor 101; W/L of the transistor 107 is 1/20 of W/L of the transistor 101; thus, it is clear that W/L of the transistor 105 is larger than the W/L of the transistor 107 ). Therefore, it would have been obvious to person skilled in the art at the time the invention was made to have Lee et al.’s fourth transistor (NT3) width to length ratio larger than the width to length ratio of all transistors including the fifth transistor (N12) for the purpose of preventing erroneous operation.
Regarding the difference noted in item (2), it is noted that Lee et al.’s fourth transistor (NT3) having a gate electrode receiving an output signal from the second circuit and one of a source and a drain is connected to the power supply VDDT instead of having the one of the source and drain receiving the output signal from the second circuit as noted in item (2). Liu et al.’s figures 10A and 10D discloses a variation of an input transistor (Q1) can be configured in either configuration without altering the circuit operation. Thus, it would have been obvious to person skilled in the art at the time the invention was made to have Lee et al.’s fourth transistor (NT3) reconfigured as Liu et al.’s transistor Q1 having one of a source and drain receiving an output signal from the second circuit element (Liu et al.’s figure 10A; figure 8) as taught by Liu et al. reference.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TUAN THIEU LAM whose telephone number is (571)272-1744. The examiner can normally be reached Monday-Friday, 8:30 am to 5:00 pm.
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/TUAN T LAM/Primary Examiner, Art Unit 2842 1/14/2026