DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Other references: Senior (US 10169246 – compressed memory system); Garcia (US 10216415).
Miller (US 5490260 – computer using fixed sized swap ages with compressed data stored)
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 2/4/2026 has been entered.
Claim Rejections - 35 USC § 103
4. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
5. Claims 1,2,3, 8,9, 10,15,16, 17 are rejected under 35 U.S.C. 103 as being unpatentable over Li (US 20170004069) and in view of Loh (US 20150019813) and further in view of Gruber (US 20170083997)
Claim 1. Li discloses A device (e.g., a computing device 100, 0033 Fig. 1), comprising:
data compression circuitry to compress a first page sized block of data read from a first single page of memory and produce a first block of compressed data from the first page sized block of data (e.g., compression engine 116 of the CE 102 may compress received data for storage onto the main memory 136. compression engine 116 may utilize a pre-defined two-level compression mechanism to compress each page and each cache line within the page and generate a compressed physical page., 0045-0047, Fig. 1, 2); and
circuitry to write the first block of compressed data (e.g., block 704, the data in the at least one page is compressed based on a predefined two-level compression mechanism to generate at least one compressed physical page. , 0093 Fig. 7; a cache line 206 is found to be uncompressible to an extent that it may not be stored into the slot of predefined size, the compression engine 116 may leave such cache line 206 uncompressed. That is, if the cache line 206 is uncompressible or necessitates a larger space than the size of the slot after compression, the compression engine 116 may not compress such cache line 206 and mark it as an uncompressible cache line 206., 0051; data section 302 in chunks of fixed sizes, 0065).
Li does not disclose, but Loh discloses
where the plurality of fixed size regions of the second single page of memory are collectively equal in size to each of the first single page of memory and the second single page of memory (eg., 0031 - compression of data blocks typically results in compressed data blocks of non-uniform sizes, the location of a compressed data block within the row 222 ; 0054 - compressed to generate a compressed data block of a reduced size. This enables the resulting compressed data block to be stored at a variable offset within the row 902,; [0044] In the illustrated example of FIG. 5, a row 502 (corresponding to row 222 of FIG. 2) of the first level memory 106 initially stores four compressed data blocks, denoted "A", "B", "C", and "D"),
each of the plurality of fixed size regions are uniform in size (eg., [0026] the individual segments of data to be compressed before storage in the first level memory 106 are of a fixed or uniform size. This uniform size may correlate to a typical cache line or memory row configuration. the first level memory 106 comprises a DRAM with a 2 kilobyte (KB) row buffer that is divided into thirty-two 64 byte blocks, each uncompressed data segment may be a 64 byte segment. ), and
the two or more fixed size regions of the plurality of fixed size regions of the second single page of memory where the first block of compressed data is to be written are collectively smaller in size than each of the first single page of memory and the second single page of memory (eg., 0020 - the compressed pages typically have non-uniform sizes. Moreover, the compressed pages may not be stored as contiguous blocks within the lower-level memory; 0026 - the resulting compressed data segments may be of different, or non-uniform, sizes.; 0031 - compression of data blocks typically results in compressed data blocks of non-uniform sizes, the location of a compressed data block within the row 222 ).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the compression and decompression of memory pages as disclosed by Li with Loh, providing the benefit of enables the resulting compressed data block to be stored at a variable offset within the row 902, thereby reducing the number of program-erase cycles to any given memory cell within the row 902 over time (see Loh, 0054) employing compression in a memory hierarchy of a processing system so as to reduce memory accesses to higher-level memories, and thereby reduce memory performance bottlenecks and uneven wear of higher-level memories (0018) .
Li in view of Loh does not disclose, but Gruber discloses
to two or more fixed size regions of a plurality of fixed size regions of a second single page of memory (eg., 0004, 0059, 0071 Figs. 3A-3D - storing, by GPU 12, a plurality of bandwidth-compressed graphics data 56 into a respective plurality of blocks 54 in memory 26, wherein each of the plurality of blocks 54 is of a uniform fixed size in the memory 26, and wherein one or more of the plurality of bandwidth-compressed graphics data 56 has a size that is smaller than the fixed size )
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the compression and decompression of memory pages as disclosed by Li with Loh, with Gruber, providing the benefit of stored in uniformly-sized blocks in memory that may accommodate the largest bandwidth-compressed graphics data out of the plurality of bandwidth-compressed graphics data (see Gruber, 0003) perform bandwidth compression of a surface by dividing the surface into sub-regions and compressing each of the sub-regions of the surface to generate a plurality of bandwidth-compressed graphics data (0013).
Claim 2. Li discloses selection circuitry to, based on a number of fixed size regions to be occupied by the first block of compressed data, select the second single page of memory from a plurality of pages of memory allocated to store compressed pages of data (e.g., Any compressed physical page 204 may therefore either be provided with 1, 2, 3, or 4 data blocks of 1 KB from the chunk based on the size of the compressed physical page 204 for storage in the data section 302, 0065).
Claim 3. Li discloses compressed memory access circuitry to, at least in response to an access to an address associated with the first single page of memory, (e.g., receive a request to read data from a main memory 106, where the request may include a shadow address corresponding to location of storage of the data. , 0088 Fig. 6)
read the one or more fixed size regions of the second single page of memory to produce a second block of compressed data (e.g., write data to the storage devices, the decompression engine 118 of the CE 102 may either decompress the compressed physical page 204 to generate a corresponding page 202 and provide it to the storage device or may provide the compressed physical page to the storage device to save bandwidth during the transfer. In examples when the decompression engine 118 provides the compressed physical page 204 to the storage device, the compressed physical page 204 may be decompressed after transfer and prior to storage on the storage device., 0081).
Li does not disclose, but Loh discloses
two or more fixed size regions of the plurality of fixed size regions of the second single page of memory (eg., [0043] FIGS. 4 and 5 illustrate example operations of the shuffle/compact logic 210 in accordance with some embodiments. In the example illustrated in FIG. 4, a row 402 (of the first level memory 106 initially stores four compressed data blocks, denoted "A", "B", "C", and "D", with unused spaces 411, 412, 413, and 414 interspersed in between. Subsequently, a new compressed data block, denoted "E", is received for storage in the row 402.. ).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the compression and decompression of memory pages as disclosed by Li with Loh, providing the benefit of enables the resulting compressed data block to be stored at a variable offset within the row 902, thereby reducing the number of program-erase cycles to any given memory cell within the row 902 over time (see Loh, 0054) employing compression in a memory hierarchy of a processing system so as to reduce memory accesses to higher-level memories, and thereby reduce memory performance bottlenecks and uneven wear of higher-level memories (0018) .
Claim 8. Li discloses A device (e.g., a computing device 100, 0033 Fig. 1), comprising:
data compression circuitry to compress page sized blocks of and produce blocks of compressed data from the page sized blocks of data (e.g., compression engine 116 of the CE 102 may compress received data for storage onto the main memory 136. compression engine 116 may utilize a pre-defined two-level compression mechanism to compress each page and each cache line within the page and generate a compressed physical page., 0045-0047, Fig. 1); and
circuitry to write the blocks of compressed data, respectively, (e.g., block 704, the data in the at least one page is compressed based on a predefined two-level compression mechanism to generate at least one compressed physical page. , 0093 Fig. 7; a cache line 206 is found to be uncompressible to an extent that it may not be stored into the slot of predefined size, the compression engine 116 may leave such cache line 206 uncompressed. That is, if the cache line 206 is uncompressible or necessitates a larger space than the size of the slot after compression, the compression engine 116 may not compress such cache line 206 and mark it as an uncompressible cache line 206., 0051; data section 302 in chunks of fixed sizes, 0065).
Li does not disclose, but Loh discloses
where the plurality of fixed size regions of each of the other single pages of memory are collectively equal in size to each of the single pages of memory and each of the other single pages of memory (eg., 0031 - compression of data blocks typically results in compressed data blocks of non-uniform sizes, the location of a compressed data block within the row 222 ; 0054 - compressed to generate a compressed data block of a reduced size. This enables the resulting compressed data block to be stored at a variable offset within the row 902,; [0044] In the illustrated example of FIG. 5, a row 502 (corresponding to row 222 of FIG. 2) of the first level memory 106 initially stores four compressed data blocks, denoted "A", "B", "C", and "D"),
each of the plurality of fixed size regions are uniform in size (eg., [0026] the individual segments of data to be compressed before storage in the first level memory 106 are of a fixed or uniform size. This uniform size may correlate to a typical cache line or memory row configuration. the first level memory 106 comprises a DRAM with a 2 kilobyte (KB) row buffer that is divided into thirty-two 64 byte blocks, each uncompressed data segment may be a 64 byte segment. ), and
each of the two or more fixed size regions of the other single pages of memory where the blocks of compressed data are to be written are collectively smaller in size than each of the single pages of memory and each of the other single pages of memory (eg., 0020 - the compressed pages typically have non-uniform sizes. Moreover, the compressed pages may not be stored as contiguous blocks within the lower-level memory; 0026 - the resulting compressed data segments may be of different, or non-uniform, sizes.; 0031 - compression of data blocks typically results in compressed data blocks of non-uniform sizes, the location of a compressed data block within the row 222 ).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the compression and decompression of memory pages as disclosed by Li with Loh, providing the benefit of enables the resulting compressed data block to be stored at a variable offset within the row 902, thereby reducing the number of program-erase cycles to any given memory cell within the row 902 over time (see Loh, 0054) employing compression in a memory hierarchy of a processing system so as to reduce memory accesses to higher-level memories, and thereby reduce memory performance bottlenecks and uneven wear of higher-level memories (0018) .
Li in view of Loh does not disclose, but Gruber discloses
to two or more fixed size regions of a plurality of fixed size regions of a second single page of memory (eg., 0004, 0059, 0071 Figs. 3A-3D - storing, by GPU 12, a plurality of bandwidth-compressed graphics data 56 into a respective plurality of blocks 54 in memory 26, wherein each of the plurality of blocks 54 is of a uniform fixed size in the memory 26, and wherein one or more of the plurality of bandwidth-compressed graphics data 56 has a size that is smaller than the fixed size )
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the compression and decompression of memory pages as disclosed by Li with Loh, with Gruber, providing the benefit of stored in uniformly-sized blocks in memory that may accommodate the largest bandwidth-compressed graphics data out of the plurality of bandwidth-compressed graphics data (see Gruber, 0003) perform bandwidth compression of a surface by dividing the surface into sub-regions and compressing each of the sub-regions of the surface to generate a plurality of bandwidth-compressed graphics data (0013).
Claim 9 is rejected for reasons similar to Claim 2 above.
Claim 10 is rejected for reasons similar to Claim 3 above.
Claim 15. Li discloses A method (e.g., a computing device 100, 0033 Fig. 1), comprising:
compressing, by a memory buffer device, a first page sized block of to produce a first block of compressed data from the first page sized block of data (e.g., compression engine 116 of the CE 102 may compress received data for storage onto the main memory 136. compression engine 116 may utilize a pre-defined two-level compression mechanism to compress each page and each cache line within the page and generate a compressed physical page., 0045-0047, Fig. 1); and
writing the first block of compressed data to, where the one or more fixed size regions do not consist of an entirety of the second single page of memory and each of the fixed size regions are uniform in size (e.g., block 704, the data in the at least one page is compressed based on a predefined two-level compression mechanism to generate at least one compressed physical page. , 0093 Fig. 7; a cache line 206 is found to be uncompressible to an extent that it may not be stored into the slot of predefined size, the compression engine 116 may leave such cache line 206 uncompressed. That is, if the cache line 206 is uncompressible or necessitates a larger space than the size of the slot after compression, the compression engine 116 may not compress such cache line 206 and mark it as an uncompressible cache line 206., 0051; data section 302 in chunks of fixed sizes, 0065).
Li does not disclose, but Loh discloses
where the plurality of fixed size regions of the second single page of memory are Page collectively equal in size to each of the first single page of memory and the second single page of memory (eg., 0031 - compression of data blocks typically results in compressed data blocks of non-uniform sizes, the location of a compressed data block within the row 222 ; 0054 - compressed to generate a compressed data block of a reduced size. This enables the resulting compressed data block to be stored at a variable offset within the row 902,; [0044] In the illustrated example of FIG. 5, a row 502 (corresponding to row 222 of FIG. 2) of the first level memory 106 initially stores four compressed data blocks, denoted "A", "B", "C", and "D"),
each of the plurality of fixed size regions are uniform in size (eg., [0026] the individual segments of data to be compressed before storage in the first level memory 106 are of a fixed or uniform size. This uniform size may correlate to a typical cache line or memory row configuration. the first level memory 106 comprises a DRAM with a 2 kilobyte (KB) row buffer that is divided into thirty-two 64 byte blocks, each uncompressed data segment may be a 64 byte segment. ), and
the two or more fixed size regions of the plurality of fixed size regions of the second single page of memory where the first block of compressed data is written is collectively smaller in size than each of the first single page of memory and the second single page of memory (eg., 0020 - the compressed pages typically have non-uniform sizes. Moreover, the compressed pages may not be stored as contiguous blocks within the lower-level memory; 0026 - the resulting compressed data segments may be of different, or non-uniform, sizes.; 0031 - compression of data blocks typically results in compressed data blocks of non-uniform sizes, the location of a compressed data block within the row 222 ).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the compression and decompression of memory pages as disclosed by Li with Loh, providing the benefit of enables the resulting compressed data block to be stored at a variable offset within the row 902, thereby reducing the number of program-erase cycles to any given memory cell within the row 902 over time (see Loh, 0054) employing compression in a memory hierarchy of a processing system so as to reduce memory accesses to higher-level memories, and thereby reduce memory performance bottlenecks and uneven wear of higher-level memories (0018) .
Li in view of Loh does not disclose, but Gruber discloses
to two or more fixed size regions of a plurality of fixed size regions of a second single page of memory (eg., 0004, 0059, 0071 Figs. 3A-3D - storing, by GPU 12, a plurality of bandwidth-compressed graphics data 56 into a respective plurality of blocks 54 in memory 26, wherein each of the plurality of blocks 54 is of a uniform fixed size in the memory 26, and wherein one or more of the plurality of bandwidth-compressed graphics data 56 has a size that is smaller than the fixed size )
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the compression and decompression of memory pages as disclosed by Li with Loh, with Gruber, providing the benefit of stored in uniformly-sized blocks in memory that may accommodate the largest bandwidth-compressed graphics data out of the plurality of bandwidth-compressed graphics data (see Gruber, 0003) perform bandwidth compression of a surface by dividing the surface into sub-regions and compressing each of the sub-regions of the surface to generate a plurality of bandwidth-compressed graphics data (0013).
Claim 16 is rejected for reasons similar to Claim 2 above.
Claim 17 is rejected for reasons similar to Claim 3 above.
7. Claims 4-7, 11-14, 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Li (US 20170004069) and in view of Loh (cited above) and Gruber (cited above) and further in view of MacDonald (US 5696927)
Claim 4. Li discloses decompression circuitry to decompress the second block of compressed data and produce a second page sized block of data (e.g., the decompression engine 118 of the CE 102 may either decompress the compressed physical page 204 to generate a corresponding page 202 and provide it to the storage device or may provide the compressed physical page to the storage device to save bandwidth during the transfer. In examples when the decompression engine 118 provides the compressed physical page 204 to the storage device, the compressed physical page 204 may be decompressed after transfer and prior to storage on the storage device., 0081; ; and
Li in view of Loh and Gruber does not disclose, but MacDonald disclosed
circuitry to write the second page sized block of data to a third single page of memory (e.g., compressed page is then decompressed into a physical memory page such as 313 , col 6:33-35).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the compression and decompression of memory pages as disclosed by Li, in view of Loh and Gruber with MacDonald, providing the benefit of compression/decompression engine integrated with a memory paging system (see MacDonald col 1: 7-20).
Claim 5. Li discloses circuitry to maintain a data table structure to associate addresses associated with the first page sized block of data to the one or more fixed size regions (e.g., Since the metadata section directly provides information of the compressed physical pages, the metadata section may be directly mapped to the shadow address space by the CE, while being stored in the main memory and referenced by the physical address space. , 0029; processing engine 124 of the CE 102 may map the shadow pages 306 to the compressed physical pages 204. In one example implementation, the mapping between the shadow pages 306 and the pages stored in the data section 302 may be based on me metadata section 304, 0064).
Li does not disclose, but Loh discloses
two or more fixed size regions (eg., [0043] FIGS. 4 and 5 illustrate example operations of the shuffle/compact logic 210 in accordance with some embodiments. In the example illustrated in FIG. 4, a row 402 (of the first level memory 106 initially stores four compressed data blocks, denoted "A", "B", "C", and "D", with unused spaces 411, 412, 413, and 414 interspersed in between. Subsequently, a new compressed data block, denoted "E", is received for storage in the row 402.. ).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the compression and decompression of memory pages as disclosed by Li with Loh, providing the benefit of enables the resulting compressed data block to be stored at a variable offset within the row 902, thereby reducing the number of program-erase cycles to any given memory cell within the row 902 over time (see Loh, 0054) employing compression in a memory hierarchy of a processing system so as to reduce memory accesses to higher-level memories, and thereby reduce memory performance bottlenecks and uneven wear of higher-level memories (0018) .
Claim 6. Li discloses wherein the first single page of memory may be reallocated for use by a host device (e.g., de-allocate data from the main memory 106. The processing engine 124 may de-allocate the compressed physical page 204 based on a two-step mechanism. First, the processing engine 124 may return the blocks occupied by the compressed physical pages 204 in the data section 302 to the linked list of free blocks. Further, the processing engine 124 may also release a corresponding metadata entry 502 in the metadata section 304 of the main memory 106. It may occur that till the time of de-allocation of the compressed physical page 204 from the data section 302, the data within the page may have changed and correspondingly may have to be written to storage devices associated with the computing device 100., 0080; processors 108 , 0037).
Claim 7. Li discloses wherein the first single page of memory, the second single page of memory, and third single page of memory reside in dynamic random access memory (DRAM).(e.g., main memory may also be implemented as a volatile memory, including, but not limited to, SRAM, DRAM, 0040)
Claim 11 is rejected for reasons similar to Claim 4 above.
Claim 12 is rejected for reasons similar to Claim 5 above.
Claim 13 is rejected for reasons similar to Claim 6 above.
Claim 14 is rejected for reasons similar to Claim 7 above.
Claim 18 is rejected for reasons similar to Claim 4 above.
Claim 19 is rejected for reasons similar to Claim 5 above.
Claim 20 is rejected for reasons similar to Claim 6 above.
Response to Arguments
Applicant's arguments filed 2/4/2026 have been fully considered but they are not persuasive.
For claims 1, 8 and 15, Applicant argues that that the cited references do not disclose the amended limitations. The Office disagrees.
In the present OA, the updated combination of references render the amended limitations as obvious.
Specifically, Li in view of Loh does not disclose, but Gruber discloses
to two or more fixed size regions of a plurality of fixed size regions of a second single page of memory (eg., 0004, 0059, 0071 Figs. 3A-3D - storing, by GPU 12, a plurality of bandwidth-compressed graphics data 56 into a respective plurality of blocks 54 in memory 26, wherein each of the plurality of blocks 54 is of a uniform fixed size in the memory 26, and wherein one or more of the plurality of bandwidth-compressed graphics data 56 has a size that is smaller than the fixed size )
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the compression and decompression of memory pages as disclosed by Li with Loh, with Gruber, providing the benefit of stored in uniformly-sized blocks in memory that may accommodate the largest bandwidth-compressed graphics data out of the plurality of bandwidth-compressed graphics data (see Gruber, 0003) perform bandwidth compression of a surface by dividing the surface into sub-regions and compressing each of the sub-regions of the surface to generate a plurality of bandwidth-compressed graphics data (0013).
Applicant’s arguments for dependent claims are based on their respective base independent claims, which are addressed above.
Conclusion
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/GAUTAM SAIN/Primary Examiner, Art Unit 2135
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