Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Takatsuka (US 20210183930 A1) in view of Fujiwara et al. (EP 3816659 A2) hereafter referred to as Fujiwara
In regard to claim 1 Takatsuka teaches a device [see Fig. 1 see paragraph 0051, see “FIGS. 2A and 2B are schematic views”], comprising:
a single photon avalanche diode [“the pixel 100 including the SPAD of the APD serving as a light detection unit in the structure of the solid-state imaging device according to the first embodiment will be described as an example”] in a portion of a substrate [“In the pixel 100, an n-type semiconductor region 101 and a p-type semiconductor region 102 are formed inside a well layer 103” “p-type semiconductor region 121”] and including:
an anode comprising a first doped region [“p-type semiconductor region 121”] having an upper face [bottom face in Fig. 1] coplanar with an upper face [bottom face in Fig. 1] of the portion;
a cathode comprising a second doped region [“n-type semiconductor region 101 functions as a cathode”] having an upper face coplanar with the upper face [bottom face in Fig. 1] of the portion; and
an insulating trench [“In FIG. 1, separating regions for separating the SPADs of adjacent pixels 100 are provided on both sides of the well layer 103. As the separating regions, groove parts (trenches) are formed between the p-type semiconductor region 121 and the p-type semiconductor region 122, and an insulating film 123 and the light-shielding part 124 are embedded in the groove parts”] located in the first doped region for the anode; and
but does not teach a resistor resting on the insulating trench.
See Fujiwara teaches see Fig. 2, “For example, each photodiode PD functions as an avalanche photodiode” “first conductivity type is one of a p-type or an n-type. The second conductivity type is the other of the p-type or the n-type” “structure body 21 is insulative. The structure body 21 is provided to suppress conduction and optical interference between the semiconductor parts 10” “Each element 1 includes a quenching part. In the example, a quenching resistance 30 is provided as the quenching part. The quenching resistance 30 is electrically connected to the first semiconductor layer 11 of each photodiode PD” “For example, the quenching resistance 30 is arranged with the structure body 21 or the semiconductor region 25 in the Z-direction” “quenching resistance 30 includes polysilicon as a semiconductor material. An n-type impurity or a p-type impurity may be added to the quenching resistance 30”, see Fig. 29 see “In FIGS. 27 to 29, the arrangements of the quenching resistances and the contacts are illustrated” “in FIG. 29, the electrical resistance of the quenching resistance 30a is less than the electrical resistance of the quenching resistance 30b. For example, the length of the quenching resistance 30a is less than the length of the quenching resistance 30a when viewed from the Z-direction”. See that in Fig. 2 see that 30 is on “second insulating layer IL2” which is on “semiconductor region 25”. See that IL2 is shown in a trench as well as on “semiconductor region 25”.
Thus, see that Takatsuka already teaches the ability to embed insulator in the anode 121, see paragraph [0158] it can be partial “partially penetrates” and Fujiwara teaches “the quenching resistance 30 is arranged with the structure body 21 or the semiconductor region 25”.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Takatsuka to include an additional insulator embedded in a trench in anode semiconductor 121 and placing a length of polysilicon resistor on the insulator i.e. to modify Takatsuka to include a resistor resting on the insulating trench.
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation is to quench the SPAD of Takatsuka to prevent excess current flow.
In regard to claim 2 Takatsuka and Fujiwara as combined teaches wherein lateral and lower faces of the insulating trench are covered [see combination Fujiwara] by the first doped region.
In regard to claim 3 Takatsuka and Fujiwara as combined teaches wherein the portion is surrounded [see Takatsuka “In FIG. 1, separating regions for separating the SPADs of adjacent pixels 100 are provided on both sides of the well layer 103. As the separating regions, groove parts (trenches) are formed between the p-type semiconductor region 121 and the p-type semiconductor region 122, and an insulating film 123 and the light-shielding part 124 are embedded in the groove parts” , see “FIGS. 2A and 2B are schematic views”] by an insulating wall.
In regard to claim 4 Takatsuka and Fujiwara as combined teaches wherein the first doped region and the insulating trench have a shape which surrounds [see Takatsuka “In FIG. 1, separating regions for separating the SPADs of adjacent pixels 100 are provided on both sides of the well layer 103. As the separating regions, groove parts (trenches) are formed between the p-type semiconductor region 121 and the p-type semiconductor region 122, and an insulating film 123 and the light-shielding part 124 are embedded in the groove parts” , see “FIGS. 2A and 2B are schematic views”] the second doped region.
In regard to claim 5 Takatsuka and Fujiwara as combined teaches wherein the shape of the first doped region and the insulating trench are in the form of a ring [see Takatsuka “In FIG. 1, separating regions for separating the SPADs of adjacent pixels 100 are provided on both sides of the well layer 103. As the separating regions, groove parts (trenches) are formed between the p-type semiconductor region 121 and the p-type semiconductor region 122, and an insulating film 123 and the light-shielding part 124 are embedded in the groove parts” , see “FIGS. 2A and 2B are schematic views”].
In regard to claim 6 Takatsuka and Fujiwara as combined teaches wherein the resistor is made of a conductive track [see combination Fujiwara, see doped polysilicon has a length on the insulator] resting on an upper surface of the insulating trench.
In regard to claim 7 Takatsuka and Fujiwara as combined teaches wherein the conductive track is made of polycrystalline silicon [see combination Fujiwara, see doped polysilicon].
In regard to claim 8 Takatsuka and Fujiwara as combined teaches wherein the shape of the first doped region and the insulating trench are in the form of a ring [see combination Fujiwara, see doped polysilicon has a length on the insulator and it has a open ring shape because the insulator is in the ring shaped anode semiconductor 121 and it has two ends because it is a resistor i.e. in a resistor one end of the polysilicon is one end of the resistor and the other end of the polysilicon is the other end of the resistor] and wherein the conductive track is shaped in the form of a ring but with an opening to define two ends forming terminals of the resistor.
In regard to claim 9 Takatsuka and Fujiwara as combined does not teach wherein the portion has an octagonal profile.
However see Fujiwara Fig. 22, Fig. 25, Figs. 27-29 hexagonal packing and compare to Takatsuka Fig. 2A, see that hexagonal packing is more efficient use of space.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Takatsuka to include wherein the portion has an octagonal profile.
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation is better use of space for better device preformance.
In regard to claim 10 Takatsuka and Fujiwara as combined teaches wherein an upper face of the insulating trench is coplanar [see combination Fujiwara, see an additional insulator embedded in a trench in anode semiconductor 121 and placing a length of polysilicon resistor on the insulator] with the upper face of the first doped region for the anode.
In regard to claim 11 Takatsuka and Fujiwara as combined teaches wherein the resistor rests on [see combination Fujiwara, see an additional insulator embedded in a trench in anode semiconductor 121 and placing a length of polysilicon resistor on the insulator] the upper face of the insulating trench.
In regard to claim 12 Takatsuka and Fujiwara as combined teaches wherein the anode further comprises a third doped region [102, see “In the pixel 100, an n-type semiconductor region 101 and a p-type semiconductor region 102 are formed inside a well layer 103”] buried in said portion of the substrate below and in vertical alignment [see 102 is centered below 101 i.e. alignment under broadest reasonable interpretation] with the second doped region for the cathode.
In regard to claim 13 Takatsuka and Fujiwara as combined teaches wherein said third doped region for the anode is electrically coupled [see that 121 and 102 are connected by 103 and form the anode side of the PN junction] to the first doped region for the anode.
Claim(s) 14-23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Takatsuka (US 20210183930 A1) in view of Fujiwara et al. (EP 3816659 A2) hereafter referred to as Fujiwara
In regard to claim 14 Takatsuka teaches a method of manufacturing a device [see Fig. 1 see paragraph 0051, see “FIGS. 2A and 2B are schematic views”], comprising:
a) forming a first doped region [“p-type semiconductor region 121”] for an anode of a single photon avalanche diode [“the pixel 100 including the SPAD of the APD serving as a light detection unit in the structure of the solid-state imaging device according to the first embodiment will be described as an example” “In the pixel 100, an n-type semiconductor region 101 and a p-type semiconductor region 102 are formed inside a well layer 103”] in a portion of a substrate;
b) forming a second doped region for a cathode [“n-type semiconductor region 101 functions as a cathode”] of the single photon avalanche diode in the portion of the substrate;
c) forming an insulating trench [“In FIG. 1, separating regions for separating the SPADs of adjacent pixels 100 are provided on both sides of the well layer 103. As the separating regions, groove parts (trenches) are formed between the p-type semiconductor region 121 and the p-type semiconductor region 122, and an insulating film 123 and the light-shielding part 124 are embedded in the groove parts”] within the first doped region for the anode;
but does not teach: d) forming a resistor resting on the insulating trench.
See Fujiwara teaches see Fig. 2, “For example, each photodiode PD functions as an avalanche photodiode” “first conductivity type is one of a p-type or an n-type. The second conductivity type is the other of the p-type or the n-type” “structure body 21 is insulative. The structure body 21 is provided to suppress conduction and optical interference between the semiconductor parts 10” “Each element 1 includes a quenching part. In the example, a quenching resistance 30 is provided as the quenching part. The quenching resistance 30 is electrically connected to the first semiconductor layer 11 of each photodiode PD” “For example, the quenching resistance 30 is arranged with the structure body 21 or the semiconductor region 25 in the Z-direction” “quenching resistance 30 includes polysilicon as a semiconductor material. An n-type impurity or a p-type impurity may be added to the quenching resistance 30”, see Fig. 29 see “In FIGS. 27 to 29, the arrangements of the quenching resistances and the contacts are illustrated” “in FIG. 29, the electrical resistance of the quenching resistance 30a is less than the electrical resistance of the quenching resistance 30b. For example, the length of the quenching resistance 30a is less than the length of the quenching resistance 30a when viewed from the Z-direction”. See that in Fig. 2 see that 30 is on “second insulating layer IL2” which is on “semiconductor region 25”. See that IL2 is shown in a trench as well as on “semiconductor region 25”.
Thus, see that Takatsuka already teaches the ability to embed insulator in the anode 121, see paragraph [0158] it can be partial “partially penetrates” and Fujiwara teaches “the quenching resistance 30 is arranged with the structure body 21 or the semiconductor region 25”.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Takatsuka to include an additional insulator embedded in a trench in anode semiconductor 121 and placing a length of polysilicon resistor on the insulator i.e. to modify Takatsuka to include d) forming a resistor resting on the insulating trench.
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation is to quench the SPAD of Takatsuka to prevent excess current flow.
In regard to claim 15 Takatsuka and Fujiwara as combined teaches wherein forming the first doped region comprises forming the first doped region with an upper surface coplanar with [see Takatsuka Fig. 1] an upper surface of the portion of the substrate, and wherein forming the second doped region comprises forming the second doped region with an upper surface coplanar with [see Takatsuka Fig. 1] the upper surface of the portion of the substrate.
In regard to claim 16 Takatsuka and Fujiwara as combined teaches wherein forming the resistor comprises forming a length of polysilicon [see combination Fujiwara, see doped polysilicon has a length on the insulator and the insulator is in the ring shaped anode semiconductor 121] on the upper surface of the first doped region.
In regard to claim 17 Takatsuka and Fujiwara as combined teaches further comprising doping [see combination Fujiwara, see doped polysilicon] the polysilicon.
In regard to claim 18 Takatsuka and Fujiwara as combined teaches wherein forming the first doped region comprises forming the first doped region with a shape that surrounds [see Takatsuka “In FIG. 1, separating regions for separating the SPADs of adjacent pixels 100 are provided on both sides of the well layer 103. As the separating regions, groove parts (trenches) are formed between the p-type semiconductor region 121 and the p-type semiconductor region 122, and an insulating film 123 and the light-shielding part 124 are embedded in the groove parts” , see “FIGS. 2A and 2B are schematic views”] the second doped region.
In regard to claim 19 Takatsuka and Fujiwara as combined teaches wherein the shape is a ring [see Takatsuka “In FIG. 1, separating regions for separating the SPADs of adjacent pixels 100 are provided on both sides of the well layer 103. As the separating regions, groove parts (trenches) are formed between the p-type semiconductor region 121 and the p-type semiconductor region 122, and an insulating film 123 and the light-shielding part 124 are embedded in the groove parts” , see “FIGS. 2A and 2B are schematic views”].
In regard to claim 20 Takatsuka and Fujiwara as combined teaches wherein forming the resistor comprises forming a length of polysilicon on the upper surface of the first doped region with the shape of a ring but with an opening [see combination Fujiwara, see doped polysilicon has a length on the insulator and it has a open ring shape because the insulator is in the ring shaped anode semiconductor 121 and it has two ends because it is a resistor i.e. in a resistor one end of the polysilicon is one end of the resistor and the other end of the polysilicon is the other end of the resistor] to define two ends forming terminals of the resistor.
In regard to claim 21 Takatsuka and Fujiwara as combined teaches further comprising forming an insulating wall surrounding [see Takatsuka “In FIG. 1, separating regions for separating the SPADs of adjacent pixels 100 are provided on both sides of the well layer 103. As the separating regions, groove parts (trenches) are formed between the p-type semiconductor region 121 and the p-type semiconductor region 122, and an insulating film 123 and the light-shielding part 124 are embedded in the groove parts” , see “FIGS. 2A and 2B are schematic views”] the portion for the substrate for the single photon avalanche diode.
In regard to claim 22 Takatsuka and Fujiwara as combined teaches further comprising forming a third doped region [102, see “In the pixel 100, an n-type semiconductor region 101 and a p-type semiconductor region 102 are formed inside a well layer 103”] for the anode buried in said portion of the substrate, wherein the second doped region for the cathode this is located above and in vertical alignment [see 102 is centered below 101 i.e. alignment under broadest reasonable interpretation] with the third doped region for the anode.
In regard to claim 23 Takatsuka and Fujiwara as combined teaches wherein said third doped region for the anode is electrically coupled [see that 121 and 102 are connected by 103 and form the anode side of the PN junction] to the first doped region for the anode.
Claim(s) 24-27 is/are rejected under 35 U.S.C. 103 as being unpatentable over Takatsuka (US 20210183930 A1) in view of Fujiwara et al. (EP 3816659 A2) hereafter referred to as Fujiwara
In regard to claim 24 Takatsuka teaches a device [see Fig. 1 see paragraph 0051, see “FIGS. 2A and 2B are schematic views”], comprising:
a single photon avalanche diode [“the pixel 100 including the SPAD of the APD serving as a light detection unit in the structure of the solid-state imaging device according to the first embodiment will be described as an example”] in a portion of a substrate [“In the pixel 100, an n-type semiconductor region 101 and a p-type semiconductor region 102 are formed inside a well layer 103” “p-type semiconductor region 121”];
wherein the portion has a profile delimited by a wall [“In FIG. 1, separating regions for separating the SPADs of adjacent pixels 100 are provided on both sides of the well layer 103. As the separating regions, groove parts (trenches) are formed between the p-type semiconductor region 121 and the p-type semiconductor region 122, and an insulating film 123 and the light-shielding part 124 are embedded in the groove parts”] forming a contour around the portion;
wherein the single photon avalanche diode includes:
a doped region [“p-type semiconductor region 121”] at an upper surface [bottom face in Fig. 1] of the portion of the substrate;
but does not teach: an insulating trench contained within said doped region and having a surface coplanar with the upper surface of the portion; and
a conductive track forming a resistor with two ends, said conducting track extending on said surface of the insulating trench.
See Fujiwara teaches see Fig. 2, “For example, each photodiode PD functions as an avalanche photodiode” “first conductivity type is one of a p-type or an n-type. The second conductivity type is the other of the p-type or the n-type” “structure body 21 is insulative. The structure body 21 is provided to suppress conduction and optical interference between the semiconductor parts 10” “Each element 1 includes a quenching part. In the example, a quenching resistance 30 is provided as the quenching part. The quenching resistance 30 is electrically connected to the first semiconductor layer 11 of each photodiode PD” “For example, the quenching resistance 30 is arranged with the structure body 21 or the semiconductor region 25 in the Z-direction” “quenching resistance 30 includes polysilicon as a semiconductor material. An n-type impurity or a p-type impurity may be added to the quenching resistance 30”, see Fig. 29 see “In FIGS. 27 to 29, the arrangements of the quenching resistances and the contacts are illustrated” “in FIG. 29, the electrical resistance of the quenching resistance 30a is less than the electrical resistance of the quenching resistance 30b. For example, the length of the quenching resistance 30a is less than the length of the quenching resistance 30a when viewed from the Z-direction”. See that in Fig. 2 see that 30 is on “second insulating layer IL2” which is on “semiconductor region 25”. See that IL2 is shown in a trench as well as on “semiconductor region 25”.
Thus, see that Takatsuka already teaches the ability to embed insulator in the anode 121, see paragraph [0158] it can be partial “partially penetrates” and Fujiwara teaches “the quenching resistance 30 is arranged with the structure body 21 or the semiconductor region 25”.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Takatsuka to include an additional insulator embedded in a trench in anode semiconductor 121 and placing a length of polysilicon resistor on the insulator i.e. to modify Takatsuka to include an insulating trench contained within said doped region and having a surface coplanar with the upper surface of the portion; and a conductive track forming a resistor with two ends, said conducting track extending on said surface of the insulating trench.
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation is to quench the SPAD of Takatsuka to prevent excess current flow.
In regard to claim 25 Takatsuka and Fujiwara as combined teaches wherein the conductive track is made [see combination Fujiwara, see doped polysilicon] of doped polysilicon.
In regard to claim 26 Takatsuka and Fujiwara as combined teaches wherein the doped region [see Takatsuka “p-type semiconductor region 121”] is a part of an anode of the single photon avalanche diode.
In regard to claim 27 Takatsuka and Fujiwara as combined teaches wherein the doped region surrounds [see Takatsuka “In FIG. 1, separating regions for separating the SPADs of adjacent pixels 100 are provided on both sides of the well layer 103. As the separating regions, groove parts (trenches) are formed between the p-type semiconductor region 121 and the p-type semiconductor region 122, and an insulating film 123 and the light-shielding part 124 are embedded in the groove parts” , see “FIGS. 2A and 2B are schematic views”] a cathode of the single photon avalanche diode.
Conclusion
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/SITARAMARAO S YECHURI/ Primary Examiner, Art Unit 2893