Prosecution Insights
Prosecution Insights
11 pending office actions • 7 art units • 11 examiners • 0 of 11 (0%) have an AI response strategy ready • 30 patents granted in the last 365 days
Based on the USPTO statutory response window for each pending office action. 11 of the docket's apps have a known mailing date; the rest are excluded from the tile counts.
Every pending office action with a known statutory deadline, placed on a days-until-due axis. Dots left of Today are overdue; the further right, the more runway. Cases that share a deadline window stack vertically. 11 of the docket's apps have a known mailing date.
Difficulty is derived from the rejection statutes on the most recent pending office action. §101-driven and multi-statute cases are graded Hard; §112-only and obviousness-type double-patenting cases are graded Easy; everything else is Medium. "Unknown" means we have not yet parsed a statute for that office action.
| Bucket | Cases |
|---|---|
| §103 only | 8 (73%) |
| §112 only | 2 (18%) |
| No statute on record | 1 (9%) |
How the docket's pending cases split across USPTO tech-center bands.
Manual office-action response work runs about 10 hours per case. The time-saved bands below show what IP Author's prosecution pipeline typically delivers — a conservative 20% on the low end, 35% in the middle, 50% on the high end.
| Examiner | Apps on this docket | Allow rate | Interview lift |
|---|---|---|---|
| KEAGY, ROSE ALYSSA | 1 | 96.7% | +6.3% |
| CHANG, JAY C | 1 | 84.7% | +14.5% |
| YUSHINA, GALINA G | 1 | 79.1% | +16.9% |
| MCCOY, THOMAS WILSON | 1 | 92.9% | +12.5% |
| BOOTH, RICHARD A | 1 | 85.5% | +8.3% |
| PRIDEMORE, NATHAN ANDREW | 1 | 73.8% | +20.3% |
| ONUTA, TIBERIU DAN | 1 | 77.5% | +20.1% |
| BRASFIELD, QUINTON A | 1 | 72.0% | +17.5% |
| ABDELAZIEZ, YASSER A | 1 | 86.3% | +2.5% |
| GARCES, NELSON Y | 1 | 80.2% | +2.7% |
Cases in front of an examiner with an allow rate of 80%+ where the difficulty is Easy or Medium. The top 6 ordered by deadline are shown.
| App # | Title | Examiner | Due in |
|---|---|---|---|
| 18190893 | MOS TRANSISTOR ON SOI STRUCTURE | GARCES, NELSON Y | 103d overdue |
| 18131543 | INTEGRATED CIRCUIT INCLUDING A METAL PILLAR IN CONTACT WITH A SILICON REGION ON AN OHMIC COUPLING REGION, AND CORRESPONDING MANUFACTURING METHOD | ABDELAZIEZ, YASSER A | 60d overdue |
| 18230423 | MOSFET TRANSISTOR | MCCOY, THOMAS WILSON | 44d overdue |
| 18343298 | METHOD FOR MANUFACTURING HIGH-VOLTAGE TRANSISTORS ON A SILICON-ON-INSULATOR TYPE BULK | BOOTH, RICHARD A | 2d overdue |
| 18537135 | VARIABLE-CAPACITANCE DIODE | KEAGY, ROSE ALYSSA | 5d |
| 18387627 | TRANSISTOR MANUFACTURING METHOD | CHANG, JAY C | 22d |
Cases in front of an examiner whose interview lift is 10 percentage points or more — i.e. interviewed cases historically resolve more favorably than non-interviewed ones. The top 6 ordered by deadline are shown.
| App # | Title | Examiner | Due in |
|---|---|---|---|
| 18230423 | MOSFET TRANSISTOR | MCCOY, THOMAS WILSON | 44d overdue |
| 18303409 | ELECTRICAL CONNECTION AND ITS METHOD OF FABRICATION | BRASFIELD, QUINTON A | 4d overdue |
| 18324327 | SEMICONDUCTOR DEVICE OF THE SILICON ON INSULATOR TYPE AND CORRESPONDING MANUFACTURING METHOD | PRIDEMORE, NATHAN ANDREW | 1d overdue |
| 18387627 | TRANSISTOR MANUFACTURING METHOD | CHANG, JAY C | 22d |
| 18311779 | METHOD OF MANUFACTURING AN INTERCONNECTION STRUCTURE OF AN INTEGRATED CIRCUIT | ONUTA, TIBERIU DAN | 46d |
| 18491349 | METHOD OF FABRICATING AN ELECTRONIC CHIP INCLUDING A MEMORY CIRCUIT | YUSHINA, GALINA G | 63d |
| Art Unit | Apps |
|---|---|
| 2814 | 4 |
| 2898 | 2 |
| 2818 | 1 |
| 2817 | 1 |
| 2811 | 1 |
| 2812 | 1 |
| 2893 | 1 |
| App # | Title | Examiner | Art Unit | Statutes | Status | Due in | AI | Filed |
|---|---|---|---|---|---|---|---|---|
| 18537135 | VARIABLE-CAPACITANCE DIODE | KEAGY, ROSE ALYSSA | 2818 | §112 | Non-Final OA | 5d | Pending | Dec 12, 2023 |
| 18387627 | TRANSISTOR MANUFACTURING METHOD | CHANG, JAY C | 2817 | §112 | Non-Final OA | 22d | Pending | Nov 07, 2023 |
| 18491349 | METHOD OF FABRICATING AN ELECTRONIC CHIP INCLUDING A MEMORY CIRCUIT | YUSHINA, GALINA G | 2811 | §103 | Non-Final OA | 63d | Pending | Oct 20, 2023 |
| 18230423 | MOSFET TRANSISTOR | MCCOY, THOMAS WILSON | 2814 | §103 | Non-Final OA | 44d overdue | Pending | Aug 04, 2023 |
| 18343298 | METHOD FOR MANUFACTURING HIGH-VOLTAGE TRANSISTORS ON A SILICON-ON-INSULATOR TYPE BULK | BOOTH, RICHARD A | 2812 | §103 | Non-Final OA | 2d overdue | Pending | Jun 28, 2023 |
| 18324327 | SEMICONDUCTOR DEVICE OF THE SILICON ON INSULATOR TYPE AND CORRESPONDING MANUFACTURING METHOD | PRIDEMORE, NATHAN ANDREW | 2898 | §103 | Non-Final OA | 1d overdue | Pending | May 26, 2023 |
| 18311779 | METHOD OF MANUFACTURING AN INTERCONNECTION STRUCTURE OF AN INTEGRATED CIRCUIT | ONUTA, TIBERIU DAN | 2814 | §103 | Final Rejection | 46d | Pending | May 03, 2023 |
| 18303409 | ELECTRICAL CONNECTION AND ITS METHOD OF FABRICATION | BRASFIELD, QUINTON A | 2814 | §103 | Non-Final OA | 4d overdue | Pending | Apr 19, 2023 |
| 18131543 | INTEGRATED CIRCUIT INCLUDING A METAL PILLAR IN CONTACT WITH A SILICON REGION ON AN OHMIC COUPLING REGION, AND CORRESPONDING MANUFACTURING METHOD | ABDELAZIEZ, YASSER A | 2898 | §103 | Non-Final OA | 60d overdue | Pending | Apr 06, 2023 |
| 18190893 | MOS TRANSISTOR ON SOI STRUCTURE | GARCES, NELSON Y | 2814 | §103 | Non-Final OA | 103d overdue | Pending | Mar 27, 2023 |
| 18178333 | CAPACITOR INCLUDING LATERAL PLATES AND METHOD FOR FORMING A CAPACITOR | BODNAR, JOHN A | 2893 | Other | Non-Final OA | 22d overdue | Pending | Mar 03, 2023 |
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