DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species 1 in the reply filed on 10/28/26 is acknowledged.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 is/are rejected under 35 U.S.C. 102a1 as being anticipated by Inaba (US 2021/0343717).
1. A memory device, comprising:
a memory array (Fig.3A-3B) (MCA) and [0062-0063]/Fig.12 (MCs make an array) and [0095]) comprising:
a vertical transistor (Fig.1B (30) and [0035-0036]) having a first terminal and a second terminal [0036];
a storage unit (Fig.1B (20) and [0033]) having a first end (Fig.1B (Et) and [0036]) coupled to the first terminal [0036-Et is coupled to the source] of the vertical transistor (Fig.1B (30) and [0035-0036]); and
a bit line (Fig.1B (BL) and [0036]) coupled to the second terminal [0036-BL is coupled to the drain] of the vertical transistor (Fig.1B (30) and [0035-0036]); and
a peripheral circuit (Fig.12 (21) and [0094-0095]) coupled to the memory array Fig.12 (MCs make an array) and [0095]),
wherein the vertical transistor (Fig.1B (30) and [0035-0036]) comprises a semiconductor body (Fig.1B (31) and [0036/0045]) extending in a first direction, and a gate structure (Fig.1B (G/WL) and [0035-0036]) coupled to at least one side of the semiconductor body (Fig.1B (31) and [0036/0045]); and the vertical transistor (Fig.1B (30) and [0035-0036]) is disposed between the bit line (Fig.1B (BL) and [0036]) and the storage unit (Fig.1B (20) and [0033]) along the first direction.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-3 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Okajima et al (US 2022/0285350).
1. A memory device, comprising:
a memory array (Fig.4 (110/MC) and [0138]) comprising:
a vertical transistor (Fig.4 and 7 (1-cell transistor) and [0151/0172-0174]) having a first terminal and a second terminal (Fig.7 (SDa/SDb) and [0174]);
a storage unit (Fig.4 and 7 (2) and [0161-0167]) having a first end coupled to the first terminal (Fig.7 (SDa) and [0174]) of the vertical transistor (Fig.4 and 7 (1-cell transistor) and [0151/0172-0174]); and
a bit line (Fig.4 and 7 (BL) and [0180-0186]) coupled to the second terminal (Fig.7 (SDb) and [0174]) of the vertical transistor (Fig.4 and 7 (1-cell transistor) and [0151/0172-0174]); and
a peripheral circuit (Fig.4 (TR) and [0138-0142]) coupled to the memory array (Fig.4 (110) and [0138]),
wherein the vertical transistor (Fig.4 and 7 (1-cell transistor) and [0151/0172-0174]) comprises a semiconductor body (Fig.4 and 7 (10) and [0174-0175]) extending in a first direction, and
a gate structure (Fig.4 and 7 (WL/12) and [0174]) and coupled to at least one side of the semiconductor body (Fig.4 and 7 (10) and [0174-0175]); and
the vertical transistor (Fig.4 and 7 (1-cell transistor) and [0151/0172-0174]) is disposed between the bit line (Fig.4 and 7 (BL) and [0180-0186]) and the storage unit (Fig.4 and 7 (2) and [0161-0167])along the first direction.
2. The memory device of claim 1, wherein a second end of the storage unit (Fig.4 and 7 (2) and [0161-0167]) is coupled to the peripheral circuit (Fig.4 (TR) and [0138-0142]).
3. The memory device of claim 2, wherein the storage unit (Fig.4 and 7 (2) and [0161-0167]) is disposed between the vertical transistor (Fig.4 and 7 (1-cell transistor) and [0151/0172-0174]) and the peripheral circuit (Fig.4 (TR) and [0138-0142]) along the first direction.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Okajima et al (US 2022/0285350) in further view of Cheng et al (US 20210265309).
Okajima teaches the limitations of claim 1 as cited above, and teaches disposing together the memory array (Fig.4 (110/MC) and [0138]) and the peripheral circuit (Fig.4 (TR) and [0138-0142]).
However fails to explicitly teach using a bonding interface between the memory array and peripheral circuit.
Chen et al teaches a similar device including:
4. The memory device of claim 1, further comprising: a bonding interface (Fig.7A (710) and [0083-0085] and disposed between the memory array (Fig.7A (756) and [0082]) and the peripheral circuit (Fig.7A (720) and [0082]).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Okajima’s teachings to include the bonding interface as taught by Cheng because doing so allows the memory and peripheral circuitry to be formed separately and then subsequently be stacked together thus preventing creating unnecessary stresses upon the devices during processing and securely attaching the devices in a stacking manner to conserve limited space.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Liu (WO 2020210928); Sun et al (WO 2025039205) and Zhu et al (US 2023/0060149) teach similar structures.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LAURA M MENZ whose telephone number is (571)272-1697. The examiner can normally be reached Monday-Friday 7:00-3:30.
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/LAURA M MENZ/Primary Examiner, Art Unit 2813
1/13/26
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