DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I: Claims 1-11 in the reply filed on 03/09/2026 is acknowledged. Claims 12-18 are hereby withdrawn as being related to a nonelected invention.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-11 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2017/0170151 A1 to Rhee et al. (hereinafter “Rhee”).
Regarding claim 1, Rhee discloses a light-emitting diode (LED) arrangement structure comprising:
a PCB board (display device 100, 2000 having substrate 2010; Fig. 2, 3A, 13; paragraphs [0042], [0122]), wherein a plurality of data lines extending in a first direction, a plurality of scanning lines extending in a second direction, and a plurality of via holes are disposed in a display region of the PCB board (plurality of data lines 2020 and scan lines 2040 disposed orthogonal relative one another with through holes disposed in display region of substrate 110; Figs. 13, 18E; paragraphs [0133]-[0134], [0136]); the plurality of data lines and the plurality of scanning lines are located on different layers of the PCB board, and the second direction intersects the first direction (plurality of data lines 2020 and scan lines 2040 disposed orthogonal relative one another on different layers of substrate 110; Fig. 13; paragraph [0136]); and the plurality of via holes include a plurality of first via holes and a plurality of second via holes (first plurality of through holes in layer 2170 for positioning of terminals 2152 and second plurality of through holes in layer 2170 for positioning of terminals 2156; Fig. 13; paragraph [0136]); and
a plurality of LEDs disposed on the PCB board, wherein the plurality of LEDs are arranged in an array in the first direction and the second direction to form a plurality of LED rows and a plurality of LED columns, the LED rows extend in the first direction, and the LED columns extend in the second direction (LEDs formed in array of columns of rows along directions of lines 2020, 2040; Figs. 2, 3B and 13); each of the LED rows includes a plurality of LED groups, and each of the LED groups includes two adjacent LEDs (groups of LEDs in pairs of twos; Figs. 2, 3B and 13); a plurality of adjacent LEDs are sequentially arranged in the second direction to form a plurality of light-emitting pixels (pixels formed by sequentially-arranged LEDs in second direction; Figs. 2, 3B and 13); and
each of the LEDs includes a common-electrode terminal and a non-common-electrode terminal, wherein common-electrode terminals of all LEDs in each of the LED columns are connected to a corresponding one of the scanning lines through one or more first via holes of the first via holes (each LED includes terminals 2152, 2156 where terminals 2152 are connected to scan lines 2040 via first plurality of through holes in layer 2170; Fig. 14; paragraph [0123]);
non-common-electrode terminals of all LEDs in each of the LED rows are connected to a corresponding one of the data lines (terminals 2156 connected to data lines 2020; Fig. 14); and
non-common-electrode terminals of two LEDs in each of LED groups in at least one of the LED rows are connected to each other on a surface layer of the PCB board (groups of LEDs connected to one another on surface layer of substrate 2010; Figs. 13, 15).
Regarding claim 2, Rhee discloses the LED arrangement structure according to claim 1, wherein a plurality of non-common-electrode connection lines extending in the first direction are further provided in the display area of the PCB board (connection lines 2160 disposed along direction of data lines 2020 in display area of substrate 2010; Fig. 15; paragraph [0129]), the non-common-electrode connection lines and the data lines are located at different layers of the PCB board, and the non-common-electrode connection lines and the scanning lines are located at different layers of the PCB board (lines 2020, 2040, 2160 are disposed at different layers of substrate 2010; Fig. 14); and the non-common-electrode terminals of the two LEDs in each of the LED groups are connected to a corresponding one of the non-common-electrode connection lines (terminals 2156 connected to lines 2160; Fig. 14).
Regarding claim 3, Rhee discloses the LED arrangement structure according to claim 2, wherein each of the non-common-electrode connection lines is connected to a corresponding one of the data lines through a corresponding second via hole of the second via holes (second plurality of through holes in layer 2170 connecting lines 2160 with lines 2020; Figs. 14 and 18E).
Regarding claim 4, Rhee discloses the LED arrangement structure according to claim 3, wherein in each of the LED groups, the corresponding one of the non-common-electrode connection lines is connected to a corresponding one of the data lines through at least one second via hole (in each LED group, the second plurality of through holes in layer 2170 connect lines 2160 with lines 2020; Figs. 14 and 18E).
Regarding claim 5, Rhee discloses the LED arrangement structure according to claim 1, wherein common-electrode terminals of all LEDs in each of the light-emitting pixels are connected to a corresponding one of the scanning lines through a corresponding one of the first via holes (terminals 2152 are connected to scan lines 2040 via first plurality of through holes in layer 2170; Fig. 14; paragraph [0123]).
Regarding claim 6, Rhee discloses the LED arrangement structure according to claim 1, wherein in each of the LED columns, common-electrode terminals of all LEDs of at least two adjacent light-emitting pixels are connected to a corresponding one of the scanning lines through a corresponding one of the first via holes (in each LED group, terminals 2152 are connected to scan lines 2040 via first plurality of through holes in layer 2170; Fig. 14; paragraph [0123]).
Regarding claim 7, Rhee discloses the LED arrangement structure according to claim 2, wherein the non-common-electrode terminals of the two LEDs in each of the LED groups are adjacent to each other in the first direction, and the non-common-electrode connection lines are located on the surface layer of the PCB board (in each LED group, terminals 2156 are adjacent one another in data line 2020 direction, where lines 2160 are located within surface layer of substrate 2010; Figs. 13-15).
Regarding claim 8, Rhee discloses the LED arrangement structure according to claim 1, wherein all the LEDs in each of the LED rows are LEDs with the same light-emitting color (one color phosphor may be deposited along each data line 2020; paragraphs [0063], [0105]).
Regarding claim 9, Rhee discloses the LED arrangement structure according to claim 1, wherein the LEDs comprise a plurality of red LEDs, a plurality of blue LEDs, and a plurality of green LEDs (LEDs include green, red and blue colors; paragraphs [0006], [0062]-[0063], [0104]).
Regarding claim 10, Rhee discloses the LED arrangement structure according to claim 1, wherein each of the light-emitting pixels comprises a red LED, a blue LED and a green LED (red, green and blue pixels; paragraphs [0006], [0062]-[0063], [0104]).
Regarding claim 11, Rhee discloses the LED arrangement structure according to claim 1, wherein the LEDs are encapsulated on the PCB board in a COB manner or an SMD manner (LEDs encapsulated after mounting onto substrate 2010; Figs. 14-15; paragraph [0131]).
Conclusion
The following prior art made of record and not relied upon is considered pertinent to applicant's disclosure: US 2019/0206926 A1 to Diana et al. and US 2022/0190220 A1 to Kang et al. each discloses display devices having related scan and data line arrangements relative other LED structures.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to IAN DEGRASSE whose telephone number is (571) 272-0261. The examiner can normally be reached Monday through Friday 8:30a until 5:00p.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, JEFF NATALINI can be reached on (571) 272-2266. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
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/IAN DEGRASSE/Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818
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