Attorney’s Docket Number: JHAP0165US
Filing Date: 07/11/2023
Claimed Foreign Priority Date: 05/25/2023 (CN 202310597532.4)
Applicants: Lai et al.
Examiner: Younes Boulghassoul
DETAILED ACTION
This Office action responds to the Election filed on 11/20/2025.
Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election of Group Invention I, directed to a semiconductor structure, in the reply filed on 11/20/2025, is acknowledged. Applicant indicated that claims 1-14 read on the elected Group Invention. The examiner agrees.
Accordingly, pending in the application are claims 1-20, with claims 15-20 standing withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Group Invention, there being no allowable generic or linking claim. Furthermore, because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claim 14 is rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Claim 14 recites the limitation “wherein the semiconductor substrate comprises the fin-shaped structures isolated by…” in L. 2. There is insufficient antecedent basis for this limitation in the claim, as claim 14 or claim 1 (from which claim 14 depends), are devoid of any prior recitation of a “fin-shaped structures” limitation. For the purpose of examination, the claim will be construed as reciting -- wherein the fin-shaped structures isolated by… --, until further clarifications are provided by the applicant.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-4, 9-11, and 13-14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee et al. (US2015/0255464).
Regarding Claim 1, Lee (see, e.g., Figs. 1-2 or 10; and Par. [0021]-[0027]) shows all aspects of the instant invention, including a semiconductor device, comprising:
- a semiconductor substrate having a cell region and a peripheral region (e.g., semiconductor substrate having cell region 100a and peripheral circuit region 100b), wherein the semiconductor substrate comprises at least one fin-shaped structure (e.g., one of active regions 110a,c) isolated by an insulation structure (e.g., device isolation layer 112)
- a first stacked structure disposed in the semiconductor substrate (see, e.g., Fig. 2a), wherein the first stacked structure is disposed straddling the at least one fin-shaped structure, extends in a horizontal direction, and is disposed in the cell region and the peripheral region, and the first stacked structure comprises:
an electrically conductive layer (e.g., metal gate electrode 114a) comprising:
a first portion located in the cell region
a second portion located in the peripheral region
a capping layer (e.g., polysilicon gate electrode 114b) disposed on the electrically conductive layer
a dielectric capping layer (e.g., sealing nitride layer 116) disposed on the capping layer and the electrically conductive layer, wherein the dielectric capping layer contacts a top surface of the second portion of the electrically conductive layer
- a contact structure (e.g., gate contact 120) directly contacting the electrically conductive layer and electrically connected with the first stacked structure.
Regarding Claim 2, Lee (see, e.g., Figs. 1-2) shows that at least a part of the top surface of the second portion of the electrically conductive layer (e.g., 114a in 100b) is not covered by the capping layer (e.g., 114b).
Regarding Claim 3, Lee (see, e.g., Figs. 1-2) shows that a sidewall of the capping layer (e.g., 114b) faces the contact structure (e.g., 120) in the horizontal direction, and the sidewall of the capping layer is separated from the contact structure.
Regarding Claim 4, Lee (see, e.g., Figs. 1-2) shows that the capping layer (e.g., 114b) is partly located on the first portion of the electrically conductive layer (e.g., 114a in 100a) and partly located on the second portion of the electrically conductive layer (e.g., 114a in 100b), and the sidewall of the capping layer is located above the second portion of the electrically conductive layer.
Regarding Claim 9, Lee (see, e.g., Figs. 1-2) shows that the dielectric capping layer (e.g., 116) directly contacts a top surface of the electrically conductive layer (e.g., 114a) and a top surface of the capping layer (e.g., 114b).
Regarding Claim 10, Lee (see, e.g., Figs. 1-2 and 8-9) shows a second stacked structure (e.g., bit line 118/224 having a stacked structure of a conductive pattern 224a and the hard mask pattern 224b) disposed above the semiconductor substrate, wherein the second stacked structure is located on the cell region (e.g., 100a), the second stacked structure is disposed adjacent to an interface between the cell region and the peripheral region, and a distance between a sidewall of the capping layer (e.g., 114b) and the contact structure (e.g., 120) in the horizontal direction is less than a distance between the second stacked structure (e.g., 118/224) and the contact structure in the horizontal direction (see, e.g., Fig. 2a).
Regarding Claim 11, Lee (see, e.g., Figs. 1-2 and Par. [0024]) shows that the electrically conductive layer comprises a metallic electrically conductive material (e.g., 114a of tungsten (W)), and the capping layer comprises doped polycrystalline silicon or undoped polycrystalline silicon (e.g., 114b of polysilicon).
Regarding Claim 13, Lee (see, e.g., Figs. 1-2) shows that a sidewall of the capping layer (e.g., 114b) faces the contact structure (e.g., 120) in the horizontal direction, and a distance between the sidewall of the capping layer and the contact structure in the horizontal direction is less than a distance between the at least one fin-shaped structure (e.g., 110a) and the contact structure in the horizontal direction (see, e.g., Fig. 2a).
Regarding Claim 14, Lee (see, e.g., Figs. 1-2 and 10) shows that the semiconductor substrate comprises fin-shaped structures (e.g., 100a and 110c) isolated by the insulation structure (e.g., 112), a sidewall of the capping layer (e.g., 114b) faces the contact structure (e.g., 120) in the horizontal direction, and the sidewall of the capping layer is located above one of the fin-shaped structures (e.g., 110c) closest to the contact structure among the fin-shaped structures.
Claims 1-3, 6, 9, and 13-14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Fujimoto et al. (US2021/0313330).
Regarding Claim 1, Fujimoto (see, e.g., Figs. 2 and 13A-B; and Par. [0032]-[0036],[0052]-[0058]) shows all aspects of the instant invention, including a semiconductor device, comprising:
- a semiconductor substrate having a cell region and a peripheral region (e.g., semiconductor substrate 10 having memory cell region M and memory end region N), wherein the semiconductor substrate comprises at least one fin-shaped structure (e.g., one of silicon regions 10b) isolated by an insulation structure (e.g., isolation region 12)
- a first stacked structure disposed in the semiconductor substrate (see, e.g., Fig. 13b), wherein the first stacked structure is disposed straddling the at least one fin-shaped structure, extends in a horizontal direction, and is disposed in the cell region and the peripheral region, and the first stacked structure comprises:
an electrically conductive layer (e.g., metal conductive layer 14) comprising:
a first portion located in the cell region
a second portion located in the peripheral region
a capping layer (e.g., conductive layer 20) disposed on the electrically conductive layer
a dielectric capping layer (e.g., cap fill layer 16 of silicon oxide) disposed on the capping layer and the electrically conductive layer, wherein the dielectric capping layer contacts a top surface of the second portion of the electrically conductive layer
- a contact structure (e.g., contact 18) directly contacting the electrically conductive layer and electrically connected with the first stacked structure.
Regarding Claim 2, Fujimoto (see, e.g., Figs. 2 and 13A-B) shows that at least a part of the top surface of the second portion of the electrically conductive layer (e.g., 14 in N) is not covered by the capping layer (e.g., 20).
Regarding Claim 3, Fujimoto (see, e.g., Figs. 2 and 13A-B) shows that a sidewall of the capping layer (e.g., 20) faces the contact structure (e.g., 18) in the horizontal direction, and the sidewall of the capping layer is separated from the contact structure.
Regarding Claim 6, Fujimoto (see, e.g., Figs. 2 and 13A-B) shows that the sidewall of the capping layer (e.g., 20) is located in the cell region (e.g., M).
Regarding Claim 9, Fujimoto (see, e.g., Figs. 2 and 13A-B) shows that the dielectric capping layer (e.g., 16) directly contacts a top surface of the electrically conductive layer (e.g., 14) and a top surface of the capping layer (e.g., 20).
Regarding Claim 13, Fujimoto (see, e.g., Figs. 2 and 13A-B) shows that a sidewall of the capping layer (e.g., 20) faces the contact structure (e.g., 18) in the horizontal direction, and a distance between the sidewall of the capping layer and the contact structure in the horizontal direction is less than a distance between the at least one fin-shaped structure (e.g., any 10b other than at M/N interface) and the contact structure in the horizontal direction (see, e.g., Fig. 13B).
Regarding Claim 14, Fujimoto (see, e.g., Figs. 2 and 13A-B) shows that the semiconductor substrate comprises fin-shaped structures (e.g., 10b) isolated by the insulation structure (e.g., 12), a sidewall of the capping layer (e.g., 20) faces the contact structure (e.g., 18) in the horizontal direction, and the sidewall of the capping layer is located above one of the fin-shaped structures closest to the contact structure among the fin-shaped structures (e.g., 10b at M/N interface).
Claims 1-3, 5, 9, 11, and 13-14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Honda (US2022/0293510).
Regarding Claim 1, Honda (see, e.g., Figs. 2 and 15A-B; and Par. [0032]-[0037],[0076]-[0079]) shows all aspects of the instant invention, including a semiconductor device, comprising:
- a semiconductor substrate having a cell region and a peripheral region (e.g., semiconductor substrate 10 having memory cell region M and peripheral region N), wherein the semiconductor substrate comprises at least one fin-shaped structure (e.g., one of active regions 10a) isolated by an insulation structure (e.g., insulating film 36)
- a first stacked structure disposed in the semiconductor substrate (see, e.g., Fig. 15b), wherein the first stacked structure is disposed straddling the at least one fin-shaped structure, extends in a horizontal direction, and is disposed in the cell region and the peripheral region, and the first stacked structure comprises:
an electrically conductive layer (e.g., TiN conductive part 64) comprising:
a first portion located in the cell region
a second portion located in the peripheral region
a capping layer (e.g., polysilicon layer 68) disposed on the electrically conductive layer
a dielectric capping layer (e.g., insulating film 70 of silicon oxide) disposed on the capping layer and the electrically conductive layer, wherein the dielectric capping layer contacts a top surface of the second portion of the electrically conductive layer
- a contact structure (e.g., word-line contacts 8) directly contacting the electrically conductive layer and electrically connected with the first stacked structure.
Regarding Claim 2, Honda (see, e.g., Figs. 2 and 15A-B) shows that at least a part of the top surface of the second portion of the electrically conductive layer (e.g., 64 in N) is not covered by the capping layer (e.g., 70).
Regarding Claim 3, Honda (see, e.g., Figs. 2 and 15A-B) shows that a sidewall of the capping layer (e.g., 68) faces the contact structure (e.g., 8) in the horizontal direction, and the sidewall of the capping layer is separated from the contact structure.
Regarding Claim 5, Honda (see, e.g., Figs. 2 and 15A-B) shows that the sidewall of the capping layer (e.g., 68) is located at an interface between the cell region (e.g., M) and the peripheral region (e.g., N).
Regarding Claim 9, Honda (see, e.g., Figs. 2 and 15A-B) shows that the dielectric capping layer (e.g., 70) directly contacts a top surface of the electrically conductive layer (e.g., 64) and a top surface of the capping layer (e.g., 68).
Regarding Claim 11, Honda (see, e.g., Figs. 2 and 15A-B; and Par [0073],[0076]) shows that the electrically conductive layer comprises a metallic electrically conductive material (e.g., 64 of TiN), and the capping layer comprises doped polycrystalline silicon or undoped polycrystalline silicon (e.g., 68 of polysilicon).
Regarding Claim 13, Honda (see, e.g., Figs. 2 and 15A-B) shows that a sidewall of the capping layer (e.g., 68) faces the contact structure (e.g., 8) in the horizontal direction, and a distance between the sidewall of the capping layer and the contact structure in the horizontal direction is less than a distance between the at least one fin-shaped structure (e.g., any 10b in M) and the contact structure in the horizontal direction (see, e.g., Fig. 15B).
Regarding Claim 14, Honda (see, e.g., Figs. 2 and 15A-B) shows that the semiconductor substrate comprises fin-shaped structures (e.g., 10b) isolated by the insulation structure (e.g., 36), a sidewall of the capping layer (e.g., 68) faces the contact structure (e.g., 8) in the horizontal direction, and the sidewall of the capping layer is located above one of the fin-shaped structures closest to the contact structure among the fin-shaped structures (e.g., 10b in N).
Claims 1-4 and 9-14 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Bae et al. (US2023/0363149).
Regarding Claim 1, Bae (see, e.g., Figs. 1-2 and 8; and Par. [0032]-[0037],[0074]-[0079]) shows all aspects of the instant invention, including a semiconductor device, comprising:
- a semiconductor substrate (e.g., semiconductor substrate 10) having a cell region (e.g., cell region 20) and a peripheral region (see, e.g., Fig. 2: regions 22,24 are peripheral to 20 thus do constitute a peripheral region), wherein the semiconductor substrate comprises at least one fin-shaped structure (e.g., one of cell active regions ACT) isolated by an insulation structure (e.g., cell element separation layer 105)
- a first stacked structure disposed in the semiconductor substrate (see, e.g., Fig. 8: cell gate structure 110), wherein the first stacked structure is disposed straddling the at least one fin-shaped structure, extends in a horizontal direction, and is disposed in the cell region and the peripheral region, and the first stacked structure comprises:
an electrically conductive layer (e.g., metal cell gate electrode 112) comprising:
a first portion located in the cell region
a second portion located in the peripheral region
a capping layer (e.g., polysilicon capping conductive layer 114) disposed on the electrically conductive layer
a dielectric capping layer (e.g., SiN cell gate capping layer 113) disposed on the capping layer and the electrically conductive layer, wherein the dielectric capping layer contacts a top surface of the second portion of the electrically conductive layer
- a contact structure (e.g., contact CB2) directly contacting the electrically conductive layer and electrically connected with the first stacked structure.
Regarding Claim 2, Bae (see, e.g., Figs. 1-2 and 8) shows that at least a part of the top surface of the second portion of the electrically conductive layer (e.g., 112 in 22,24) is not covered by the capping layer (e.g., 114).
Regarding Claim 3, Bae (see, e.g., Figs. 1-2 and 8) shows that a sidewall of the capping layer (e.g., 114) faces the contact structure (e.g., CB2) in the horizontal direction, and the sidewall of the capping layer is separated from the contact structure.
Regarding Claim 4, Bae (see, e.g., Figs. 1-2 and 8) shows that the capping layer (e.g., 114) is partly located on the first portion of the electrically conductive layer (e.g., 112 in 20) and partly located on the second portion of the electrically conductive layer (e.g., 112 in 22,24), and the sidewall of the capping layer is located above the second portion of the electrically conductive layer.
Regarding Claim 9, Bae (see, e.g., Figs. 1-2 and 8) shows that the dielectric capping layer (e.g., 113) directly contacts a top surface of the electrically conductive layer (e.g., 112) and a top surface of the capping layer (e.g., 114).
Regarding Claim 10, Bae (see, e.g., Figs. 1-2 and 8) shows a second stacked structure (e.g., bit line gate structure 140ST) disposed above the semiconductor substrate, wherein the second stacked structure is located on the cell region (e.g., 20), the second stacked structure is disposed adjacent to an interface between the cell region and the peripheral region, and a distance between a sidewall of the capping layer (e.g., 114) and the contact structure (e.g., CB2) in the horizontal direction is less than a distance between the second stacked structure (e.g., 140ST) and the contact structure in the horizontal direction (see, e.g., Fig. 8).
Regarding Claim 11, Bae (see, e.g., Figs. 1-2 and 8) shows that the electrically conductive layer comprises a metallic electrically conductive material (see, e.g., Par. [0054]: 112 of W, Al, or Cu), and the capping layer comprises doped polycrystalline silicon or undoped polycrystalline silicon (see, e.g., Par. [0055]: 114 of polysilicon).
Regarding Claim 12, Bae (see, e.g., Figs. 1-2 and 8) shows that a mask layer (e.g., cell insulating layer 130) disposed on the first stacked structure, wherein the mask layer is partially located on the peripheral region, and the contact structure penetrates through the mask layer.
Regarding Claim 13, Bae (see, e.g., Figs. 1-2 and 8) shows that a sidewall of the capping layer (e.g., 114) faces the contact structure (e.g., CB2) in the horizontal direction, and a distance between the sidewall of the capping layer and the contact structure in the horizontal direction is less than a distance between the at least one fin-shaped structure (e.g., ACT in 20 and directly adjacent to 22) and the contact structure in the horizontal direction (see, e.g., Fig. 8).
Regarding Claim 14, Bae (see, e.g., Figs. 1-2 and 8) shows that the semiconductor substrate comprises fin-shaped structures (e.g., CB2) isolated by the insulation structure (e.g., 105), a sidewall of the capping layer (e.g., 114) faces the contact structure (e.g., CB2) in the horizontal direction, and the sidewall of the capping layer is located above one of the fin-shaped structures closest to the contact structure among the fin-shaped structures (e.g., ACT in 20 and directly adjacent to 22).
Allowable Subject Matter
Claims 7 and 8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The additional references cited disclose DRAM devices with contacts to WLs in peripheral circuit regions, and having features similar to the instant invention.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Younes Boulghassoul at (571) 270-5514. The examiner can normally be reached on Monday-Friday 9am-6pm EST (Eastern Standard Time), or by e-mail via younes.boulghassoul@uspto.gov. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Wael Fahmy can be reached at (571) 272-1705. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/YOUNES BOULGHASSOUL/Primary Examiner, Art Unit 2814