DETAILED ACTION
This action is responsive to the following communications: the Amendment filed on June 23, 2026.
Claims 1-20 are pending. Claims 1, 8 and 15 are amended. Claims 1, 8 and 15 are independent.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 20210090660) in view of Park (US 20100195387).
Regarding independent claim 1, Kim discloses a method for multi-state programming of a memory structure, the method comprising:
initiating a programming operation to program multiple program states of a non-volatile memory structure [Fig. 4, para. 89 and 95], each of the multiple program states being associated with a different respective programming voltage bias (VPGM) level from among a plurality of programming voltage bias (VPGM) level [see Fig. 7, a program voltage having a high level, corresponding to the highest program state, is applied to the selected word line. As the level of the program voltage is increased, the rising speed of the threshold voltage of the memory cell is increased, and the program speed may also be increased. The program operation is performed on all of a plurality of program states by adjusting the length of the net program period tNet in which an actual program operation is performed, para. 134-135], the memory structure [Fig. 3: 110] comprising a plurality of memory elements [Fig. 3: BLK1, BLK2, …, BLKz, para. 82];
applying, to all selected word lines of the memory structure including word lines not being programmed to a highest program state of the multiple program states, a first programming voltage bias (VPGM) level configured to program the highest program state of the multiple program states [see Fig. 7, an identical program voltage is applied to a selected word line regardless of the target program state, para. 134], wherein the first programming voltage bias (VPGM) level is applied according to a first program pulse width [see Fig. 7, Vpgm is applied to a selected word line that is coupled to selected memory cells during a period ranging from time t1 to time t5, para. 122 and 135], and wherein the same first programming voltage bias (VPGM) level is applied to all of the selected word lines for the first group [see Fig. 7, an identical program voltage is applied to a selected word line regardless of the target program state, para. 134]; and
for each program state of the multiple program states other than the highest program state of the multiple program states, while applying the first programming voltage bias (VPGM) level, applying a different bitline voltage bias (VBL) to one or more bitlines associated with one or more of the memory elements selected to be programmed to the program states of the multiple program states other than the highest program state [based on the target program state of selected memory cells, the levels of program enable voltages that are applied to the plurality of bit lines or time points at which the program enable voltages are applied to the respective bit lines may differ from each other, para. 80. See Fig. 7, the program enable voltage is applied to a bit line that is coupled to memory cells of which the target program state is the highest program state P7. The program inhibit voltage is applied to bit lines that are coupled to memory cells of which the target program states are the other program states besides the highest program state (P1 to P6), para. 124. While a program voltage is applied to the selected word line, the period in which a program inhibit voltage is applied to a bit line, coupled to a programmed cell, is a program inhibit period tInh and the period in which a program enable voltage is applied to a bit line, is a net program period tNet, para. 128], wherein the different bitline voltage bias (VBL) is applied according to a respective program sub-pulse width that is less than the first program pulse width [see Fig. 7, when the target program state is higher, the length of the net program period tNet is longer and the length of the program inhibit period tInh is shorter, para. 129-130].
However, Kim is silent with respect to dividing the multiple program states into at least a first group and a second group, wherein each of the first group and the second group includes a different subset of the multiple program states and applying the programming voltage bias (VPGM) level and the different bitline voltage bias (VBL) for each group.
Park teaches a method for multi-state programming of a memory structure, the method comprising: initiating a programming operation to program multiple program states of a non- volatile memory structure [para. 12], each of the multiple program states being associated with a different respective programming voltage bias (VPGM) level from among a plurality of programming voltage bias (VPGM) level [see Fig. 9, para. 63-65], the memory structure comprising a plurality of memory elements; and
dividing the multiple program states into at least a first group and a second group [see Fig. 9, the programming method includes a first program mode and a second program mode, para. 62-63], wherein each of the first group and the second group includes a different subset of the multiple program states [a different program mode may be used depending on a program state. For instance, the P1 and P2 programs may be performed in the first program mode and the P3 program may be performed in the second program mode, para. 68].
It would have been obvious for a person having ordinary skill in the art before the effective filling date of claimed invention to apply teachings of Park to the teaching of Kim such that modifying Kim’s programming method by dividing Kim’s plurality of target states into low-state and high-state subsets as taught by Park and applying Kim’s highest state programming technique independently to each resulting subset to decrease disturb errors and increase data reliability [see Park’s para. 93].
Regarding claim 2, Kim in combination with Park teach the limitations with respect to claim 1.
Furthermore, Kim discloses a magnitude of the respective program sub- pulse width increases an incremental amount with each higher program state [see Fig. 7, the net program period (tNet) increases when the target program state increases, para. 128-131].
Regarding claim 3, Kim in combination with Park teach the limitations with respect to claim 2.
Furthermore, Kim discloses the incremental amount is identical between each program state [see Fig. 7, interval of tNet in each program state may vary, para 147].
Regarding claim 4, Kim in combination with Park teach the limitations with respect to claim 2.
Furthermore, Kim discloses the incremental amount is nonidentical between each program state [see Fig. 7, interval of tNet in each program state may vary, para 147].
Regarding claim 5, Kim in combination with Park teach the limitations with respect to claim 1.
Furthermore, Kim discloses further comprising pre-determining a magnitude of the respective program sub-pulse width such that the program state is effectively programmed according to the first programming voltage bias (VPGM) [see Fig. 7, tNet is adjusted based on the target program state so that the threshold voltages of program cells may be more efficiently controlled, para. 134-135, 146 and 151].
Regarding claim 6, Kim in combination with Park teach the limitations with respect to claim 1.
Furthermore, Kim discloses the multiple program states are concurrently programmed within the first program pulse width [see Fig. 7, the program operations for the respective program states are performed in parallel, para. 125, 130 and 136].
Regarding claim 7, Kim in combination with Park teach the limitations with respect to claim 1.
Furthermore, Kim discloses the memory structure comprises a plurality of NAND-type memory cells [para. 34 and 46].
Regarding independent claim 8, Kim discloses a memory controller [Fig. 1: 200], comprising:
a communication pathway configured to couple to a non-volatile memory structure [Fig. 3: 110, para. 45], wherein the memory structure comprises a plurality of memory elements [Fig. 3: BLK1, BLK2, …, BLKz, para. 82];
the memory controller configured to: initiate a programming operation to program multiple program states of the memory structure [Fig. 4, para. 89 and 95], each of the multiple program states being associated with a different respective programming voltage bias (VPGM) level from among a plurality of programming voltage bias (VPGM) level [see Fig. 7, a program voltage having a high level, corresponding to the highest program state, is applied to the selected word line. As the level of the program voltage is increased, the rising speed of the threshold voltage of the memory cell is increased, and the program speed may also be increased. The program operation is performed on all of a plurality of program states by adjusting the length of the net program period tNet in which an actual program operation is performed, para. 134-135];
apply, to all selected word lines of the memory structure including word lines not being programmed to a highest program state of the multiple program states, a first programming voltage bias (VPGM) level configured to program the highest program state of the multiple program states [see Fig. 7, an identical program voltage is applied to a selected word line regardless of the target program state, para. 134], wherein the first programming voltage bias (VPGM) level is applied according to a first program pulse width [see Fig. 7, Vpgm is applied to a selected word line that is coupled to selected memory cells during a period ranging from time t1 to time t5, para. 122 and 135], and wherein the same first programming voltage bias (VPGM) level is applied to all of the selected word lines for the first group [see Fig. 7, an identical program voltage is applied to a selected word line regardless of the target program state, para. 134];
for each program state of the multiple program states other than the highest program state of the multiple program states, while applying the first programming voltage bias (VPGM) level, apply a different bitline voltage bias (VBL) to one or more bitlines associated with one or more of the memory elements selected to be programmed to the program states of the multiple program states other than the highest program state [based on the target program state of selected memory cells, the levels of program enable voltages that are applied to the plurality of bit lines or time points at which the program enable voltages are applied to the respective bit lines may differ from each other, para. 80. See Fig. 7, the program enable voltage is applied to a bit line that is coupled to memory cells of which the target program state is the highest program state P7. The program inhibit voltage is applied to bit lines that are coupled to memory cells of which the target program states are the other program states besides the highest program state (P1 to P6), para. 124. While a program voltage is applied to the selected word line, the period in which a program inhibit voltage is applied to a bit line, coupled to a programmed cell, is a program inhibit period tInh and the period in which a program enable voltage is applied to a bit line, is a net program period tNet, para. 128], wherein the different bitline voltage bias (VBL) is applied according to a respective program sub-pulse width that is less than the first program pulse width [see Fig. 7, when the target program state is higher, the length of the net program period tNet is longer and the length of the program inhibit period tInh is shorter, para. 129-130].
However, Kim is silent with respect to dividing the multiple program states into at least a first group and a second group, wherein each of the first group and the second group includes a different subset of the multiple program states and applying the programming voltage bias (VPGM) level and the different bitline voltage bias (VBL) for each group.
Park teaches a memory controller [Fig. 4: 60], comprising a communication pathway configured to couple to a non-volatile memory structure, wherein the memory structure comprises a plurality of memory elements [para. 42];
the memory controller configured to initiate a programming operation to program multiple program states of a non- volatile memory structure [para. 12], each of the multiple program states being associated with a different respective programming voltage bias (VPGM) level from among a plurality of programming voltage bias (VPGM) level [see Fig. 9, para. 63-65], the memory structure comprising a plurality of memory elements; and
divide the multiple program states into at least a first group and a second group [see Fig. 9, the programming method includes a first program mode and a second program mode, para. 62-63], wherein each of the first group and the second group includes a different subset of the multiple program states [a different program mode may be used depending on a program state. For instance, the P1 and P2 programs may be performed in the first program mode and the P3 program may be performed in the second program mode, para. 68].
It would have been obvious for a person having ordinary skill in the art before the effective filling date of claimed invention to apply teachings of Park to the teaching of Kim such that modifying Kim’s programming method by dividing Kim’s plurality of target states into low-state and high-state subsets as taught by Park and applying Kim’s highest state programming technique independently to each resulting subset to decrease disturb errors and increase data reliability [see Park’s para. 93].
Regarding claim 9, Kim in combination with Park teach the limitations with respect to claim 8.
Furthermore, Kim discloses a magnitude of the respective program sub- pulse width increases an incremental amount with each higher program state [see Fig. 7, the net program period (tNet) increases when the target program state increases, para. 128-131].
Regarding claim 10, Kim in combination with Park teach the limitations with respect to claim 9.
Furthermore, Kim discloses the incremental amount is identical between each program state [see Fig. 7, intervals of tNet in each program state may vary, para 147].
Regarding claim 11, Kim in combination with Park teach the limitations with respect to claim 9.
Furthermore, Kim discloses the incremental amount is nonidentical between each program state [see Fig. 7, interval of tNet in each program state may vary, para 147].
Regarding claim 12, Kim in combination with Park teach the limitations with respect to claim 8.
Furthermore, Kim discloses further comprising pre-determining a magnitude of the respective program sub-pulse width such that the program state is effectively programmed according to the first programming voltage bias (VPGM) level [see Fig. 7, tNet is adjusted based on the target program state so that the threshold voltages of program cells may be more efficiently controlled, para. 134-135, 146 and 151].
Regarding claim 13, Kim in combination with Park teach the limitations with respect to claim 8.
Furthermore, Kim discloses the multiple program states are concurrently programmed within the first program pulse width [see Fig. 7, the program operations for the respective program states are performed in parallel, para. 125, 130 and 136].
Regarding claim 14, Kim in combination with Park teach the limitations with respect to claim 8.
Furthermore, Kim discloses the memory structure comprises a plurality of NAND-type memory cells [para. 34 and 46].
Regarding independent claim 15, Kim discloses a non-volatile memory system [Fig. 1: 100], comprising:
a memory structure comprising a population of NAND-type memory elements [para. 34 and 45-46]; and
a memory controller [Fig. 200] coupled to the memory structure and: initiating a programming operation to multiple program states of a non-volatile memory structure [Fig. 4, para. 89 and 95], each of the multiple program states being associated with a different respective programming voltage bias (VPGM) level from among a plurality of programming voltage bias (VPGM) level [see Fig. 7, a program voltage having a high level, corresponding to the highest program state, is applied to the selected word line. As the level of the program voltage is increased, the rising speed of the threshold voltage of the memory cell is increased, and the program speed may also be increased. The program operation is performed on all of a plurality of program states by adjusting the length of the net program period tNet in which an actual program operation is performed, para. 134-135];
applying, to all selected word lines of the memory structure including word lines not being programmed to a highest program state of the multiple program states, a first programming voltage bias (VPGM) level configured to program the highest program state of the multiple program states [see Fig. 7, an identical program voltage is applied to a selected word line regardless of the target program state, para. 134], wherein the first programming voltage bias (VPGM) level is applied according to a first program pulse width [see Fig. 7, Vpgm is applied to a selected word line that is coupled to selected memory cells during a period ranging from time t1 to time t5, para. 122 and 135], and wherein the same first programming voltage bias (VPGM) level is applied to all of the selected word lines for the first group [see Fig. 7, an identical program voltage is applied to a selected word line regardless of the target program state, para. 134]; and
for each program state of the multiple program states other than the highest program state of the multiple program states, while applying the first programming voltage bias (VPGM) level, applying a different bitline voltage bias (VBL) to one or more bitlines associated with one or more of the memory elements selected to be programmed to the program states of the multiple program states other than the highest program state [based on the target program state of selected memory cells, the levels of program enable voltages that are applied to the plurality of bit lines or time points at which the program enable voltages are applied to the respective bit lines may differ from each other, para. 80. See Fig. 7, the program enable voltage is applied to a bit line that is coupled to memory cells of which the target program state is the highest program state P7. The program inhibit voltage is applied to bit lines that are coupled to memory cells of which the target program states are the other program states besides the highest program state (P1 to P6), para. 124. While a program voltage is applied to the selected word line, the period in which a program inhibit voltage is applied to a bit line, coupled to a programmed cell, is a program inhibit period tInh and the period in which a program enable voltage is applied to a bit line, is a net program period tNet, para. 128], wherein the different bitline voltage bias (VBL) is applied according to a respective program sub-pulse width that is less than the first program pulse width [see Fig. 7, when the target program state is higher, the length of the net program period tNet is longer and the length of the program inhibit period tInh is shorter, para. 129-130].
However, Kim is silent with respect to dividing the multiple program states into at least a first group and a second group, wherein each of the first group and the second group includes a different subset of the multiple program states and applying the programming voltage bias (VPGM) level and the different bitline voltage bias (VBL) for each group.
Park teaches a non-volatile memory system [Fig. 4: 10, para. 37], comprising a memory structure [Fig. 4: 20] comprising a population of NAND-type memory elements [para. 38] and a memory controller [Fig. 4: 60] coupled to the memory structure [para. 42] and
initiating a programming operation to program multiple program states of a non- volatile memory structure [para. 12], each of the multiple program states being associated with a different respective programming voltage bias (VPGM) level from among a plurality of programming voltage bias (VPGM) level [see Fig. 9, para. 63-65], the memory structure comprising a plurality of memory elements; and
dividing the multiple program states into at least a first group and a second group [see Fig. 9, the programming method includes a first program mode and a second program mode, para. 62-63], wherein each of the first group and the second group includes a different subset of the multiple program states [a different program mode may be used depending on a program state. For instance, the P1 and P2 programs may be performed in the first program mode and the P3 program may be performed in the second program mode, para. 68].
It would have been obvious for a person having ordinary skill in the art before the effective filling date of claimed invention to apply teachings of Park to the teaching of Kim such that modifying Kim’s programming method by dividing Kim’s plurality of target states into low-state and high-state subsets as taught by Park and applying Kim’s highest state programming technique independently to each resulting subset to decrease disturb errors and increase data reliability [see Park’s para. 93].
Regarding claim 16, Kim in combination with Park teach the limitations with respect to claim 15.
Furthermore, Kim discloses a magnitude of the respective program sub- pulse width increases an incremental amount with each higher program state [see Fig. 7, the net program period (tNet) increases when the target program state increases, para. 128-131].
Regarding claim 17, Kim in combination with Park teach the limitations with respect to claim 16.
Furthermore, Kim discloses the incremental amount is identical between each program state [see Fig. 7, interval of tNet in each program state may vary, para 147].
Regarding claim 18, Kim in combination with Park teach the limitations with respect to claim 16.
Furthermore, Kim discloses the incremental amount is nonidentical between each program state [see Fig. 7, interval of tNet in each program state may vary, para 147].
Regarding claim 19, Kim in combination with Park teach the limitations with respect to claim 15.
Furthermore, Kim discloses a magnitude of the respective program sub-pulse width is pre-determined such that the program state is effectively programmed according to the first programming voltage bias (VPGM) level [tNet is adjusted based on the target program state so that the threshold voltages of program cells may be more efficiently controlled, para. 134-135, 146 and 151].
Regarding claim 20, Kim in combination with Park teach the limitations with respect to claim 15.
Furthermore, Kim discloses the multiple program states are concurrently programmed within the first program pulse width [see Fig. 7, the program operations for the respective program states are performed in parallel, para. 125, 130 and 136].
Response to Arguments
Applicant's arguments filed on June 23, 2026 with respect to claim 1 have been fully considered but they are not persuasive.
With respect to independent claim 1, Applicant asserted that Kim and Park fail to disclose “the same first programming voltage bias (VPGM) level is applied to all of the selected word lines for the first group and the same second programming voltage bias (VPGM) level is applied to all of the selected word lines for the second group”, as recited in claim 1. “Accordingly, Park cannot be relied upon to make up for the deficiencies of Kim with respect to the recited manner in which the first and second programming voltage bias levels are applied for the first and second groups”, see Applicant’s Remarks pages 10-13. This particular remark is not considered persuasive.
The Examiner acknowledges that Kim does not disclose dividing the multiple program states into at least a first group and a second group. However, the rejection does not rely upon Kim alone for the claimed grouping. Rather, Kim is relied upon for teaching the manner in which a common programming voltage is applied to a plurality of target programming states, while Park is relied upon for teaching that different subsets of program states may be subject to different programming modes.
Kim teaches in the embodiment of Fig. 7, “an identical program voltage is applied to a selected word line regardless of the target program state” and “a program voltage having a high level, corresponding to the highest program state, may be applied to the selected word line” [para. 134]. Kim then teaches rather than varying the program voltage level for the individual target states, the programming of the plurality of states may be controlled by adjusting the length of the net program period tNet, whereby the respective program states may be programmed in parallel [para. 135-136]. Kim further teaches the actual programming interval for a memory cell may be varied according to the target program state. Specifically, while VPGM is applied to the selected word line, a program enable voltage is applied to the corresponding bit line during a net program period tNet and a higher target program state may have a longer net program period [para. 128-131]. Kim additionally teaches determining both the time at which a program enable voltage is applied and the level of that voltage based on target program state.
Park is relied upon for the additional teaching of separating program states according to program state level and subjecting the resulting subsets to different programming modes. Park teaches the programming method includes a first program mode and a second program mode [para. 62-63]. Park further describes a different program mode may be used depending on a program state. For instance, the P1 and P2 programs may be performed in the first program mode and the P3 program may be performed in the second program mode [para. 68]. Accordingly, Park teaches the principle of partitioning target program states according to their respective program state levels and applying different programming mode to the resulting subsets.
Applicant agued that “Park fails to disclose applying the programming voltage bias levels for the first and second groups in the same manner as recited in the claims as amended” because Park teaches incrementally increasing VPGM during its first programming mode, whereas VPGM is maintained at a maximum value during the second programming mode. However, Applicant’s argument does not address the combination as proposed. The rejection does not require incorporating Park’s particular stepwise VPGM waveform into Kim. Rather, Park is relied upon for its teaching of partitioning program states according to state level, while Kim’s common highest state VPGM programming technique is retained and applied to each resulting subset.
It would have been obvious for a person having ordinary skill in the art before the effective filling date of claimed invention to apply teachings of Park to the teaching of Kim such that modifying Kim’s programming method by dividing Kim’s plurality of target states into low-state and high-state subsets as taught by Park and applying Kim’s highest state programming technique independently to each resulting subset to decrease disturb errors and increase data reliability [see Park’s para. 93].
For the above reason, the previously applied rejection is considered proper and maintained. The independent claims 8 and 15 were argued for substantially the same reason, and the arguments are not persuasive for the same reason.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DUY H LUONG whose telephone number is (571)270-5088. The examiner can normally be reached Mon-Fri. 9am-6pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander Sofocleous can be reached at (571)272-0635. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/DUY H LUONG/Examiner, Art Unit 2825
/ANTHAN TRAN/Primary Examiner, Art Unit 2825
Prosecution Insights