DETAILED ACTION
This action is responsive to the following communications: the Amendment filed on December 17, 2025.
Claims 1-20 are pending. Claims 1, 8 and 15 are amended. Claims 1, 8 and 15 are independent.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments, see Applicant’s Remarks page 9, filed on December 17, 2025, with respect to the Specification have been fully considered and are persuasive. The objection of the Specification has been withdrawn.
Applicant’s arguments with respect to claims 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Objections
Claims 1, 8 and 15 objected to because of the following informalities:
In Claim 1, line 33, “less than second first program pulse width” should be --less than the second program pulse width--.
In Claim 8, line 35, “less than second first program pulse width” should be --less than the second program pulse width--.
In Claim 15, line 34, “less than second first program pulse width” should be --less than the second program pulse width--.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 20210090660) in view of Park (US 20100195387).
Regarding independent claim 1, Kim discloses a method for multi-state programming of a memory structure, the method comprising:
initiating a programming operation to program multiple program states of a non-volatile memory structure [Fig. 4, para. 89 and 95], each of the multiple program states being associated with a different respective programming voltage bias (VPGM) level from among a plurality of programming voltage bias (VPGM) level [see Fig. 7, a program voltage having a high level, corresponding to the highest program state, is applied to the selected word line. As the level of the program voltage is increased, the rising speed of the threshold voltage of the memory cell is increased, and the program speed may also be increased. The program operation is performed on all of a plurality of program states by adjusting the length of the net program period tNet in which an actual program operation is performed, para. 134-135], the memory structure [Fig. 3: 110] comprising a plurality of memory elements [Fig. 3: BLK1, BLK2, …, BLKz, para. 82];
applying, to all selected word lines of the memory structure including word lines not being programmed to a highest program state of the multiple program states, a first programming voltage bias (VPGM) level configured to program the highest program state of the multiple program states [see Fig. 7, an identical program voltage is applied to a selected word line regardless of the target program state, para. 134], wherein the first programming voltage bias (VPGM) level is applied according to a first program pulse width [see Fig. 7, Vpgm is applied to a selected word line that is coupled to selected memory cells during a period ranging from time t1 to time t5, para. 122 and 135]; and
for each program state of the multiple program states other than the highest program state of the multiple program states, while applying the first programming voltage bias (VPGM) level, applying a different bitline voltage bias (VBL) to one or more bitlines associated with one or more of the memory elements selected to be programmed to the program states of the multiple program states other than the highest program state [based on the target program state of selected memory cells, the levels of program enable voltages that are applied to the plurality of bit lines or time points at which the program enable voltages are applied to the respective bit lines may differ from each other, para. 80. See Fig. 7, the program enable voltage is applied to a bit line that is coupled to memory cells of which the target program state is the highest program state P7. The program inhibit voltage is applied to bit lines that are coupled to memory cells of which the target program states are the other program states besides the highest program state (P1 to P6), para. 124. While a program voltage is applied to the selected word line, the period in which a program inhibit voltage is applied to a bit line, coupled to a programmed cell, is a program inhibit period tInh and the period in which a program enable voltage is applied to a bit line, is a net program period tNet, para. 128], wherein the different bitline voltage bias (VBL) is applied according to a respective program sub-pulse width that is less than the first program pulse width [see Fig. 7, when the target program state is higher, the length of the net program period tNet is longer and the length of the program inhibit period tInh is shorter, para. 129-130].
However, Kim is silent with respect to dividing the multiple program states into at least a first group and a second group, wherein each of the first group and the second group includes a different subset of the multiple program states and applying the programming voltage bias (VPGM) level and the different bitline voltage bias (VBL) for each group.
Park teaches a method for multi-state programming of a memory structure, the method comprising: initiating a programming operation to program multiple program states of a non- volatile memory structure [para. 12], each of the multiple program states being associated with a different respective programming voltage bias (VPGM) level from among a plurality of programming voltage bias (VPGM) level [see Fig. 9, para. 63-65], the memory structure comprising a plurality of memory elements; and
dividing the multiple program states into at least a first group and a second group [see Fig. 9, the programming method includes a first program mode and a second program mode, para. 62-63], wherein each of the first group and the second group includes a different subset of the multiple program states [a different program mode may be used depending on a program state. For instance, the P1 and P2 programs may be performed in the first program mode and the P3 program may be performed in the second program mode, para. 68].
It would have been obvious for a person having ordinary skill in the art before the effective filling date of claimed invention to apply teachings of Park to the teaching of Kim such that applying Kim’s per state programming into each of Park’s program mode with different program states to decrease disturb errors and increase data reliability [see Park’s para. 93].
Regarding claim 2, Kim in combination with Park teach the limitations with respect to claim 1.
Furthermore, Kim discloses a magnitude of the respective program sub- pulse width increases an incremental amount with each higher program state [see Fig. 7, the net program period (tNet) increases when the target program state increases, para. 128-131].
Regarding claim 3, Kim in combination with Park teach the limitations with respect to claim 2.
Furthermore, Kim discloses the incremental amount is identical between each program state [see Fig. 7, interval of tNet in each program state may vary, para 147].
Regarding claim 4, Kim in combination with Park teach the limitations with respect to claim 2.
Furthermore, Kim discloses the incremental amount is nonidentical between each program state [see Fig. 7, interval of tNet in each program state may vary, para 147].
Regarding claim 5, Kim in combination with Park teach the limitations with respect to claim 1.
Furthermore, Kim discloses further comprising pre-determining a magnitude of the respective program sub-pulse width such that the program state is effectively programmed according to the first programming voltage bias (VPGM) [see Fig. 7, tNet is adjusted based on the target program state so that the threshold voltages of program cells may be more efficiently controlled, para. 134-135, 146 and 151].
Regarding claim 6, Kim in combination with Park teach the limitations with respect to claim 1.
Furthermore, Kim discloses the multiple program states are concurrently programmed within the first program pulse width [see Fig. 7, the program operations for the respective program states are performed in parallel, para. 125, 130 and 136].
Regarding claim 7, Kim in combination with Park teach the limitations with respect to claim 1.
Furthermore, Kim discloses the memory structure comprises a plurality of NAND-type memory cells [para. 34 and 46].
Regarding independent claim 8, Kim discloses a memory controller [Fig. 1: 200], comprising:
a communication pathway configured to couple to a non-volatile memory structure [Fig. 3: 110, para. 45], wherein the memory structure comprises a plurality of memory elements [Fig. 3: BLK1, BLK2, …, BLKz, para. 82];
the memory controller configured to: initiate a programming operation to program multiple program states of the memory structure [Fig. 4, para. 89 and 95], each of the multiple program states being associated with a different respective programming voltage bias (VPGM) level from among a plurality of programming voltage bias (VPGM) level [see Fig. 7, a program voltage having a high level, corresponding to the highest program state, is applied to the selected word line. As the level of the program voltage is increased, the rising speed of the threshold voltage of the memory cell is increased, and the program speed may also be increased. The program operation is performed on all of a plurality of program states by adjusting the length of the net program period tNet in which an actual program operation is performed, para. 134-135];
apply, to all selected word lines of the memory structure including word lines not being programmed to a highest program state of the multiple program states, a first programming voltage bias (VPGM) level configured to program the highest program state of the multiple program states [see Fig. 7, an identical program voltage is applied to a selected word line regardless of the target program state, para. 134], wherein the first programming voltage bias (VPGM) level is applied according to a first program pulse width [see Fig. 7, Vpgm is applied to a selected word line that is coupled to selected memory cells during a period ranging from time t1 to time t5, para. 122 and 135];
for each program state of the multiple program states other than the highest program state of the multiple program states, while applying the first programming voltage bias (VPGM) level, apply a different bitline voltage bias (VBL) to one or more bitlines associated with one or more of the memory elements selected to be programmed to the program states of the multiple program states other than the highest program state [based on the target program state of selected memory cells, the levels of program enable voltages that are applied to the plurality of bit lines or time points at which the program enable voltages are applied to the respective bit lines may differ from each other, para. 80. See Fig. 7, the program enable voltage is applied to a bit line that is coupled to memory cells of which the target program state is the highest program state P7. The program inhibit voltage is applied to bit lines that are coupled to memory cells of which the target program states are the other program states besides the highest program state (P1 to P6), para. 124. While a program voltage is applied to the selected word line, the period in which a program inhibit voltage is applied to a bit line, coupled to a programmed cell, is a program inhibit period tInh and the period in which a program enable voltage is applied to a bit line, is a net program period tNet, para. 128], wherein the different bitline voltage bias (VBL) is applied according to a respective program sub-pulse width that is less than the first program pulse width [see Fig. 7, when the target program state is higher, the length of the net program period tNet is longer and the length of the program inhibit period tInh is shorter, para. 129-130].
However, Kim is silent with respect to dividing the multiple program states into at least a first group and a second group, wherein each of the first group and the second group includes a different subset of the multiple program states and applying the programming voltage bias (VPGM) level and the different bitline voltage bias (VBL) for each group.
Park teaches a memory controller [Fig. 4: 60], comprising a communication pathway configured to couple to a non-volatile memory structure, wherein the memory structure comprises a plurality of memory elements [para. 42];
the memory controller configured to initiate a programming operation to program multiple program states of a non- volatile memory structure [para. 12], each of the multiple program states being associated with a different respective programming voltage bias (VPGM) level from among a plurality of programming voltage bias (VPGM) level [see Fig. 9, para. 63-65], the memory structure comprising a plurality of memory elements; and
divide the multiple program states into at least a first group and a second group [see Fig. 9, the programming method includes a first program mode and a second program mode, para. 62-63], wherein each of the first group and the second group includes a different subset of the multiple program states [a different program mode may be used depending on a program state. For instance, the P1 and P2 programs may be performed in the first program mode and the P3 program may be performed in the second program mode, para. 68].
It would have been obvious for a person having ordinary skill in the art before the effective filling date of claimed invention to apply teachings of Park to the teaching of Kim such that applying Kim’s per state programming into each of Park’s program mode with different program states to decrease disturb errors and increase data reliability [see Park’s para. 93].
Regarding claim 9, Kim in combination with Park teach the limitations with respect to claim 8.
Furthermore, Kim discloses a magnitude of the respective program sub- pulse width increases an incremental amount with each higher program state [see Fig. 7, the net program period (tNet) increases when the target program state increases, para. 128-131].
Regarding claim 10, Kim in combination with Park teach the limitations with respect to claim 9.
Furthermore, Kim discloses the incremental amount is identical between each program state [see Fig. 7, intervals of tNet in each program state may vary, para 147].
Regarding claim 11, Kim in combination with Park teach the limitations with respect to claim 9.
Furthermore, Kim discloses the incremental amount is nonidentical between each program state [see Fig. 7, interval of tNet in each program state may vary, para 147].
Regarding claim 12, Kim in combination with Park teach the limitations with respect to claim 8.
Furthermore, Kim discloses further comprising pre-determining a magnitude of the respective program sub-pulse width such that the program state is effectively programmed according to the first programming voltage bias (VPGM) level [see Fig. 7, tNet is adjusted based on the target program state so that the threshold voltages of program cells may be more efficiently controlled, para. 134-135, 146 and 151].
Regarding claim 13, Kim in combination with Park teach the limitations with respect to claim 8.
Furthermore, Kim discloses the multiple program states are concurrently programmed within the first program pulse width [see Fig. 7, the program operations for the respective program states are performed in parallel, para. 125, 130 and 136].
Regarding claim 14, Kim in combination with Park teach the limitations with respect to claim 8.
Furthermore, Kim discloses the memory structure comprises a plurality of NAND-type memory cells [para. 34 and 46].
Regarding independent claim 15, Kim discloses a non-volatile memory system [Fig. 1: 100], comprising:
a memory structure comprising a population of NAND-type memory elements [para. 34 and 45-46]; and
a memory controller [Fig. 200] coupled to the memory structure and: initiating a programming operation to multiple program states of a non-volatile memory structure [Fig. 4, para. 89 and 95], each of the multiple program states being associated with a different respective programming voltage bias (VPGM) level from among a plurality of programming voltage bias (VPGM) level [see Fig. 7, a program voltage having a high level, corresponding to the highest program state, is applied to the selected word line. As the level of the program voltage is increased, the rising speed of the threshold voltage of the memory cell is increased, and the program speed may also be increased. The program operation is performed on all of a plurality of program states by adjusting the length of the net program period tNet in which an actual program operation is performed, para. 134-135];
applying, to all selected word lines of the memory structure including word lines not being programmed to a highest program state of the multiple program states, a first programming voltage bias (VPGM) level configured to program the highest program state of the multiple program states [see Fig. 7, an identical program voltage is applied to a selected word line regardless of the target program state, para. 134], wherein the first programming voltage bias (VPGM) level is applied according to a first program pulse width [see Fig. 7, Vpgm is applied to a selected word line that is coupled to selected memory cells during a period ranging from time t1 to time t5, para. 122 and 135]; and
for each program state of the multiple program states other than the highest program state of the multiple program states, while applying the first programming voltage bias (VPGM) level, applying a different bitline voltage bias (VBL) to one or more bitlines associated with one or more of the memory elements selected to be programmed to the program states of the multiple program states other than the highest program state [based on the target program state of selected memory cells, the levels of program enable voltages that are applied to the plurality of bit lines or time points at which the program enable voltages are applied to the respective bit lines may differ from each other, para. 80. See Fig. 7, the program enable voltage is applied to a bit line that is coupled to memory cells of which the target program state is the highest program state P7. The program inhibit voltage is applied to bit lines that are coupled to memory cells of which the target program states are the other program states besides the highest program state (P1 to P6), para. 124. While a program voltage is applied to the selected word line, the period in which a program inhibit voltage is applied to a bit line, coupled to a programmed cell, is a program inhibit period tInh and the period in which a program enable voltage is applied to a bit line, is a net program period tNet, para. 128], wherein the different bitline voltage bias (VBL) is applied according to a respective program sub-pulse width that is less than the first program pulse width [see Fig. 7, when the target program state is higher, the length of the net program period tNet is longer and the length of the program inhibit period tInh is shorter, para. 129-130].
However, Kim is silent with respect to dividing the multiple program states into at least a first group and a second group, wherein each of the first group and the second group includes a different subset of the multiple program states and applying the programming voltage bias (VPGM) level and the different bitline voltage bias (VBL) for each group.
Park teaches a non-volatile memory system [Fig. 4: 10, para. 37], comprising a memory structure [Fig. 4: 20] comprising a population of NAND-type memory elements [para. 38] and a memory controller [Fig. 4: 60] coupled to the memory structure [para. 42] and
initiating a programming operation to program multiple program states of a non- volatile memory structure [para. 12], each of the multiple program states being associated with a different respective programming voltage bias (VPGM) level from among a plurality of programming voltage bias (VPGM) level [see Fig. 9, para. 63-65], the memory structure comprising a plurality of memory elements; and
dividing the multiple program states into at least a first group and a second group [see Fig. 9, the programming method includes a first program mode and a second program mode, para. 62-63], wherein each of the first group and the second group includes a different subset of the multiple program states [a different program mode may be used depending on a program state. For instance, the P1 and P2 programs may be performed in the first program mode and the P3 program may be performed in the second program mode, para. 68].
It would have been obvious for a person having ordinary skill in the art before the effective filling date of claimed invention to apply teachings of Park to the teaching of Kim such that applying Kim’s per state programming into each of Park’s program mode with different program states to decrease disturb errors and increase data reliability [see Park’s para. 93].
Regarding claim 16, Kim in combination with Park teach the limitations with respect to claim 15.
Furthermore, Kim discloses a magnitude of the respective program sub- pulse width increases an incremental amount with each higher program state [see Fig. 7, the net program period (tNet) increases when the target program state increases, para. 128-131].
Regarding claim 17, Kim in combination with Park teach the limitations with respect to claim 16.
Furthermore, Kim discloses the incremental amount is identical between each program state [see Fig. 7, interval of tNet in each program state may vary, para 147].
Regarding claim 18, Kim in combination with Park teach the limitations with respect to claim 16.
Furthermore, Kim discloses the incremental amount is nonidentical between each program state [see Fig. 7, interval of tNet in each program state may vary, para 147].
Regarding claim 19, Kim in combination with Park teach the limitations with respect to claim 15.
Furthermore, Kim discloses a magnitude of the respective program sub-pulse width is pre-determined such that the program state is effectively programmed according to the first programming voltage bias (VPGM) level [tNet is adjusted based on the target program state so that the threshold voltages of program cells may be more efficiently controlled, para. 134-135, 146 and 151].
Regarding claim 20, Kim in combination with Park teach the limitations with respect to claim 15.
Furthermore, Kim discloses the multiple program states are concurrently programmed within the first program pulse width [see Fig. 7, the program operations for the respective program states are performed in parallel, para. 125, 130 and 136].
Conclusion
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/DUY H LUONG/Examiner, Art Unit 2825
/ALEXANDER SOFOCLEOUS/Supervisory Patent Examiner, Art Unit 2825