DETAILED ACTION
Claims 1-19 have been examined.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on March 31, 2025, has been entered.
Specification
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Drawings
Replacement FIG.1 submitted on March 31, 2025, is objected to for failing to comply with 37 CFR 1.84(a)(1) and 37 CFR 1.84(l), which requires the drawings be in black, and that all drawings be made by a process which will give them satisfactory reproduction characteristics. Every line, number, and letter must be durable, clean, solid black (except for color drawings), sufficiently dense and dark, and uniformly thick and well-defined. The weight of all lines and letters must be heavy enough to permit adequate reproduction. This requirement applies to all lines however fine, to shading, and to lines representing cut surfaces in sectional views. While the boxes, arrows, and lead lines are in black, the text in the drawing is pixelated, likely because applicant did not use black (RGB = 000), despite the drawings appearing black to the naked eye. This cannot be confirmed with certainty since the examiner does not have access to applicant’s submitted pdf file. However, it is the examiner’s experience that pixelation usually occurs when black is not being used. In such a case, the dithering used to convert applicant's grayscale image to black and white will add white pixels to try to estimate applicant's "gray" color, and the final drawings may not print properly or may print with reduced quality. Therefore, applicant must be sure to use only black and white. Applicant may perform the following process to correct the color content:
1. Open the drawings PDF file with Adobe Acrobat Pro DC (a similar Adobe product may work, but the examiner has only tested this in Adobe Acrobat Pro DC);
2. Click “File” and then click “Print”;
3. Select “Adobe PDF” as the printer. If not available, “Microsoft Print to PDF” may also work, though this has not been tested. If neither option is available, this process may not be applicable, and applicant should try to find an alternate way to print in only black and white.
4. Uncheck “Print in grayscale (black and white)”;
5. Uncheck “Save ink/toner”;
6. Click “Advanced”;
7. Under “Color Management”, for the “Color Profile” field, select “Black & White” near the bottom of the list. The examiner also had “Treat grays as K-only grays” checked, and “Preserve Black” checked.
8. Click “OK” and then click “Print”. The resulting PDF should comprise only black and white drawings. Please review the final drawings for potential unintended consequences of this process.
NOTE: The examiner notes that this particular process is customized to this particular set of drawings. It may not work on other sets of drawings in other applications. If applicant is unable to perform the above conversion, the examiner would be willing to perform the conversion and email the resulting pdf file to applicant for formal filing once all other objections are resolved, provided an Authorization for Internet Communications (PTO/SB/439) is on record (see MPEP 502.03).
While not formally objected to, FIGs.4-5 include lower quality illustrations than the remaining FIGs. In particular, everything outside of the text appears to be fuzzy, pixelated/grainy, non-uniform, etc. The examiner recommends (not requires) an improvement in quality.
At least one corrected drawing sheet in compliance with 37 CFR 1.121(d) is required in reply to the Office action to avoid abandonment of the application. The figure or figure number of an amended drawing should not be labeled as “amended.” Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
Such claim limitations are:
In claim 10, “a first processing element running a program” and “extracting microarchitectural context information…”. From paragraphs 3 and 24, the first processing element is interpreted to include a core, microprocessor, processor, or integrated circuit, and equivalents thereof.
In claim 11, “the second processing element instantiates…”. Again, from paragraphs 3 and 24, the second processing element is interpreted to include a core, microprocessor, processor, or integrated circuit, and equivalents thereof.
In claims 14-15, “the first processing elements communicates…”. Again, from paragraphs 3 and 24, the first processing element is interpreted to include a core, microprocessor, processor, or integrated circuit, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 4-6, 8-12, 14-16, and 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Vega et al., U.S. Patent Application Publication No. 2006/0005189 A1, in view of Hennessy et al., “Computer Architecture - A Quantitative Approach”.
Referring to claim 1, Vega has taught a method, comprising:
extracting microarchitectural information (from paragraph 41 and claims 10 and 14, device state and/or memory state comprising state of processor registers, a state of virtual hardware, and/or a state of working memory, is/are extracted) from a first processing element (FIG.4, 102) associated with a program (FIG.4, VM 108) running on the first processing element, the extracted microarchitectural context information including information that tracks digital logic information of the program running on the first processing element (as stated, register data, for instance, is extracted. Register data tracks the input (operand) and result (output) information generated by the running program. All information in a digital logic system such as Vega is digital logic information);
transferring the extracted microarchitectural information to a first operating system associated with the first processing element (see claims 10 and 14, which set forth that the device state and memory state are transferred from first operating system (OS) 104. In order for OS 104 to perform the transfer, the state(s) must first be transferred to the OS (e.g. from internal registers));
forwarding, by the first operating system, the extracted microarchitectural information to a second processing element (see claim 10 and paragraph 41 and note that the information is forwarded to second element 102’ (e.g. a second host, per paragraph 36)); and
instantiating a process at the second processing element using the extracted microarchitectural information (see FIG.1, and note that a process (VM 108’) is instantiated on element 102’ that uses the data transferred from element 102. This allows for migration of a VM (e.g. see abstract and paragraphs 10-11);
Vega has not taught wherein the digital logic information comprises a process flow between two or more of an arithmetic logic unit, a register, a cache, and a scheduler used by the program running on the first processing element. However, Hennessy has taught an arithmetic logic unit (ALU) that obtains operands from, and writes results to, registers (see p.134 and 163). This is a basic flow of data in a processor datapath, which allows a processor to quickly obtain operands from fast register storage to perform various arithmetic (add, subtract, etc.) and logic (AND, OR, NOT, XOR, etc.) operations to generate results that can be stored quickly to fast register storage in response to arithmetic/logic instructions of a program. As a result, in order to quickly perform math and logic operations, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Vega to include an arithmetic logic unit that obtains data from (and writes data to) the registers of Vega. Furthermore, when registers include outputs/results of an ALU, this means result/output data has flowed from within the ALU to the appropriate destination register in response to an ALU instruction in the process being executed. Result data flow corresponding to an executed process is deemed process flow. As such, tracking register data is a tracking of process flow of data between ALU and register.
Referring to claim 2, Vega, as modified, has taught the method of claim 1, wherein the extracted microarchitectural information comprises information about one or more internal states of the first processing element (at least registers within the processor 102 hold information about the internal state(s) of the processor 102).
Referring to claim 4, Vega, as modified, has taught the method of claim 1, wherein the step of forwarding is performed as part of cloning the program on the second processing element (as the migration includes copying state data from the first element to the second element and moving the program from the first element to the second element, the migration is a cloning process).
Referring to claim 5, Vega, as modified, has taught the method of claim 1, wherein the step of forwarding is performed as part of migrating the program to the second processing element (as previously stated, Vega is performing migration, e.g. for load balancing, software upgrades to the first element, hardware maintenance, or disaster recovery (see paragraph 38)).
Referring to claim 6, Vega, as modified, has taught the method of claim 1, wherein instantiating the process comprises receiving the extracted microarchitectural information at a second operating system associated with the second processing element and transferring, by the second operating system, the extracted microarchitectural information to the second processing element (see FIG.1 and claim 10. The second operating system 104’ of the second element 102’ receives the extracted information and would store that information locally so as to replicate the first element’s state on the second element so that the migrated VM could resume seamlessly. For instance, register data from the first element would be transferred to the registers of the second element).
Referring to claim 8, Vega, as modified, has taught the method of claim 6, wherein the first processing element resides on a first host machine and the second processing element resides on a second host machine (see at least paragraphs 2 and 10).
Referring to claim 9, Vega, as modified, has taught the method of claim 8, wherein the first host machine serves a source node for a live migration event and the second processing element serves as a target node for the live migration event (see the abstract, last sentence, and paragraph 45. The migration occurs during operation and is not noticeable to the user, meaning the downtime associated with the migration is so low (less than 1 second), it is not noticed. This is live migration (applicant could see Wikipedia’s entry for “live migration” for more information)).
Referring to claim 10, Vega has taught a system, comprising:
a first processing element (FIG.1, 102, which includes a processor (e.g. FIG.1, 21) running a program (FIG.4, VM 108), the first processing element extracting microarchitectural context information associated with the program (from paragraph 41 and claims 10 and 14, device state and/or memory state comprising state of processor registers, a state of virtual hardware, and/or a state of working memory, is/are extracted), the extracted microarchitectural context information including information that tracks digital logic information of the program running on the first processing element (as stated, register data, for instance, is extracted. Registers track the input (operand) and result (output) information of the running program. All information in a digital logic system is digital logic information); and
a first operating system (FIG.4, OS 104) associated with the first processing element, the first operating system accessing the extracted microarchitectural context information (see claims 10 and 14, which set forth that the device state and memory state are transferred from first operating system (OS) 104. In order for OS 104 to perform the transfer, the state(s) must first be accessed by OS 104 (e.g. from internal registers)), and
wherein the first operating system communicates the extracted microarchitectural context information to a second processing element (see claim 10 and paragraph 41 and note that the information is forwarded to second element 102’);
Vega has not taught wherein the digital logic information comprises a process flow between two or more of an arithmetic logic unit, a register, a cache, and a scheduler used by the program running on the first processing element. However, Hennessy has taught an arithmetic logic unit (ALU) that obtains operands from, and writes results to, registers (see p.134 and 163). This is a basic flow of data in a processor datapath, which allows a processor to quickly obtain operands from fast register storage to perform various arithmetic (add, subtract, etc.) and logic (AND, OR, NOT, XOR, etc.) operations to generate results that can be stored quickly to fast register storage in response to arithmetic/logic instructions of a program. As a result, in order to quickly perform math and logic operations, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Vega to include an arithmetic logic unit that obtains data from (and writes data to) the registers of Vega. Furthermore, when registers include outputs/results of an ALU, this means result/output data has flowed from within the ALU to the appropriate destination register in response to an ALU instruction in the process being executed. Result data flow corresponding to an executed process is deemed process flow. As such, tracking register data is a tracking of process flow of data between ALU and register.
Referring to claim 11, Vega, as modified, has taught the system of claim 10, wherein the second processing element instantiates the program using the extracted microarchitectural context information (see FIG.1, and note that a process (VM 108’) is instantiated on element 102’ that uses the data transferred from element 102. This allows for migration of a VM (e.g. see abstract and paragraphs 10-11).
Claims 12, 14-16, and 18-19 are rejected for similar reasoning as claims 2, 4-6, and 18-19, respectively.
Claims 3, 7, 13, and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Vega in view of Hennessy and Vajapeyam, U.S. Patent Application Publication No. 2015/0234687 A1 (as cited by applicant).
Referring to claim 3, Vega, as modified, has taught the method of claim 2, but has not taught wherein the extracted microarchitectural information comprises information associated with a translation lookaside buffer (TLB) or a branch predictor buffer. However, Vajapeyam has taught transferring branch prediction and TLB information from a first element to a second element for purposes of process migration. See claims 1 and 8 as well as paragraphs 4 and 22. One of ordinary skill in the art would have recognized the benefit of transferring such information in Vajapeyam so as to more quickly and correctly predict branches and translate memory addresses for the migrated process. Otherwise, the TLB and branch predictor in the second element would have to slowly be built up over time, thereby delaying the benefits of branch prediction and address translation caching. As a result, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Vega such that the extracted microarchitectural information comprises information associated with a translation lookaside buffer (TLB) or a branch predictor buffer.
Referring to claim 7, Vega, as modified, has taught the method of claim 6, but has not taught wherein the first processing element and the second processing element reside on a first host machine. However, Vajapeyam has taught migration from one core to another in the same machine, where the migration involves extracting and forwarding similar data as Vega (e.g. register data) (see claims 1 and 6-8), and the migration is done for similar reasoning as Vega (e.g. load balancing) (see paragraphs 3-4). One of ordinary skill would have recognized that the invention of Vega could be practiced on a smaller scale, e.g. within a single multi-core processor, as opposed to between two separate physical host machines, so as to also be applicable in a different environment (e.g. a multi-core environment), where there is a reduced amount of hardware. As a result, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Vega’s migration to occur in a multi-core environment, where the first processing element (first core) and the second processing element (second core) reside on a first host machine.
Claims 13 and 17 are rejected for similar reasoning as claims 3 and 7, respectively.
Claims 3 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Vega in view of Hennessy and the examiner’s taking of Official Notice.
Referring to claim 3, Vega, as modified, has taught the method of claim 2, but has not taught wherein the extracted microarchitectural information comprises information associated with a translation lookaside buffer (TLB) or a branch predictor buffer. However, recall that Vega has taught transferring information in processor registers. The examiner asserts that storing a memory address in a register (e.g. for use by a load/store instruction) and/or storing a value that plays at least a part in determining whether a branch condition is met were/was well known in the art before applicant’s invention. As addresses are translated by a TLB, storing an address would be storing information associated with a TLB. As conditional branch instructions are predicted, storing information related to the branch would be storing information associated with a branch predictor buffer. Storing this information allows the system to provide addresses to read and write data from/to memory and carry out branching based on operands meeting some condition, two very well-known computing concepts. As a result, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Vega to store memory addresses to be translated and/or store values used to determine predictable branch conditions in the processor registers, such that the extracted microarchitectural information that is forwarded for migration comprises information associated with a translation lookaside buffer (TLB) or a branch predictor buffer. The examiner notes the breadth of “associated with” versus claiming information that is within a TLB or branch predictor, for instance.
Claim 13 is rejected using Official Notice for similar reasoning as claim 3.
Response to Arguments
On pages 9-10 of applicant’s response, applicant traverses the examiner’s interpretation under 35 U.S.C. 112(f), arguing that “processing element” is a structural limitation.
The examiner respectfully agrees. While a processor is structural, the term “element” is specifically called out in MPEP 2181(I)(A) as a non-structural generic placeholder for “means”. Inserting “processing” in front of it does not create a structural term. As such, the examiner’s interpretation is maintained. Applicant could alternatively claim a processing circuit if applicant does not wish to be limited under 112(f).
On pages 10-11 of applicant’s response, applicant persuasively argues the 112(a) rejection, which is now withdrawn.
The prior art arguments in applicant’s response are not persuasive for similar reasoning given in the Advisory Action.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to David J. Huisman whose telephone number is 571-272-4168. The examiner can normally be reached on Monday-Friday, 9:00 am-5:30 pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta, can be reached at 571-270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/David J. Huisman/Primary Examiner, Art Unit 2183
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