DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention I in the reply filed on 10/3/2025 is acknowledged.
Claims 13-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 10/3/2025.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 4, 5, and 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over KANG et al. (US PG Pub 2021/0210397, hereinafter Kang).
Regarding claim 1, figure 1A of Kang discloses a semiconductor package structure, comprising:
a plurality of package bodies stacked in a first direction, at least one of the plurality of package bodies comprises:
first interconnect structures (113) extending in the first direction, and
a plurality of sub package bodies stacked in the first direction, each of the plurality of sub package bodies (110a, 110b) comprising a molding body (140) and a device structure encapsulated in the molding body, wherein the device structure comprises a passive device (¶ 33).
Kang does not explicitly disclose at least one of a resistor, a capacitor, and an inductor.
However, the listed elements are well known in the art and it would have been obvious to include of them as said passive device based on required device functionality and design constraints.
Regarding claim 2, figure 1A of Kang discloses adjacent sub-package bodies are connected through direct bonding.
Kang does not explicitly disclose the device structure comprises an active device with the passive device, wherein the active device comprises at least one of an electronic tube, a transistor, and a memory chip.
However, the listed elements are well known in the art to be combined with passive devices and it would have been obvious to include of them as said passive device based on required device functionality and design constraints.
Regarding claim 4, figure 1A of Kang discloses first electrically connecting structures (117) are disposed between adjacent surfaces of adjacent package bodies, wherein the first electrically connecting structures comprise at least one of a solder ball, a metal bump, a bonding structure, and a conductive glue structure; and
a first insulating dielectric layer (120) is disposed between a plurality of the first electrically connecting structures in a plane perpendicular to the first direction.
Regarding claim 5, figure 1A of Kang does not explicitly disclose at least one of the plurality of package bodies further comprises a first redistribution layer and a second redistribution layer disposed in the first direction; the device structure included in the at least one of the plurality of package bodies is electrically connected with at least one of the first redistribution layer and the second redistribution layer; and the first interconnect structures extend in the first direction to the first redistribution layer and the second redistribution layer.
However, it would have been obvious to include redistribution layers in the package bodies for the purpose of routing signals to/from the devices.
Regarding claim 11, figure 1A of Kang does not explicitly disclose the memory chip comprises at least one of a nonvolatile memory chip and a volatile memory chip, the nonvolatile memory chip comprising at least one of a 3D NAND memory chip, a 3D NOR memory chip, a ferroelectric memory chip, and a phase change memory chip.
However, the listed elements are well known in the art to and it would have been obvious to include of them to form a memory device.
Regarding claim 12, figure 1A of Kang discloses the entire claimed invention as noted in the above rejections, including a controller; and a memory, wherein the controller is coupled to the memory to control data storage of the memory (¶ 36)
Allowable Subject Matter
Claims 3 and 6-10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to YU-HSI DAVID SUN whose telephone number is (571)270-5773. The examiner can normally be reached Mon-Fri 8am-4pm ET.
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/YU-HSI D SUN/Primary Examiner, Art Unit 2817