DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The Office acknowledges receipt on 2 February 2026 of Applicants’ amendments in which claims 1 and 4 are amended. The Office withdraws the indefiniteness rejection identified in the Office Communication dated 6 November 2025 in view of the amendments.
Response to Arguments
Applicants argue, in the penultimate paragraph of page 6 and with respect to claim 1, that Zhang, Zhang ‘252, and Zhang ‘579 all teach electrodes made of carbon nanotubes and, thus, do not teach the subject matter newly added to claim 1 whereby “the first top electrode and the second top electrode are formed by evaporating a gold (Au) layer with a thickness of nanometers by electron beam evaporation deposition.” Claim 1 is currently rejected over the combined teachings of Zhang, Zhang ‘252, and Zhang ‘579. Obviousness can be established by combining or modifying the teachings of the prior art to produce the claimed invention where there is some teaching, suggestion, or motivation to do so. MPEP §2143.01. As this principle applies to the present circumstance, Zhang teaches: (1) the first top electrode (104) and the second top electrode (102) are each a carbon nanotube [0015], (2) that carbon nanotube and gold are alternative materials for an electrode [0049], and (3) an electrode may have a thickness of 50 nm for the gold material [0049]. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Zhang’s inverter as modified by Zhang ‘252 and Zhang ‘579 based on the further teachings of Zhang – such that the first top electrode and the second top electrode are formed by a gold (Au) layer with a thickness of nanometers – because gold has higher conductivity than carbon nanotube. Moreover, all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Zhang) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). The recitation of “formed by evaporating … by electron beam evaporation deposition” is a product-by-process limitation that does not narrow the scope of the claimed invention. [E]ven though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. MPEP §2113(I).
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-13 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-13 of U.S. Patent No. 12,495,584 in view of Zhang et al. (US20180005825A1).
Instant Application
12,495,584
1. An inverter comprises:
a gate electrode;
a gate insulating layer, locating on the gate electrode;
a bottom electrode, locating on a surface of the gate insulating layer away from the gate electrode;
a two-dimensional semiconductor layer, locating on a surface of the bottom electrode away from the gate insulating layer and simultaneously covers a surface of the gate insulating layer; and
a first top electrode and a second top electrode, locating on a surface of the two-dimensional semiconductor layer away from the gate insulating layer, wherein the first top electrode and the second top electrode are formed by evaporating a gold (Au) layer with a thickness of nanometers by electron beam evaporation deposition
wherein the bottom electrode, the two-dimensional semiconductor layer, and the gate insulating layer form air gaps, and the air gaps are distributed at opposite sides of the bottom electrode, the gate electrode is configured to connect with a signal input terminal, the bottom electrode is configured to connect with a signal output terminal, the first top electrode is connected to a positive voltage of a power supply, and the second top electrode is connected to a ground terminal.
1. A logic gate device comprises:
a gate electrode;
a gate insulating layer, locating on the gate electrode;
a bottom electrode, locating on a surface of the gate insulating layer away from the gate electrode;
a two-dimensional semiconductor layer, locating on a surface of the bottom electrode away from the gate insulating layer and simultaneously covers the first surface of the gate insulating layer;
a first top electrode and a second top electrode, locating on a surface of the two-dimensional semiconductor layer away from the gate insulating layer;
wherein the bottom electrode, the two-dimensional semiconductor layer, and the gate insulating layer form air gaps, and the air gaps are distributed at opposite sides of the bottom electrode, the gate electrode is configured to connect a gate voltage, the first top electrode and the second top electrode are configured to connect with a signal input terminal, and the bottom electrode is configured to connect with a signal output terminal under a working voltage.
2. The inverter of claim 1, wherein a part of the two-dimensional semiconductor layer is in direct contact with a part of the gate insulating layer.
2. The logic gate device of claim 1, wherein a part of the two-dimensional semiconductor layer is in direct contact with a part of the gate insulating layer.
3. The inverter of claim 1, wherein the first top electrode and the second top electrode are located at two sides of the bottom electrode respectively.
3. The logic gate device of claim 1, wherein the first top electrode and the second electrode are located at two sides of the bottom electrode respectively.
4. The inverter of claim 1, wherein the first top electrode and the second top electrode are both disposed away from direct contact with the air gaps, and oppositely arranged on two sides of the air gaps respectively.
4. The logic gate device of claim 1, wherein the first top electrode and the second top electrode are both far away from the air gaps, and oppositely arranged on two sides of the air gaps respectively.
5. The inverter of claim 1, wherein when the first top electrode is in contact with the two-dimensional semiconductor layer at a first position, the two-dimensional semiconductor layer is also directly attached to the gate insulating layer at the first position.
5. The logic gate device of claim 1, wherein when the first top electrode is in contact with the two-dimensional semiconductor layer at a first position, the two-dimensional semiconductor layer is also directly attached to the gate insulating layer at the first position.
6. The inverter of claim 1, wherein when the second top electrode is in contact with the two-dimensional semiconductor layer at a second position, the two-dimensional semiconductor layer is also directly attached to the gate insulating layer at the second position.
6. The logic gate device of claim 1, wherein when the second top electrode is in contact with the two-dimensional semiconductor layer at a second position, the two-dimensional semiconductor layer is also directly attached to the gate insulating layer at the second position.
7. The inverter of claim 1, wherein the two-dimensional semiconductor layer comprises a material selected from a group consisting of black phosphorus, molybdenum telluride, tungsten selenide, and semiconducting carbon nanotubes.
7. The logic gate device of claim 1, wherein the two-dimensional semiconductor layer comprises a material selected from a group consisting of black phosphorus, molybdenum telluride, tungsten selenide, and semiconducting carbon nanotubes.
8. The inverter of claim 1, wherein the two-dimensional semiconductor layer is a freestanding structure.
8. The logic gate device of claim 1, wherein the two-dimensional semiconductor layer is a freestanding structure.
9. The inverter of claim 1, wherein a thickness of the two-dimensional semiconductor layer is in a range between 5 nanometers to 20 nanometers.
9. The logic gate device of claim 1, wherein a thickness of the two-dimensional semiconductor layer is in a range between 5 nanometers to 20 nanometers.
10. The inverter of claim 1, wherein a part structure of the two-dimensional semiconductor layer is overlapped on the surface of the bottom electrode away from the gate insulating layer, another part structure of the two-dimensional semiconductor layer is tiled on the surface of the gate insulating layer away from the gate electrode.
10. The logic gate device of claim 1, wherein a part structure of the two-dimensional semiconductor layer is overlapped on the surface of the bottom electrode away from the gate insulating layer, another part structure of the two-dimensional semiconductor layer is tiled on the surface of the gate insulating layer away from the gate electrode.
11. The inverter of claim 1, wherein the two-dimensional semiconductor layer is disposed in direct contact with the gate insulating layer and the bottom electrode at the same time.
11. The logic gate device of claim 1, wherein the two-dimensional semiconductor layer is disposed in direct contact with the gate insulating layer and the bottom electrode at the same time.
12. The inverter of claim 1, wherein the two-dimensional semiconductor layer is an integral structure, and the two-dimensional semiconductor layer extends from the surface of the bottom electrode to the surface of the gate insulating layer.
12. The logic gate device of claim 1, wherein the two-dimensional semiconductor layer is an integral structure, and the two-dimensional semiconductor layer extends from the surface of the bottom electrode to the surface of the gate insulating layer.
13. The inverter of claim 1, wherein the bottom electrode is disposed on middle of the gate insulating layer, and the two-dimensional semiconductor layer covers the bottom electrode to form the air gaps on the opposite sides of the bottom electrode.
13. The logic gate device of claim 1, wherein the bottom electrode is disposed on middle of the gate insulating layer, and the two-dimensional semiconductor layer covers the bottom electrode to form the air gaps on the opposite sides of the bottom electrode.
Claim 1 of the instant application differs from that of 12,495,584 by the recitation whereby the first top electrode and the second top electrode are formed by evaporating a gold (Au) layer with a thickness of nanometers by electron beam evaporation deposition.
However, Zhang teaches: (1) the first top electrode (104) and the second top electrode (102) are each a carbon nanotube [0015], (2) that carbon nanotube and gold are alternative materials for an electrode [0049], and (3) an electrode may have a thickness of 50 nm for the gold material [0049]. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Zhang’s inverter as modified by Zhang ‘252 and Zhang ‘579 based on the further teachings of Zhang – such that the first top electrode and the second top electrode are formed by a gold (Au) layer with a thickness of nanometers – because gold has higher conductivity than carbon nanotube. Moreover, all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Zhang) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known material based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07. The recitation of “formed by evaporating … by electron beam evaporation deposition” is a product-by-process limitation that does not narrow the scope of the claimed invention. [E]ven though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. MPEP §2113(I).
Claim 1 of the instant application further differs from that of 12,495,584 by the recitation whereby “the first top electrode is connected to a positive voltage of a power supply, and the second top electrode is connected to a ground terminal.” Zhang teaches in Fig. 3 and paragraph [0052] a first top electrode (104) is connected to a positive voltage (VDD) of a power supply (VDD-VSS), and a second top electrode (102) is connected to a ground terminal (VSS). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify 18/220,869’s inverter based on the teachings of Zhang – such that the first top electrode is connected to a positive voltage of a power supply, and the second top electrode is connected to a ground terminal – because all the claimed elements (e.g., electrodes, positive voltage and ground terminal of power supply) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Zhang) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A).
Claim 4 of the instant application further differs from that of 12,495,584 by the recitation whereby first top electrode and the second top electrode are both disposed away from direct contact with the air gaps, whereas claim 4 of 12,495,584 recites the first top electrode and the second top electrode are both far away from the air gaps, and oppositely arranged on two sides of the air gaps respectively. Ignoring the indefiniteness of the relative terminology of “far away” in claim 4 of 12,495,584, these claims essentially recite the same subject matter.
Claims 2, 3, and 513 of the instant application are otherwise the same as those of 18/220,869.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-4, 8, 10-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhang et al. (US20180005825A1) in view of Zhang et al. (US20180006252A1) and Zhang et al. (US20180342579A1).
Regarding claim 1, Zhang teaches in Figs. 3 and 4 an inverter comprises:
a gate electrode (201);
a gate insulating layer (205), locating on the gate electrode (201);
a bottom electrode (108), locating on a surface of the gate insulating layer (205) away from the gate electrode (201);
a two-dimensional semiconductor layer (106) covers a surface of the gate insulating layer (205); and
a first top electrode (104) and a second top electrode (102),
the gate electrode (201) is configured to connect with a signal input terminal (Vin), the bottom electrode (108) is configured to connect with a signal output terminal (Vout), the first top electrode (104) is connected to a positive voltage (VDD) of a power supply (VDD-VSS), and the second top electrode (102) is connected to a ground terminal (VSS) {see Examiner’s Note, below}.
Zhang does not teach:
the two-dimensional semiconductor layer, locating on a surface of the bottom electrode away from the gate insulating layer;
the first top electrode and the second top electrode, locating on a surface of the two-dimensional semiconductor layer away from the gate insulating layer,
wherein the bottom electrode, the two-dimensional semiconductor layer, and the gate insulating layer form air gaps, and the air gaps are distributed at opposite sides of the bottom electrode.
However, Zhang teaches in Fig. 4 and paragraph [0052] that the structure illustrated by Fig. 3 forms the circuit equivalent of a complementary combination of a PMOS transistor and an NMOS transistor configured to operate as an inverter. And Zhang further teaches in paragraph [0052] that both of the PMOS and NMOS transistors use the same 2-D semiconductor layer and the same material for each S/D electrode.
In an analogous art, Zhang ‘252 teaches in Fig. 4 a semiconductor transistor (200) in which: (1) a 2-D semiconductor layer (104) is disposed between a drain electrode (204) and each of a source electrode (202), a gate insulator (210), and a gate electrode (208) and (2) the source electrode (202) is disposed between the 2-D semiconductor layer (104) and the gate insulator (210). Zhang ‘252’s ordering of the source electrode (202), the 2-D semiconductor layer (104), and the drain electrode (204) with respect to the combination of the gate electrode (208) and gate insulator (210) is the opposite (e.g., upside down) ordering to that of Zhang’s PMOS transistor in Fig. 4.
In an analogous art, Zhang ‘579 teaches in Fig. 4 a semiconductor transistor (200) in which: (1) a 2-D semiconductor layer (104) is disposed between a source electrode (204) and each of a drain electrode (202), a gate insulator (210), and a gate electrode (208) and (2) the drain electrode (202) is disposed between the 2-D semiconductor layer (104) and the gate insulator (210). Zhang ‘579’s ordering of the drain electrode (202), the 2-D semiconductor layer (104), and the source electrode (204) with respect to the combination of the gate electrode (208) and gate insulator (210) is the opposite (e.g., upside down) ordering to that of Zhang’s NMOS transistor in Fig. 4.
Thus: (A) Zhang and Zhang ‘252 teach alternative orderings of layers (e.g., for the drain electrode, 2-D semiconductor layer, and source electrode) with respect to the combination of the gate electrode (208) and gate insulator (210) for a transistor that may be used as Zhang’s PMOS transistor and (B) Zhang and Zhang ‘579 teach alternative orderings of layers (e.g., for the drain electrode, 2-D semiconductor layer, and source electrode) with respect to the combination of the gate electrode (208) and gate insulator (210) for a transistor that may be used as Zhang’s NMOS transistor. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Zhang’s inverter based on the teachings of Zhang ‘252 and Zhang ‘579 – such that Zhang’s PMOS transistor configuration is modified according to Zhang ‘252’s ordering of layers and Zhang’s NMOS transistor configuration is modified according to Zhang ‘579’s orderings of layers – because a person of ordinary skill has good reason to pursue the known options within his or her technical grasp. MPEP ¶2143((I)(E). Moreover, all the claimed elements (e.g., two-dimensional semiconductor layer, electrodes) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by of Zhang ‘252 and Zhang ‘579) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, a rearrangement of parts that does not modify the operation of a device is an obvious matter of design choice. MPEP §2144.04(VI)(C). Still further, the reversal of parts is an obvious modification. MPEP §2144.04(VI)(A). According to this modification, Zhang’s nano-heterostructure 100 – comprising the two-dimensional semiconductor layer (106) and the three electrodes (102), (104), (108) – would be essentially flipped upside-down on the top surface of the gate insulating layer (205) with the series connected source and drain of the two transistors (PMOS, NMOS) sharing a common electrode.
Consequences of the modifications are that: (I) the modified two-dimensional semiconductor layer (106’) is located on a surface of the modified bottom electrode (108’) away from the gate insulating layer (205), (II) the modified first top electrode (104’) and the modified second top electrode (102’) are located on a surface of the two-dimensional semiconductor layer (106’) away from the gate insulating layer (205), and (III) the modified bottom electrode (108’), the modified two-dimensional semiconductor layer (106’), and the gate insulating layer (205) form air gaps, and the air gaps are distributed at opposite sides of the modified bottom electrode (108’) {where ’ indicates the modified feature; e.g., 106’ indicates the modified two-dimensional semiconductor layer}.
Zhang as modified by Zhang ‘252 and Zhang ‘579 above does not teach the first top electrode and the second top electrode are formed by evaporating a gold (Au) layer with a thickness of nanometers by electron beam evaporation deposition.
However, Zhang teaches: (1) the first top electrode (104) and the second top electrode (102) are each a carbon nanotube [0015], (2) that carbon nanotube and gold are alternative materials for an electrode [0049], and (3) an electrode may have a thickness of 50 nm for the gold material [0049]. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Zhang’s inverter as modified by Zhang ‘252 and Zhang ‘579 based on the further teachings of Zhang – such that the first top electrode and the second top electrode are formed by a gold (Au) layer with a thickness of nanometers – because gold has higher conductivity than carbon nanotube. Moreover, all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Zhang) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known material based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07. The recitation of “formed by evaporating … by electron beam evaporation deposition” is a product-by-process limitation that does not narrow the scope of the claimed invention. [E]ven though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. MPEP §2113(I).
Examiner’s Note: Each recitation of “is configured to connect with” is directed to a manner in which the claimed subject matter is intended to be employed and, accordingly, does not structurally distinguish the claimed invention from the prior art. MPEP §2114(II) – a “recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus” if the prior art apparatus teaches all the structural limitations of the claim. Moreover, the corresponding features of the applied references are similarly configured to connect.
Regarding claim 2, Zhang as modified by Zhang ‘252 and Zhang ‘579 teaches the inverter of claim 1, but Zhang does not teach wherein a part of the two-dimensional semiconductor layer is in direct contact with a part of the gate insulating layer.
However, a consequence of the modifications of Zhang’s inverter identified with respect to claim 1 is that a part of the modified two-dimensional semiconductor layer (106’) is in direct contact with a part of the gate insulating layer (205) {where ’ indicates the modified feature; e.g., 106’ indicates the modified two-dimensional semiconductor layer}.
Regarding claim 3, Zhang as modified by Zhang ‘252 and Zhang ‘579 teaches the inverter of claim 1, and Zhang further teaches wherein the first top electrode (104) and the second top electrode (102) are located at two sides of the bottom electrode (108) respectively {Each of electrodes 102 and 104 has portions on each side of electrode 108}.
Regarding claim 4, Zhang as modified by Zhang ‘252 and Zhang ‘579 teaches the inverter of claim 1, but Zhang does not teach wherein the first top electrode and the second top electrode are both disposed away from direct contact with the air gaps and oppositely arranged on two sides of the air gaps respectively.
However, consequences of the modifications of Zhang’s inverter identified with respect to claim 1 are that the modified first top electrode (104’) and the modified second top electrode (102’) are both disposed away from direct contact with the air gaps, and oppositely arranged on two sides of the air gaps respectively {Each of electrodes 102 and 104 are arranged on opposite sides of the air gaps; where ’ indicates the modified feature; e.g., 106’ indicates the modified two-dimensional semiconductor layer}.
Regarding claim 8, Zhang as modified by Zhang ‘252 and Zhang ‘579 teaches the inverter of claim 1, and Zhang further teaches wherein the two-dimensional semiconductor layer (106) is a freestanding structure {Applicants’ specification describes “freestanding” as not requiring a substrate for support}.
Regarding claim 10, Zhang as modified by Zhang ‘252 and Zhang ‘579 teaches the inverter of claim 1, but Zhang does not teach wherein a part structure of the two-dimensional semiconductor layer is overlapped on the surface of the bottom electrode away from the gate insulating layer, another part structure of the two-dimensional semiconductor layer is tiled on the surface of the gate insulating layer away from the gate electrode.
However, consequences of the modifications of Zhang’s inverter identified with respect to claim 1 are that a part structure of the modified two-dimensional semiconductor layer (106’) is overlapped on the surface of the modified bottom electrode (108’) away from the gate insulating layer (205), another part structure of the modified two-dimensional semiconductor layer (106’) is tiled on the surface of the gate insulating layer (205) away from the gate electrode (201) {where ’ indicates the modified feature; e.g., 106’ indicates the modified two-dimensional semiconductor layer}.
Regarding claim 11, Zhang as modified by Zhang ‘252 and Zhang ‘579 teaches the inverter of claim 1, but Zhang does not necessarily teach wherein the two-dimensional semiconductor layer is disposed in direct contact with the gate insulating layer and the bottom electrode at the same time.
However, a consequence of the modifications of Zhang’s inverter identified with respect to claim 1 is that the modified two-dimensional semiconductor layer (106’) is disposed in direct contact with the gate insulating layer (205) and the modified bottom electrode (108’) at the same time {where ’ indicates the modified feature; e.g., 106’ indicates the modified two-dimensional semiconductor layer}.
Regarding claim 12, Zhang as modified by Zhang ‘252 and Zhang ‘579 teaches the inverter of claim 1, but Zhang does not necessarily teach wherein the two-dimensional semiconductor layer is an integral structure, and the two-dimensional semiconductor layer extends from the surface of the bottom electrode to the surface of the gate insulating layer.
However, consequences of the modifications of Zhang’s inverter identified with respect to claim 1 are that the modified two-dimensional semiconductor layer (106’) is an integral structure, and the modified two-dimensional semiconductor layer (106’) extends from the surface of the modified bottom electrode (108’) to the surface of the gate insulating layer (205) {where ’ indicates the modified feature; e.g., 106’ indicates the modified two-dimensional semiconductor layer}.
Regarding claim 13, Zhang as modified by Zhang ‘252 and Zhang ‘579 teaches the inverter of claim 1, but Zhang does not necessarily teach wherein the bottom electrode is disposed on middle of the gate insulating layer, and the two-dimensional semiconductor layer covers the bottom electrode to form the air gaps on the opposite sides of the bottom electrode.
However, consequences of the modifications of Zhang’s inverter identified with respect to claim 1 are that the modified bottom electrode (108’) is disposed on middle of the gate insulating layer (205), and the modified two-dimensional semiconductor layer (106’) covers the modified bottom electrode (108’) to form the air gaps on the opposite sides of the modified bottom electrode (108’) {where ’ indicates the modified feature; e.g., 106’ indicates the modified two-dimensional semiconductor layer}.
Claim(s) 5, 6, and 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhang in view of Zhang ‘252 and Zhang ‘579 as applied to claim 1 above, and further in view of Heo et al. (US20150137075A1).
Regarding claim 5, Zhang as modified by Zhang ‘252 and Zhang ‘579 teaches the inverter of claim 1, but Zhang does not teach wherein when the first top electrode is in contact with the two-dimensional semiconductor layer at a first position, the two-dimensional semiconductor layer is also directly attached to the gate insulating layer at the first position.
In an analogous art pertaining to a four-terminal CMOS inverter employing a 2-D semiconductor material, which inverter is similar to that claimed in the instant application, Heo teaches in Fig. 1 and paragraph [0069] an electrode (E30) that is electrically connected to a Vout terminal and disposed between, without overlapping, two electrodes (E10, E20) electrically connected to opposite polarities (VDD, VS) of a power supply. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Zhang’s inverter as modified by Zhang ‘252 and Zhang ‘579 based on the teachings of Heo – such that Zhang’s bottom electrode is modified as taught by Heo so as to not overlap Zhang’s first and second top electrodes – because all the claimed elements (e.g., electrodes) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Heo) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). A consequence of this modification is that when the modified first top electrode (104’) is in contact with the modified two-dimensional semiconductor layer (106’) at a first position, the modified two-dimensional semiconductor layer (106’) is also directly attached to the gate insulating layer (205) at the first position {where ’ indicates the modified feature; e.g., 106’ indicates the modified two-dimensional semiconductor layer}.
Regarding claim 6, Zhang as modified by Zhang ‘252 and Zhang ‘579 teaches the inverter of claim 1, but Zhang does not teach wherein when the second top electrode is in contact with the two-dimensional semiconductor layer at a second position, the two-dimensional semiconductor layer is also directly attached to the gate insulating layer at the second position.
Heo teaches in Fig. 1 and paragraph [0069] an electrode (E30) that is electrically connected to a Vout terminal and disposed between, without overlapping, two electrodes (E10, E20) electrically connected to opposite polarities (VDD, VS) of a power supply. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Zhang’s inverter as modified by Zhang ‘252 and Zhang ‘579 based on the teachings of Heo – such that Zhang’s bottom electrode is modified as taught by Heo so as to not overlap Zhang’s first and second top electrodes – because all the claimed elements (e.g., electrodes) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Heo) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). A consequence of this modification is that when the modified second top electrode (102’) is in contact with the modified two-dimensional semiconductor layer (106’) at a second position, the modified two-dimensional semiconductor layer (106’) is also directly attached to the gate insulating layer (205) at the second position {where ’ indicates the modified feature; e.g., 106’ indicates the modified two-dimensional semiconductor layer}.
Regarding claim 9, Zhang as modified by Zhang ‘252 and Zhang ‘579 teaches the inverter of claim 1, but Zhang does not teach wherein a thickness of the two-dimensional semiconductor layer is in a range between 5 nanometers to 20 nanometers.
Heo teaches in Fig. 1 and paragraph [0080] a thickness of the two-dimensional semiconductor layer is smaller than or equal to about 10 nm. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Zhang’s inverter as modified by Zhang ‘252 and Zhang ‘579 based on the teachings of Heo – such that a thickness of the two-dimensional semiconductor layer is in a range between 5 nanometers to 20 nanometers – so the inverter including the layers may become flexible and transparent. Heo ¶0080. In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. MPEP §2144.05(I).
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhang in view of Zhang ‘252 and Zhang ‘579 as applied to claim 1 above, and further in view of Seol et al. (US20240021679A1).
Regarding claim 7, Zhang as modified by Zhang ‘252 and Zhang ‘579 teaches the inverter of claim 1, but Zhang does not teach wherein the two-dimensional semiconductor layer comprises a material selected from a group consisting of black phosphorus, molybdenum telluride, tungsten selenide, and semiconducting carbon nanotubes.
In an analogous art, Seol teaches in Fig. 1 and paragraph [0092] a two-dimensional semiconductor layer (110) comprises a material of black phosphorus. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Zhang’s inverter as modified by Zhang ‘252 and Zhang ‘579 based on the teachings of Seol – such that the two-dimensional semiconductor layer comprises a material selected from a group consisting of black phosphorus, molybdenum telluride, tungsten selenide, and semiconducting carbon nanotubes – because [t]he selection of a known material based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Conclusion
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/D.W.W./Examiner, Art Unit 2891
/MATTHEW C LANDAU/Supervisory Patent Examiner, Art Unit 2891