DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 8, 10, and 12-15 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al (US Publication 20230145610) in view of Pietambaram et al (20230197697).
Regarding claim 8, Chen teaches a manufacturing method for a multichip interconnecting packaging structure, the method comprising:
preparing a glass frame having a first surface and a second surface that are opposite to each other, and forming, on the glass frame, a first via penetrating through the glass frame and a cavity penetrating through the glass frame (Fig. 4a, glass frame 110, para 56, via 120, cavity 130);
applying an adhesive layer on the first surface of the glass frame and mounting a chip connecting device on the adhesive layer in a cavity of the glass frame, wherein terminals of the chip connecting device are attached to the adhesive layer (Fig. 4b, adhesive layer 150, chip 140 and terminals 141);
filling and forming a first insulating layer in the cavity so as to package the chip connecting device (Fig. 4c, insulating layer 160), wherein the chip connecting device has a height less than the cavity (Fig. 4c, para 10);
removing the adhesive layer (para 69) and forming a first line layer and a second line layer respectively on the first surface and the second surface of the glass frame, and forming a first via post in the first via so that the first line layer and the second line layer are in conductive communication with each other through the first via post (Fig. 4g, first line layer 131, second line layer 132, and via 120);
Chen does not teach mounting a first chip and a second chip to the first line layer, wherein the first chip and the second chip are respectively connected to the chip connecting device through the first line layer to interconnect the first chip with the second chip
Pietambaram teaches mounting a first chip and a second chip to the first line layer, wherein the first chip and the second chip are respectively connected to the chip connecting device through the first line layer to interconnect the first chip with the second chip (Fig. 3N, first chip 114-3, second chip 114-5, para 59).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Chen to include mounting a first and second chip to the first line layer as taught by Pietambaram in order to improve the manufacturing principles and operability of the device.
Regarding claim 10, Chen as modified teaches the limitations of claim 8 upon which claim 10 depends.
Chen teaches wherein the filling and forming of the first insulating layer comprises:
laminating a first insulating layer on the second surface of the glass frame so that the first insulating layer fills the cavity and covers the chip connecting device (Fig. 4c, para 66); and
exposing and developing the first insulating layer to leave only the first insulating layer in the cavity so that the first insulating layer is coplanar with the second surface (Fig. 4c, para 67).
Regarding claim 12, Chen as modified teaches the limitations of claim 8 upon which claim 12 depends.
Chen teaches wherein the forming of the first line layer comprises: forming a first pad connected to the first via post and a second pad connected to the chip connecting device (Fig. 4g, 120 a and 120c, para 73).
Regarding claims 13-15, Chen as modified teaches the limitations of claim 8 upon which claim 13 depends.
Chen does not teach:
[claim 13] laminating a second insulating layer on a surface of the second line layer;
forming a second via post running through the second insulating layer on the second insulating layer; and
forming a third line layer on the second insulating layer, so that the third line layer is electrically connected to the second line layer through the second via post.
[claim 14] further comprising: laminating a third insulating layer on the surface of the third line layer; forming a third via post running through the third insulating layer on the third insulating layer; and forming a fourth line layer on the third insulating layer, so that the fourth line layer is electrically connected to the third line layer through the third via post.
[claim 15] electrically connecting the fourth line layer to a substrate such that the multichip interconnecting packaging structure is interconnected with the substrate.
Pietambaram teaches:
[claim 13] laminating a second insulating layer on a surface of the second line layer (Fig. 1A, second insulating layer 127 on contacts 144, para 61-69);
forming a second via post running through the second insulating layer on the second insulating layer (Fig. 1A, 150 running through 127, para 61-69); and
forming a third line layer on the second insulating layer, so that the third line layer is electrically connected to the second line layer through the second via post (Fig. 1A, 146 on 127 so that 146 is electrically connected to 144 through 150).
[claim 14] further comprising: laminating a third insulating layer on the surface of the third line layer; forming a third via post running through the third insulating layer on the third insulating layer; and forming a fourth line layer on the third insulating layer, so that the fourth line layer is electrically connected to the third line layer through the third via post (para 28, "the package substrate 102 may be a set of redistribution layers formed on a panel carrier by laminating or spinning on a dielectric material, and creating conductive vias and lines by laser drilling or ablation and plating").
[claim 15] electrically connecting the fourth line layer to a substrate such that the multichip interconnecting packaging structure is interconnected with the substrate (para 28, "the package substrate 102 may be a set of redistribution layers formed on a panel carrier by laminating or spinning on a dielectric material, and creating conductive vias and lines by laser drilling or ablation and plating").
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Chen to include the additional line and insulation layers and via as taught by Pietambaram in order to improve the interconnectivity and reliability of the device.
Response to Arguments
Applicant’s arguments with respect to claim(s) 8 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NICHOLAS HUTSON whose telephone number is (571)270-1750. The examiner can normally be reached Mon-Fri 8am-5pm.
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/NICHOLAS LELAND HUTSON/ Examiner, Art Unit 2818
/JEFF W NATALINI/ Supervisory Patent Examiner, Art Unit 2818